WO1999019875A3 - Apparatus and method for pipelined memory operations - Google Patents
Apparatus and method for pipelined memory operations Download PDFInfo
- Publication number
- WO1999019875A3 WO1999019875A3 PCT/US1998/021458 US9821458W WO9919875A3 WO 1999019875 A3 WO1999019875 A3 WO 1999019875A3 US 9821458 W US9821458 W US 9821458W WO 9919875 A3 WO9919875 A3 WO 9919875A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- memory device
- operation units
- memory core
- units
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98951040A EP1019912A2 (en) | 1997-10-10 | 1998-09-09 | Apparatus and method for pipelined memory operations |
AU96933/98A AU9693398A (en) | 1997-10-10 | 1998-09-09 | Apparatus and method for pipelined memory operations |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US6168297P | 1997-10-10 | 1997-10-10 | |
US60/061,682 | 1997-10-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1999019875A2 WO1999019875A2 (en) | 1999-04-22 |
WO1999019875A3 true WO1999019875A3 (en) | 1999-09-02 |
Family
ID=22037421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/021458 WO1999019875A2 (en) | 1997-10-10 | 1998-09-09 | Apparatus and method for pipelined memory operations |
Country Status (4)
Country | Link |
---|---|
US (5) | US6356975B1 (en) |
EP (3) | EP1981033B1 (en) |
AU (1) | AU9693398A (en) |
WO (1) | WO1999019875A2 (en) |
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KR100318266B1 (en) * | 1999-06-28 | 2001-12-24 | 박종섭 | output data compression method and packet command driving type memory device |
US6850446B1 (en) * | 2001-12-06 | 2005-02-01 | Virage Logic Corporation | Memory cell sensing with low noise generation |
JP2004086682A (en) * | 2002-08-28 | 2004-03-18 | Fujitsu Ltd | Functional block design method and functional block design device |
US7197662B2 (en) * | 2002-10-31 | 2007-03-27 | Ring Technology Enterprises, Llc | Methods and systems for a storage system |
US7415565B2 (en) * | 2002-10-31 | 2008-08-19 | Ring Technology Enterprises, Llc | Methods and systems for a storage system with a program-controlled switch for routing data |
US7707351B2 (en) * | 2002-10-31 | 2010-04-27 | Ring Technology Enterprises Of Texas, Llc | Methods and systems for an identifier-based memory section |
US6879526B2 (en) * | 2002-10-31 | 2005-04-12 | Ring Technology Enterprises Llc | Methods and apparatus for improved memory access |
GB2399899B (en) * | 2003-03-27 | 2005-06-22 | Micron Technology Inc | Active memory command engine and method |
US7073023B2 (en) * | 2003-05-05 | 2006-07-04 | Lsi Logic Corporation | Method for minimizing RAID 0 data transfer rate variability |
US7280428B2 (en) | 2004-09-30 | 2007-10-09 | Rambus Inc. | Multi-column addressing mode memory system including an integrated circuit memory device |
US8595459B2 (en) * | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
US7499307B2 (en) * | 2005-06-24 | 2009-03-03 | Mosys, Inc. | Scalable embedded DRAM array |
US7274618B2 (en) * | 2005-06-24 | 2007-09-25 | Monolithic System Technology, Inc. | Word line driver for DRAM embedded in a logic process |
US7660183B2 (en) | 2005-08-01 | 2010-02-09 | Rambus Inc. | Low power memory device |
US20070260841A1 (en) | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
US20090182977A1 (en) * | 2008-01-16 | 2009-07-16 | S. Aqua Semiconductor Llc | Cascaded memory arrangement |
US8477734B2 (en) * | 2008-03-25 | 2013-07-02 | Qualcomm Incorporated | Reporting of ACK and CQI information in a wireless communication system |
US20100037020A1 (en) * | 2008-08-07 | 2010-02-11 | Seagate Technology Llc | Pipelined memory access method and architecture therefore |
JP2012511789A (en) * | 2008-12-09 | 2012-05-24 | ラムバス・インコーポレーテッド | Non-volatile memory device for parallel and pipelined memory operation |
JP5752686B2 (en) * | 2009-08-20 | 2015-07-22 | ラムバス・インコーポレーテッド | Atomic memory device |
US8599886B2 (en) * | 2010-08-26 | 2013-12-03 | Qualcomm Incorporated | Methods and apparatus for reducing transfer qualifier signaling on a two-channel bus |
US9268719B2 (en) | 2011-08-05 | 2016-02-23 | Rambus Inc. | Memory signal buffers and modules supporting variable access granularity |
KR20150086718A (en) * | 2014-01-20 | 2015-07-29 | 삼성전자주식회사 | Method and Apparatus for processing data by pipeline using memory |
CN109313918B (en) | 2016-09-02 | 2023-04-28 | 拉姆伯斯公司 | Memory component with input/output data rate alignment |
TWI707364B (en) * | 2017-05-24 | 2020-10-11 | 華邦電子股份有限公司 | Memory storage apparatus and an operating method thereof |
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WO1994024628A1 (en) * | 1993-04-22 | 1994-10-27 | Analog Devices, Inc. | Multi-phase multi-access pipeline memory system |
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-
1998
- 1998-09-09 WO PCT/US1998/021458 patent/WO1999019875A2/en not_active Application Discontinuation
- 1998-09-09 EP EP08153150A patent/EP1981033B1/en not_active Expired - Lifetime
- 1998-09-09 EP EP09161662A patent/EP2105841A1/en not_active Withdrawn
- 1998-09-09 AU AU96933/98A patent/AU9693398A/en not_active Abandoned
- 1998-09-09 EP EP98951040A patent/EP1019912A2/en not_active Withdrawn
- 1998-10-09 US US09/169,526 patent/US6356975B1/en not_active Expired - Fee Related
-
2002
- 2002-01-18 US US10/053,632 patent/US6718431B2/en not_active Expired - Fee Related
-
2004
- 2004-04-02 US US10/817,781 patent/US6963956B2/en not_active Expired - Fee Related
-
2005
- 2005-11-08 US US11/270,251 patent/US7330951B2/en not_active Expired - Fee Related
-
2007
- 2007-02-14 US US11/675,054 patent/US7353357B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0515165A1 (en) * | 1991-05-20 | 1992-11-25 | Fujitsu Limited | A Memory access device |
WO1994012935A1 (en) * | 1992-11-25 | 1994-06-09 | Ast Research, Inc. | Pipelined data ordering system |
EP0617364A2 (en) * | 1993-03-22 | 1994-09-28 | Compaq Computer Corporation | Computer system which overrides write protection status during execution in system management mode |
WO1994024628A1 (en) * | 1993-04-22 | 1994-10-27 | Analog Devices, Inc. | Multi-phase multi-access pipeline memory system |
Also Published As
Publication number | Publication date |
---|---|
US20020095560A1 (en) | 2002-07-18 |
US20060059299A1 (en) | 2006-03-16 |
US20040193788A1 (en) | 2004-09-30 |
EP1981033A1 (en) | 2008-10-15 |
AU9693398A (en) | 1999-05-03 |
US7330951B2 (en) | 2008-02-12 |
US6963956B2 (en) | 2005-11-08 |
EP1019912A2 (en) | 2000-07-19 |
WO1999019875A2 (en) | 1999-04-22 |
EP2105841A1 (en) | 2009-09-30 |
US6718431B2 (en) | 2004-04-06 |
US6356975B1 (en) | 2002-03-12 |
US7353357B2 (en) | 2008-04-01 |
EP1981033B1 (en) | 2011-08-24 |
US20070140035A1 (en) | 2007-06-21 |
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