WO1999019875A3 - Apparatus and method for pipelined memory operations - Google Patents

Apparatus and method for pipelined memory operations Download PDF

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Publication number
WO1999019875A3
WO1999019875A3 PCT/US1998/021458 US9821458W WO9919875A3 WO 1999019875 A3 WO1999019875 A3 WO 1999019875A3 US 9821458 W US9821458 W US 9821458W WO 9919875 A3 WO9919875 A3 WO 9919875A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
memory device
operation units
memory core
units
Prior art date
Application number
PCT/US1998/021458
Other languages
French (fr)
Other versions
WO1999019875A2 (en
Inventor
Richard M Barth
Ely K Tsern
Mark A Horowitz
Donald C Stark
Craig E Hampel
Frederick A Ware
John B Dillon
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22037421&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1999019875(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rambus Inc filed Critical Rambus Inc
Priority to EP98951040A priority Critical patent/EP1019912A2/en
Priority to AU96933/98A priority patent/AU9693398A/en
Publication of WO1999019875A2 publication Critical patent/WO1999019875A2/en
Publication of WO1999019875A3 publication Critical patent/WO1999019875A3/en

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.
PCT/US1998/021458 1997-10-10 1998-09-09 Apparatus and method for pipelined memory operations WO1999019875A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP98951040A EP1019912A2 (en) 1997-10-10 1998-09-09 Apparatus and method for pipelined memory operations
AU96933/98A AU9693398A (en) 1997-10-10 1998-09-09 Apparatus and method for pipelined memory operations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6168297P 1997-10-10 1997-10-10
US60/061,682 1997-10-10

Publications (2)

Publication Number Publication Date
WO1999019875A2 WO1999019875A2 (en) 1999-04-22
WO1999019875A3 true WO1999019875A3 (en) 1999-09-02

Family

ID=22037421

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/021458 WO1999019875A2 (en) 1997-10-10 1998-09-09 Apparatus and method for pipelined memory operations

Country Status (4)

Country Link
US (5) US6356975B1 (en)
EP (3) EP1981033B1 (en)
AU (1) AU9693398A (en)
WO (1) WO1999019875A2 (en)

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US7197662B2 (en) * 2002-10-31 2007-03-27 Ring Technology Enterprises, Llc Methods and systems for a storage system
US7415565B2 (en) * 2002-10-31 2008-08-19 Ring Technology Enterprises, Llc Methods and systems for a storage system with a program-controlled switch for routing data
US7707351B2 (en) * 2002-10-31 2010-04-27 Ring Technology Enterprises Of Texas, Llc Methods and systems for an identifier-based memory section
US6879526B2 (en) * 2002-10-31 2005-04-12 Ring Technology Enterprises Llc Methods and apparatus for improved memory access
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US8595459B2 (en) * 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US7499307B2 (en) * 2005-06-24 2009-03-03 Mosys, Inc. Scalable embedded DRAM array
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US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US20090182977A1 (en) * 2008-01-16 2009-07-16 S. Aqua Semiconductor Llc Cascaded memory arrangement
US8477734B2 (en) * 2008-03-25 2013-07-02 Qualcomm Incorporated Reporting of ACK and CQI information in a wireless communication system
US20100037020A1 (en) * 2008-08-07 2010-02-11 Seagate Technology Llc Pipelined memory access method and architecture therefore
JP2012511789A (en) * 2008-12-09 2012-05-24 ラムバス・インコーポレーテッド Non-volatile memory device for parallel and pipelined memory operation
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Also Published As

Publication number Publication date
US20020095560A1 (en) 2002-07-18
US20060059299A1 (en) 2006-03-16
US20040193788A1 (en) 2004-09-30
EP1981033A1 (en) 2008-10-15
AU9693398A (en) 1999-05-03
US7330951B2 (en) 2008-02-12
US6963956B2 (en) 2005-11-08
EP1019912A2 (en) 2000-07-19
WO1999019875A2 (en) 1999-04-22
EP2105841A1 (en) 2009-09-30
US6718431B2 (en) 2004-04-06
US6356975B1 (en) 2002-03-12
US7353357B2 (en) 2008-04-01
EP1981033B1 (en) 2011-08-24
US20070140035A1 (en) 2007-06-21

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