WO1999017455A1 - Apparatus and method for aligning trellis demapped data - Google Patents

Apparatus and method for aligning trellis demapped data Download PDF

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Publication number
WO1999017455A1
WO1999017455A1 PCT/IB1998/001852 IB9801852W WO9917455A1 WO 1999017455 A1 WO1999017455 A1 WO 1999017455A1 IB 9801852 W IB9801852 W IB 9801852W WO 9917455 A1 WO9917455 A1 WO 9917455A1
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WO
WIPO (PCT)
Prior art keywords
signal
trellis
receiver
demapped
output
Prior art date
Application number
PCT/IB1998/001852
Other languages
French (fr)
Inventor
Kumar Ramaswamy
Original Assignee
Thomson Multimedia, S.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US94238097A priority Critical
Priority to US08/942,380 priority
Application filed by Thomson Multimedia, S.A. filed Critical Thomson Multimedia, S.A.
Publication of WO1999017455A1 publication Critical patent/WO1999017455A1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0054Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/256Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with trellis coding, e.g. with convolutional codes and TCM
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3776Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using a re-encoding step during the decoding process
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • H04L1/0054Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Abstract

An apparatus and method for aligning a trellis demapped data stream with a data stream output from a rate 1/2 Viterbi decoder can be implemented at either the transmitter or the receiver. When implemented at the receiver, the present invention provides a Viterbi decoder for providing output of a Viterbi decoded signal. A reencoder reencodes the Viterbi decoded signal to provide output of a reencoded signal. A trellis demapper demaps the reencoded signal to provide output of a trellis demapped signal. A delay unit receives and delays output of the Viterbi decoded signal so that the delayed Viterbi decoded signal exhibits a predetermined temporal alignment with respect to the trellis demapped signal. In this manner, efficient, synchronized system operation is achieved.

Description

APPARATUS AND METHOD FOR ALIGNING TRELLIS

DEMAPPED DATA

FIELD OF THE INVENTION

The present invention generally relates to digital signal processing in a multi¬

channel, multi-point distribution system, and more particularly, to an apparatus and

method for aligning trellis demapped data with data output from a rate 1/2 Viterbi

decoder.

BACKGROUND OF THE INVENTION

Known in the art is the use of forward-error-correction that includes convolutional

encoding in the transmission of encoded digital data over a noisy channel from a

transmitter to a receiver. The Viterbi algorithm is commonly used to decode a

convo rationally encoded sequence of bits transmitted over a noisy channel. In particular,

the Viterbi algorithm employs a series of repetitive add-compare-select operations which

accept as input certain metrics computed on each symbol received from a demodulator.

For satellite, cable and terrestrial transmission of high data rate signals, such

computations need to be performed at very high rates.

In the case of a satellite transmission channel, it is customary to transmit some

particular punctured quaternary phase shift keyed (QPSK) code known to the receiver's convolutional decoder. In the case of a terrestrial or cable transmission channel, it is

customary to transmit some particular trellis code in conjunction with a given modulation

scheme, such as quadrature amplitude modulation (QAM), phase amplitude modulation

(PAM) or phase shift keyed (PSK) code known, tef the receiver's convolutional decoder.

Pragmatic trellis codes are a subset of the general class of trellis codes wherein only one

of n bits is encoded using a convolutional code and the remaining (n-1) bits are sent

unencoded. Pragmatic trellis decoding involves decoding an information stream

corresponding to an embedded rate 1/2 encoded stream followed by a demapping

operation to extract the remainder of information bits. In this process, it is important that

the demapped data be aligned with the decoded data. The present invention has been

contemplated in order to ensure this result.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide an apparatus and

method for aligning a trellis demapped data stream with a data stream output from a rate

1/2 Viterbi decoder.

It is another object to provide an apparatus and method for aligning a trellis

demapped data stream with a data stream output from a rate 1/2 Viterbi decoder that can

be implemented at either the transmitter or the receiver.

It is still another object to provide a means for efficiently and cost effectively

enabling data alignment in a multi-channel, multi-point distribution system. When implemented at the transmitter, these and other objects can be achieved in

accordance with the principles of the present invention with an encoder for receiving and

convolutionally encoding a first input signal to provide output of an encoded signal. A

delay unit receives and delays a second input signaj/to provide output of a delayed signal.

A symbol mapper receives and performs a symbol mapping operation in response to the

encoded signal and the delayed signal, wherein the delayed signal exhibits a

predetermined temporal alignment with respect to the encoded signal.

When implemented at the receiver, these and other objects can be achieved with a

decoder for providing output of a decoded signal. A reencoder reencodes the decoded

signal to provide output of a reencoded signal. A trellis demapper demaps the reencoded

signal to provide output of a trellis demapped signal. A delay unit receives and delays

output of the decoded signal so that the delayed decoded signal exhibits a predetermined

temporal alignment with respect to the trellis demapped signal.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of this invention, and many of the attendant

advantages thereof, will be readily apparent as the same becomes better understood by

reference to the following detailed description when considered in conjunction with the

accompanying drawings, wherein:

FIG. 1 illustrates a preferred embodiment of the present invention wherein data

alignment is performed at the transmitter; and FIG. 2 illustrates another preferred embodiment of the present invention wherein

data alignment is performed at the receiver.

DETAILED DESCRIPTION O THE INVENTION

In the following detailed description, many specific details regarding known

functions and operations, which will be readily discernible to those skilled in the art, have

been omitted so as not to obscure the present invention. A more detailed explanation of

these details is provided in U.S. Patent No. 5,497,401, which is hereby incorporated by

reference.

Turning now to the drawings and referring to FIG. 1 , a preferred embodiment of

the present invention wherein data alignment is performed at the transmitter is shown. In

FIG 1, a transmitter 100 includes a rate 1/2 encoder 101, a prealignment delay 102, a

symbol mapper 103 and a modulator 104. During operation, rate 1/2 encoder 101 receives

1-bit signal inputs, performs a known rate 1/2 convolutional encoding operation and

provides 2-bit signal outputs. Prealignment delay 102 receives (n-1) bit signal inputs

(where n equals a predetermined integer selected in accordance with system design

considerations; n=4 and n=5, for example, have been used in exemplary systems), and

delays output of the (n-1) bit signals for a predetermined time period. This delay period,

which serves to align the (n-1) bit signals at desired, predetermined temporal locations

with respect to the 2-bit signals output from rate 1/2 encoder 101, compensates for

latency in demapping at the receiver 110. Symbol mapper 103 receives the 2-bit signal outputs from rate 1/2 encoder 101 and the (n-1) bit signal outputs from prealignment

delay 102, performs a known symbol mapping operation by mapping the bits to a

particular amplitude and or phase level depending on the type of modulation that is

employed, and provides output of symbol mapped data to modulator 104. Modulator 104

receives the symbol mapped data, performs a known type of modulation (e.g., PSK,

PAM, QAM), and provides output of modulated data to receiver 110 as a series of

convolutionally encoded symbol packets.

At receiver 110, a demodulator 1 11 receives the convolutionally encoded symbol

packets provided from transmitter 100. Demodulator 111, which is known in the art,

demodulates the convolutionally encoded symbol packets, and applies demodulated

signal outputs to a rate 1/2 Viterbi decoder 112 and delay logic 113. Rate 1/2 Viterbi

decoder 112 (e.g., constraint length k=7) performs the Viterbi algorithm for trellis codes,

and employs add-compare-select means, path metric storage means and memory for the

survivor paths at each level in the trellis. Rate 1/2 Viterbi decoder 112 also takes care of

metric renormalizations to avoid a buildup and overflow of accumulated metrics. The 1-

bit signal outputs from the rate 1/2 Viterbi decoder 112 are applied to a convolutional

reencoder 114. For trellis codes, reencoder 114 serves to regenerate the best estimates of

the two transmitted of the rate 1/2 embedded code. The 2-bit signal outputs from

reencoder 114 are applied to a trellis demapper 115, which is responsible for making

symbol decisions. Specifically, trellis demapper 115 uses the 2-bit signal output from

reencoder 114 for subset selection together with delayed I and Q received symbol data forwarded thereto through delay logic 113 to make these symbol decisions. The (n-1) bit

signal outputs from trellis demapper 115, and the 1-bit signal outputs from the rate 1/2

Viterbi decoder 112 are provided for additional receiver processing. Delay logic 113

accounts for the delay introduced by the rate 1/2 Vfterbi decoder 1 12 and reencoder 114,

and serves to synchronize the data stream at the output of reencoder 114 with the received

symbol stream.

As shown in FIG. 1, transmitter 100 provides prealignment delay 102 to account

for the delay that occurs in the demapping operation at receiver 110. That is,

prealignment delay 102 compensates for the latency in receiver 110 between the 1-bit

signal outputs from rate 1/2 Viterbi decoder 112 and the remaining (n-1) bit signal

outputs from trellis demapper 115. In other words, prealignment delay 102 ensures that

the (n-1) bit signals output from trellis demapper 115 are aligned at desired,

predetermined temporal locations with respect to the 1-bit signals output from the rate 1/2

Viterbi decoder 112.

Referring now to FIG. 2, another preferred embodiment of the present invention

wherein data alignment is performed at the receiver is shown. In FIG. 2, a transmitter 200

includes a rate 1/2 encoder 201, a symbol mapper 202 and a modulator 203. In

construction and operation, the transmitter 200 of FIG. 2 is essentially the same as the

transmitter 100 of FIG. 1, except that the transmitter 100 of FIG. 1 includes prealignment delay 102 while transmitter 200 of FIG. 2 does not. Accordingly, this embodiment

provides data alignment at receiver 210, rather than at transmitter 200.

The receiver 210 includes a demodulator 21 1, a rate 1/2 Viterbi decoder 212,

delay logic 213, a reencoder 214, a delay adjustment 215 and a trellis demapper 216. In

construction and operation, the receiver 210 of FIG. 2 is essentially the same as the

receiver 110 of FIG. 1, except that the receiver 210 of FIG. 2 includes delay adjustment

215 while the receiver 110 of FIG. 1 does not. In FIG. 2, delay adjustment 215 ensures

that the 1-bit signals output from the rate 1/2 Viterbi decoder 212 are aligned at desired,

predetermined temporal locations with respect to the (n-1) bit signals output from trellis

demapper 216. In this manner, efficient, synchronized system operation is achieved.

In accordance with the principles of the present invention, signal outputs from a

Viterbi decoder are properly temporally aligned with signal outputs from a trellis

demapper in a digital multi-channel, multi-point distribution system.

While there have been illustrated and described what are considered to be

preferred embodiments of the present invention, it will be understood by those skilled in

the art that various changes and modifications may be made, and equivalents may be

substituted for elements thereof without departing from the ✓true scope of the present

invention. In addition, many modifications may be made without departing from the

central scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the

invention, but that the present invention includes all embodiments falling within the

scope of the appended claims.

Claims

What is claimed is:
1. A transmitter, comprising:
an encoder for receiving and convolutionally encoding a first input signal to
provide output of an encoded signal;
a delay unit for receiving and delaying a second input signal to provide output of a
delayed signal; and
a symbol mapper for receiving and performing a symbol mapping operation in
response to the encoded signal and the delayed signal, wherein the delayed signal exhibits
a predetermined temporal alignment with respect to the encoded signal.
2. The transmitter as claimed in claim 1, wherein the first input signal
comprises a 1-bit signal.
3. The tr.ansmitter as claimed in claim 2, wherein the second input signal
comprises an (n-1) bit signal, and n equals a predetermined integer.
4. A receiver, comprising:
a decoder for providing output of a decoded signal;
a reencoder for reencoding the decoded signal to provide output of a reencoded
signal; a trellis demapper for demapping the reencoded signal to provide output of a
trellis demapped signal; and
a delay unit for receiving and delaying output of the decoded signal so that the
delayed decoded signal exhibits a predetermined temporal alignment with respect to the
trellis demapped signal.
5. The receiver as claimed in claim 4, wherein the decoder comprises a rate
1/2 Viterbi decoder.
6. The receiver as claimed in claim 4, further comprising a demodulator for
receiving input data, demodulating the input data to generate demodulated data and
providing output of the demodulated data to the decoder.
7. The receiver as claimed in claim 4, wherein the decoded signal comprises
a 1 -bit signal.
8. The receiver as claimed in claim 7, wherein the trellis demapped signal
comprises an (n-1) bit signal, and n equals a predetermined integer.
9. A method, comprising:
generating a decoded signal;
reencoding the decoded signal to generate a reencoded signal; trellis demapping the reencoded signal to generate a trellis demapped signal; and
delaying the decoded signal so that the delayed decoded signal exhibits a
predetermined temporal alignment with respect to the trellis demapped signal.
10. The method as claimed in claim 9, wherein the decoded signal comprises a
Viterbi decoded signal.
PCT/IB1998/001852 1997-10-01 1998-09-22 Apparatus and method for aligning trellis demapped data WO1999017455A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US94238097A true 1997-10-01 1997-10-01
US08/942,380 1997-10-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AU10488/99A AU1048899A (en) 1997-10-01 1998-09-22 Apparatus and method for aligning trellis demapped data

Publications (1)

Publication Number Publication Date
WO1999017455A1 true WO1999017455A1 (en) 1999-04-08

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WO (1) WO1999017455A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1091579A2 (en) * 1999-09-07 2001-04-11 Thomson Licensing S.A. Trellis demapper for Trellis decoder

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Publication number Priority date Publication date Assignee Title
EP0524625A2 (en) * 1991-07-26 1993-01-27 General Instrument Corporation Of Delaware Method and apparatus for communicating compressed video using trellis coded QAM
WO1993006550A1 (en) * 1991-09-27 1993-04-01 Qualcomm Incorporated Viterbi decoder bit efficient chainback memory method and decoder incorporating same
EP0652643A2 (en) * 1993-11-04 1995-05-10 Kabushiki Kaisha Toshiba Apparatus and method for trellis decoder
US5428646A (en) * 1992-12-24 1995-06-27 Motorola, Inc. Device and method for frame synchronization in a multi-level trellis coding system
US5497401A (en) * 1994-11-18 1996-03-05 Thomson Consumer Electronics, Inc. Branch metric computer for a Viterbi decoder of a punctured and pragmatic trellis code convolutional decoder suitable for use in a multi-channel receiver of satellite, terrestrial and cable transmitted FEC compressed-digital television data
EP0713337A2 (en) * 1994-11-18 1996-05-22 Thomson Consumer Electronics, Inc. Apparatus for demodulating and decoding satellite, terrestrial and cable transmitted digital television data

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EP0524625A2 (en) * 1991-07-26 1993-01-27 General Instrument Corporation Of Delaware Method and apparatus for communicating compressed video using trellis coded QAM
WO1993006550A1 (en) * 1991-09-27 1993-04-01 Qualcomm Incorporated Viterbi decoder bit efficient chainback memory method and decoder incorporating same
US5428646A (en) * 1992-12-24 1995-06-27 Motorola, Inc. Device and method for frame synchronization in a multi-level trellis coding system
EP0652643A2 (en) * 1993-11-04 1995-05-10 Kabushiki Kaisha Toshiba Apparatus and method for trellis decoder
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Title
ROSS M D ET AL: "PRAGMATIC TRELLIS CODED MODULATION: A SIMULATION USING 24-SECTOR QUANTIZED 8-PSK", PROCEEDINGS OF THE ANNUAL INTERNATIONAL PHOENIX CONFERENCE ON COMPUTERS AND COMMUNICATIONS, SCOTTSDALE, APR. 1 - 3, 1992, no. CONF. 11, 1 April 1992 (1992-04-01), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 232 - 239, XP000310614 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1091579A2 (en) * 1999-09-07 2001-04-11 Thomson Licensing S.A. Trellis demapper for Trellis decoder
JP2001111636A (en) * 1999-09-07 2001-04-20 Thomson Licensing Sa Method for obtaining decoded symbol data and decoder
EP1091579A3 (en) * 1999-09-07 2003-05-14 Thomson Licensing S.A. Trellis demapper for Trellis decoder
JP4673964B2 (en) * 1999-09-07 2011-04-20 トムソン ライセンシングThomson Licensing Method and decoder apparatus for obtaining decoded symbol data

Also Published As

Publication number Publication date
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