WO1999015909A1

WO1999015909A1 - Method for building a testing infrastructure for a system on a semiconductor chip

Info

Publication number: WO1999015909A1
Application number: PCT/US1998/019857
Authority: WO
Inventors: Prabhat Varma; Sandeep Bhatia
Original assignee: Duet Technologies, Inc.
Priority date: 1997-09-22
Filing date: 1998-09-22
Publication date: 1999-04-01

Abstract

A technique is provided for building a testing infrastructure for use in testing the components of a system on silicon composed of user defined logic 'UDL' components (14, 16, 18), virtual components (such as complex processors defined by netlists and having structures which are proprietary to the source) and interconnects thereof in a system self-contained on a semiconductor chip (10) having internal circuit interconnect nets (traces provided by the system chip designer), wherein the system chip includes at least one virtual component having supplied therewith a combination of functional and structural descriptions which are together inadequate to fully depict an embodiment of the virtual component.

Description

METHOD FOR BUILDING A TESTING INFRASTRUCTURE FOR A SYSTEM ON A SEMICONDUCTOR CHIP

BACKGROUND OF THE INVENTION This invention relates to testing of a so-called system on silicon, in which is embedded at least one virtual component, also known as a system level macro, a megacell or a core, which virtual component is not fully characterized, i.e., its structure or its function is not completely known or disclosed by its originator.

The challenges involved in designing systems on silicon are leading to an increase in design re-use i.e. the re-use of existing logic chips as "Intellectual Property" (hereinafter "IP") embedded in system level integrated circuits (ICs) . IP blocks, also called cores, are defined as predesigned logic modules used as building blocks in circuits. Examples of IP are micro-processors, DSP functions, MPEG functions and JPEG functions configured as cores. In addition, memory cells such as RAM or ROM may be embedded in the system level IC. User defined logic (UDL) consists of all other logic entities added by the user to customize the circuit. Parts of the UDL that can be accessed only through IP input/output ports (I/O) constitute "shadow logic."

In view of the diverse nature of the building blocks 11-14, 16 that will be used in system level ICs 10 (see Fig. 1) , it is very unlikely that one methodology will be used to test them all. For example, "built-in self-test" (BIST) techniques are becoming accepted as the preferred method for testing large embedded RAMs, while structured "design for testability" (DFT) methods such as the scan design technique, in which system flip-flops are made serially controllable/observable, are being adopted for large UDL blocks . While structured DFT techniques are likely to be increasingly used in IP blocks, the majority of IP blocks today and for the foreseeable future will be based on old chip designs - so called legacy IP. Most of this legacy IP relies on the use of functional test rather than structured DFT methodologies. Thus, a major issue in IP testing is how to allocate resources in the chip so that test programs already available for or used with the IP cores can also be used to test them.

An effective system on silicon test strategy must include a test re-use methodology for testing legacy IP, a method for accessing and activating RAM BIST, and methods for accessing serial-scan based structured DFT. It must also provide methods for testing user-defined logic.

Current IP test methodologies provide direct access to I/O terminals of IP during test by multiplexing test I/O lines with normal chip I/O terminals at the chip pads or by the use of the boundary scan methodology. Typical testing of UDL circuits is carried out using well-known techniques, such as a scan-based deterministic test. While these techniques serve the purpose of IP and UDL testing, there are several drawbacks . The use of multiplexers provides access to the IP and so allows "at-speed" test application. However, there is no provision for access to the UDL logic in the "shadow" of the IP element. In addition, the wiring overhead associated with the multiplexers may be high.

The use of boundary scan reduces wiring overhead and provides access to both the IP and UDL elements. However, test application is slow and time-consuming, thus adding to the potential overall cost of manufacturing and delivering a reliable product.

An inadequately-depicted virtual component, by its nature, cannot be merged into the user-defined logic. Hence, the chip designer cannot adequately test the system, which leads to the problem herein sought to be solved.

SUMMARY OF THE INVENTION According to the invention, a mechanism is provided whereby test methodologies previously used on standalone components can be used to test those components when they are embedded in a system-on-silicon. The methodology and circuitry extends and retains the benefits of previously-developed test methodologies used with the standalone components so that totally-new test vectors and test methodologies need not be developed for the components incorporated into a system-on- silicon. According to one aspect of the invention, a technique is provided for building the testing infrastructure for use in testing the components of a system on silicon composed of user-defined logic (UDL) components, virtual components (such as complex microprocessors defined by netlists and having structures which are proprietary to the source) , and interconnects thereof (traces in silicon) in a system self-contained on a semiconductor chip having internal circuit interconnect nets (traces provided by the system chip designer) , wherein the system chip includes at least one virtual component having supplied therewith a combination of functional and structural descriptions which are together inadequate to fully depict an embodiment of the virtual component . The technique used to define and provide the testing infrastructure has the following steps: 1) Defining mappings (manually or automatically) between ports of inadequately-depicted virtual components and the system's external ports.

2) For each path defined by these mappings for which an explicit mapping path does not exist during test operations, providing a switchable signal path via at least one test data bus and at least one test control bus (optionally one bus) to implement a signal connection of said defined path to said system external ports .

3) Providing at least one bi-directional access path or one input access path and one output access path per interconnect net, via the test data bus, to the circuit interconnect nets, wherein the access path provides a switchable alternative signal path from said system external ports to the virtual components and to the user-defined components within the on-chip system. The buses and access signal paths to the system nets connecting between virtual and virtual or real components may not be direct, i.e., they could be latched and thus time delayed. In practice, complex virtual components require that latches be used in testing environments, since the number of bus traces carrying signals which are added by this infrastructure design will typically be less than the number of ports defined for the virtual components .

There are numerous benefits for the system on silicon test strategy according to the invention:

The contemplated system-on-silicon test strategy is applicable to full custom standard cell designs and gate array design styles.

It offers a unified framework for systems on silicon test. It works with any block/core test methodology. It allows test re-use for IP cores.

It facilitates system debug, since it allows the state at system interface nets captured at selected instants to be read offline.

The technique also allows block-block interconnect test for shorts/opens/stuck-at and delay faults.

These and other advantages of the invention will be better understood by reference to the following detailed description in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a system on silicon integrated circuit (prior art) .

Fig. 2 is a block diagram illustrating a system on silicon integrated circuit with an IP test bus and distributed test collar.

Fig. 3A is a conceptual block diagram of a test re- use methodology according to the invention.

Fig. 3B is a conceptual block diagram of a test collar structure for IP bi-directional inputs and outputs.

Fig. 4A is a schematic diagram of an IP input port test collar structure. Fig. 4B is a schematic diagram of an IP output port test collar structure. Fig. 5 is a schematic diagram of a test collar substructure for IP bi-directional ports according to the invention.

Fig. 6 is a schematic diagram showing bi-directional wiring and structures connecting IP blocks and UDL blocks according to the invention.

Fig. 7 is a schematic diagram showing bi-directional structures connecting two IP blocks.

Fig. 8 is a schematic diagram showing connections between two IP blocks by a bi-directional structure.

Fig. 9 is a schematic diagram showing an IP I/O interface structure.

Fig. 10 is a block diagram showing two IP blocks connected by two IP I/O interface structures. Fig. 11 is a block diagram showing circuitry and structures for interconnecting two IP blocks.

Fig. 12 is a block diagram illustrating a multiple input shift register (MISR) -based interface structure.

Fig. 13 is a schematic diagram illustrating an interface structure with a state retention latch.

Fig. 14 is a schematic diagram illustrating a bidirectional access substructure with a state retention latch.

Fig. 15 is a schematic diagram showing bidirectional test pads. Fig. 16 is a schematic diagram showing tri-state output test pads .

Fig. 17 is a schematic diagram showing direct output test pads.

Fig. 18 is a block diagram showing an IP test collar interconnecting two IP blocks.

DESCRIPTION OF SPECIFIC EMBODIMENTS In the inventive technique, the methodology allows access to IP in a manner permitting test application time and speed to be traded off for area overhead. It allows a range of access techniques that span from full parallel access to serial access to be used. If bi-directional pins are available for test use, then the methodology allows these pins to provide bi-directional access to IP bi-directional ports and allows the UDL and IP test data wires that access a given interface signal to be shared.

In general, the methodology relies on the concept of one or more test data buses, which will usually be bi-directional but may also be input/output only, to apply test data from system pins. Where possible, existing system buses are used. Logic to isolate the system side of the bus from the test side is required. In addition, isolation logic at IP output ports is generally required - although if all IP blocks have an output disable mode that puts outputs into the high impedance state, then this can be removed. Isolation at IP block input ports may also be required, but this can be achieved through simple AND/OR logic gate structures to obtain a safe state.

In addition to a test data bus, a test control bus is also used. This may come from user data registers (as in the IEEE 1149.1 standard) and/or directly from system pins. In the latter case, the system logic driven by the test control pins must be isolated and accessed in test mode via the test data bus .

IP Test Collar

Consider a design of a system-on-silicon 10, as in Fig. 2 having a RAM component 11, IP core blocks or virtual components 12 and 13, UDL components 14, 16 and on-chip test control components 17. The system elements are interconnected by a test bus 19 wherein a test collar structure 20, comprising herein elements 21, provide access between the bus and the various elements under control of the test control block 17, as well as pad access ports 23.

Fig. 3A consists principally of an IP core block 12 and UDL blocks 14, 16 and 18. Assuming that the test methodology (for both the IP and UDL blocks) is based on functional test, a test-reuse methodology that allows the functional test of the IP to be re-used is desirable. IP blocks can be accessed for testing using a test collar 20 that consists of input/output/bi-directional structures 22, 24, 26. These basic structures do not provide access to the UDL block 14, 16 or 18. The bi-directional structure 26 shown in Fig. 3B comprises a bi-directional sub-structure 28 and an isolating tri-state buffer 30. The bi-directional sub-structure 28 is shown in Fig. 5, using logic symbols for the buffers and inverters coupled into the signal lines TDIO, CTE, BI and UBI.

Referring to Fig. 3A and Fig. 4A, the IP input structure 22 has an UDO input that is connected from the output of a UDL block 14 and a DI output that is connected to the data inputs of the IP block 12. Test data is input to the IP structure 22 via the TDI port and made available at the DI output when the cell test enable port, CTE is high.

Referring to Fig. 3A and Fig. 4B, the IP output structure 24 has a DO input port that is connected from the data output port of the IP block 12 and a UDI output port that is connected to an input port of a UDL block 16. Test data from the DO input is made available on the TDO port when the CTE port is high.

Referring again to Fig. 3A and Fig. 3B, the bi- directional structure 26 comprises a bi-directional sub-structure 28 and some input and output structures (not shown) . The bi-directional sub-structure 28 has a BI port 32 that connects to an IP bi-directional port 34 and a UBI bidirectional port 36 that connects to the UDL 18. Test data is input/output via a TDIO port 40 when the CTE port 29 is high.

The test collar cell for bi-directional ports of an IP block connected to a UDL block (to be accessed as an IP block) can be partitioned into a simple bi-directional sub-structure 28, with a bi-directional CMOS transmission gate 35, as in Fig. 7, or gate 35, as in Fig. 5. Referring also to Fig. 6, this structure provides bi-directional access to the IP core block 12, an input structure 39 that provides access to the UDL input sides 41 of the bi-directional net and an output structure 43 that provides observability of the UDL output side 45 of the bi-directional net. In addition, an isolating three-state buffer 37 is provided from the UDL output side so that the bi-directional net can be isolated from the UDL outputs during IP test . Instead of adding the isolating tri-state buffer, as shown, the UDL tri-state driver control might be modified such that these outputs can be put into the high impedance mode during IP test .

Referring to Fig. 7 and Fig. 8, a bi-directional test access structure 29 can be used at bi-directional wires 47, 48 that connect two IP core blocks 12, 112. In the input/output interface structure, the TDI and TDO ports can be connected to the same bi-directional test data wire 49. The test enable signal TE (which is low during system mode) is used to isolate the two IP blocks 12, 112 during test. If there are multiple IP blocks 12 on a bi-directional bus, then an additional isolating transmission gate will be required with each additional IP block 12 on the bus unless the IP function has been implemented with an output disable pin that can put all outputs and bi-directional outputs into tri-state mode. If the IP blocks 12 have disable output mode capabilities, then the test collar structure can be simplified to remove the isolating transmission gates in order to compact the IP access structures into a single structure. If the IP block 12 is connected to another like IP block 12, or to a UDL block 18 that is to be accessed as an IP block, the input and output structures can be combined into an IP interface structure 50 as shown in Fig. 9. Since, in general during an IP test, the controls CTEi and CTEj will not be high at the same time, TDI and TDO ports can be connected to the same bi-directional test data line. Two such IP blocks 12 and 112 connected by the IP- IP bi-directional interface structure 29 are shown in Fig. 8. Dual IP interface- I/O structures 50 are shown in Fig. 10 coupling two IP structures 12.

When there is not a sufficient number of pins available to allow direct parallel test access to an IP block 12, multiplexing techniques can be used. Referring to Fig. 11, if only IP block 12 outputs need to be multiplexed, then output multiplexing allows the IP test vectors to be re-used. However, it is required that the test vectors be repeated once for each group of IP outputs so selected. This allows "at-speed" test input application at the expense of an increase in test time. If, on the other hand, inputs to several IP blocks 12 need to be multiplexed, then state retention latches 52 are required to hold the state of the test inputs after they have been set up. This decreases test application speed as well as increase test application time. In example circuit 54 containing two IP blocks 12 with both input and output multiplexing capability, input multiplexing is not actually required, since primary port INI could be used to provide test input data for IP2, while port IN2 could be used to provide test input data for IP1.

Still another approach that can be used to reduce the amount of required multiplexing relies on the concept of data compression. Referring to Fig. 12, an MISR 58 can be added to either all or a sub-set of IP block interface outputs and bi-directional outputs of the circuit 56. This can be used to compact the test data output. The MISR 54 can also be used to serially shift in data for the IP block 12 or a UDL block (not shown) downstream of the IP outputs, as shown.

An IP interface structure 58 that combines the input and output structures with a state retention latch 60 is shown in Fig. 13. This structure has a bi-directional test data line tdio 62. With CTEi high and CTEj low, the output select (osel) line 64 can be set high to allow test data from the DI line to be made available on the tdio line 62. This data can be latched into the state retention latch 60 using the isel select line 66. The data can then be observed by setting CTEj high while keeping CTEi and osel high. This allows a snapshot of test data to be taken "at-speed" but assumes that the CTEi and CTEj can be independently controlled. Moreover, by constraints on the placement of the three-state buffers 37 so that they are adjacent to component ports, the structure can be used to test interconnect integrity. This is the basic collar structure for system debug as it provides a path from the system interconnect nets to the state retention latch 60 which is used to capture the state of the system net, and provides a path from the state retention latch 60 to the test bus so that the state can be read. (In this case, the latch input select signal (isel) 66 must be a clock available from a primary port . )

A bi-directional access structure 68 with a state retention latch 60 is shown in Fig. 14. This structure 68 allows input multiplexing. Test data output is made available on the tdio port 62 from sdio port 68 when the test data output signal (osel 64) , and the CTEi signal 66 lines are high. The test data input on the tdio line (port) 62 is latched into the state retention latch 60 using the isel 60 signal line and made available on the sdio port 68 when the osel 64 signal line is low and the CTEi 70 signal line is high. The IP bi-directional interface structure shown in Fig. 7 can be implemented with transmission gates Tl and T2 therein replaced by the bi-directional access sub-structure 68 shown in Fig. 14. Only one state retention latch 60 connected to the tdi ports of the sub-structures 68 is required therein. If the bi-directional control signal is available from the IP block then this can be used to facilitate replacement of transmission gate T3 by the bi-directional access sub-structure also. In this case, the ~TE signal is connected up to the CTEi port of the sub-structure and the IP direction control signal replaces the osel signal.

Referring now to the pad structures, of external terminal connections, associated with the invention and Fig. 15, bi-directional I/O pads 72 are useful. They can be used as bi-directional test pads by the addition of a bidirectional test isolation structure 74 that isolates the system bi-directional line or trace 76 from the test bi-directional line or trace 78. The logic structure can be a transmission gate or a basic bi-directional pad logic structure comprising tri-state buffers 80, 82 controlled by test output enable signal (TOEN) rather than the regular system output enable (SOEN) . If the bi-directional pad is broken into an input and output side, or if it goes to UDL, only the isolating three-state output buffer is required.

The TOEN signal is given by: TOEN = ~TE*OEN + TE*osel0 where oselO is the test output select signal that essentially activates normal system output access to the pad during test operation.

The SOEN signal is given by: SOEN = ~TE*OEN + TE*tdir where tdir is the test data direction signal for the test data bus connected to that pin.

Input pads can be used to provide test input directly - assuming that isolation of system inputs during test application is not required. If isolation is required then it can be achieved through simple AND/OR gates. Primary inputs (and bi-directional inputs) that control storage elements or outputs asynchronously require state retention latches to retain the system input state. Output pads require an isolating tri-state buffer to be inserted to isolate the pad from the system.

An example of a three-state output pad 84 is shown in Fig. 16, while a straight-forward output test pad 86 is shown in Fig. 17. In Fig. 16, The SDO port allows system data to be output at the DO pad when TOEN is high, while test data on the test data output port TDO is output when TOEN is low. TDO is at the high impedance state when TOEN is high.

Fig. 18 illustrates the use of a bi-directional test data bus 88 with direct access of all IP ports from the chip pins 90, using a test collar 92 to connect IP blocks 12. The test collar cells may contain latches for time multiplexing of the test data bus . Element IPj for example may have i inputs and o outputs, where n <= i+o. If n >= i+g, where g >= 1 (and n <= i+o) then this configuration allows test vectors to be applied at speed. As g increases towards o then the test application time is also reduced. It is minimized when g = o, as only 1 test session for that IP element is required; otherwise o/g test sessions are required (number of output groups = o/g) . The use of output data compression also allows at- speed testing if n >= i (i.e. g = 0). While this structure and configuration allow test vectors to be applied at-speed, minimizing test application time, the result nevertheless can

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ports must be accessed using "system access" even in test mode, unless these primary ports are used to provide test control, in which case the system side of these ports is accessed by the test bus. The size and number of test buses implemented will depend on the trade-offs made between area and test time. The "stealing" of primary pins from the UDL to implement either all or part of an input/output/bi-directional test bus can help increase test application frequency but may leave less area than the technique of using an existing system bus that is connected to IP blocks.

For an IEEE 1149.1 (JTAG) compliant design, test control can be accomplished via the JTAG test pins and user data registers. Separate user data registers can be used to control the CTE, isel, osel and tdir signals. However, the use of the JTAG controller and data registers will have a negative impact on test time and test application frequency. Another approach is to use system pins to apply some (or all) of the test control signals. In such a case, isolating-type tri-state buffers (to isolate pin changes from the system logic) will be required, and the test data bus will be used to apply test data to the system side of these pins. For designs without JTAG, the latter approach will be required. However, at least one additional test pin for test enable (TE) will be required. System pins can be used to control serial registers that set up such control. This may be acceptable for control signals that do not change during a test session i.e. the CTE signals.

If a test program is split up into multiple test sessions, all with the same input vectors but with a different group of outputs selected per test session, the output select signals can be controlled from a shift register. However, controlling the input multiplexing signals (isel) and the test direction control signals (tdir) directly from system pins may be preferred to minimize test time and maximize test application frequency.

Techniques and structures have been disclosed to provide test access to a class of circuitry herein called "intellectual property" (IP) and user defined logic (UDL) embedded in system level integrated circuits, i.e., integrated circuits in which whole systems are combined into a single substrate. The invention allows test re-use for IP blocks and provides access to the logic in the shadow (relative to accessible signal inputs and outputs) of the IP or UDL block. The test access structures are inserted at the interfaces of these blocks to provide access to their I/O interface ports. In general, the methodology relies on the concept of one or more test data buses, which will usually be bi-directional but may also be input/output only, to apply test data from system pins. Where possible, existing system buses are used. Logic to isolate the system side of the bus from the test side is required. In addition, isolation logic at IP ports is generally required - although if all IP blocks have an output disable mode that puts outputs into the high impedance state then this is not necessary. In addition to a test data bus, a test control bus is also used. This may come from user data registers (as in the IEEE 1149.1 standard) and/or directly from system pins . In the latter case the system logic driven by the test control pins must be isolated and accessed in test mode via the test data bus .

The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art. It is therefore not intended that the invention be limited, except as indicated by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method for building testing infrastructure for use to test user defined logic components, virtual components and interconnects thereof in a system self- contained on a semiconductor chip having internal circuit interconnect nets, wherein said system includes at least one virtual component having supplied therewith a combination of functional and structural descriptions which are together inadequate to fully depict an embodiment of said virtual component, said circuit interconnect nets providing coupling between said inadequately defined virtual component and at least one other virtual component or real component, said method comprising the steps of : defining mappings between selected ports of said inadequately-depicted virtual component and system external ports; for each path defined by said mappings for which an explicit mapping path does not exist during test operations, providing a switchable signal path via at least one test data bus and at least one test control bus to implement a signal connection of said defined path to said system external ports; providing means for activating component isolation during a system chip test mode so that components not under test during said system chip test mode may receive, as input, pre-defined logic states and are prevented, via their outputs, from driving said circuit interconnect nets; and providing at least one access path per net, via said test data bus, to said circuit interconnect nets, said access path providing a switchable alternative signal path from said system external ports to said virtual components and to said real components within said on-chip system.

2. The method according to claim 1 wherein said at least one access path includes an output access path and an input access path.

3. The method according to claim 1 wherein said at least one access path is a bi-directional path.

4. The method according to claim 1 where selected ones of said access paths are coupled to a virtual component and wherein test latches are provided for temporarily storing digital values of signals.

5. The method according to claim 4 further including multiplexing component test signals for selected multiple test blocks.

6. The method according to claim 1 further including multiplexing component test signals for selected multiple test blocks.

7. The method according to claim 1 further including compressing data from test signals through an MISR type shift register.

8. The method according to claim 1 wherein said at least one access path is a test bi-directional path and wherein bi-directional isolation is provided between a system bi-directional path and said test bi-directional path.

9. The method according to claim 8 wherein said bi-directional isolation includes a tri-state latch.

10. The method according to claim 8 wherein said bi-directional isolation includes a transmission gate.