WO1999004407A2

WO1999004407A2 - Current limiter for field emission structure

Info

Publication number: WO1999004407A2
Application number: PCT/US1998/013695
Authority: WO
Inventors: Yachin Liu; Steven Zimmerman
Original assignee: Fed Corporation
Priority date: 1997-07-21
Filing date: 1998-07-01
Publication date: 1999-01-28
Also published as: WO1999004407A3

Abstract

A current limiter for flat panel field emission display devices is disclosed. The current limiter includes a vertical resistor (22) and a lateral resistor (21) which in combination provide uniform emission and blow-out protection. The current limiter consists of two layers (21, 22) of different resistive materials. The resistivity for the top layer is determined by the emission current density requirement and the geometric configuration of the device, including emitter base and pitch dimensions, emitter density per array and the resistive film thickness. This top layer resistor conducts vertically and helps prevent emitters with slightly lower emission thresholds from delaying the turn-on of other emitters within a pixel. Intra-pixel individual emitter resistance is substantially controlled by the vertical resistive layer (22), while the blow-out resistance and inter-pixel uniformity is controlled primarily by the lateral resistive layer (21).

Description

CURRENT LIMITER FOR HIGH RESOLUTION FIELD EMISSION STRUCTURE

Field of the Invention

The present invention relates to flat panel field emission structures such as, for example, displays and, more particularly, relates to a current limiter in the emitter plate of the structure. The invention also relates to methods of making a flat panel field emission structure having a current limiter in the emitter plate.

Background of the Invention

Flat panel field emission displays are a type of cathode ray tube (CRT) display. CRTs produce a visual image on a screen, such as those for desk-top computers. In the CRT device, an electron gun produces a scanning electron beam that increases the energy level of phosphors or other electroluminescent elements on the screen. Photons of lights are produced when the phoshors return to their normal energy level. These photons are transmitted through the glass screen of the display to the viewer.

In spite of their benefits and wide-spread commercial acceptance, conventional CRTs, however, have a number of disadvantages. They are, generally: heavy, large, and consume substantial amounts of power. For appliances that require lightweight, portable, compact and power-efficient screens, flat panel displays are preferable over the conventional electron gun CRTs. CRT displays with electron beam scanning cannot readily be reduced in size and thickness for physical reasons. For example, image distortion occurs if the beam falls at a low angle on the screen. In color displays, the resolution is reduced. Flat panel displays find application in aviation, automobiles, work stations, lap-top computers head-wearable displays, head-up displays, outdoor signage, or practically any device containing a screen which conveys information through light emission. The advent of portable computers has driven the demand for flat panel displays. Rather than forming images with a scanned beam, flat panel displays employ a line and column addressed matrix of points (pixels). Examples of flat panel displays include plasma displays, liquid crystal displays, fluorescent displays, and field emission displays (FEDs), among other possible configurations. Plasma displays are inefficient and limited in brightness. Their manufacturing techniques limit their practical use to large area non-portable applications. Many laptop and notebook computers currently use liquid crystal displays (LCDs). Compared to a conventional electronic beam CRT, these LCD displays provide poor contrast, limited range of viewing angles and consume more power than is optimal for battery operation.

Research on flat panel display technologies has focused increasingly on field emission displays (FEDs) as an alternative to LCDs. FEDs offer relatively low manufacturing cost and complexity, low power consumption, high brightness, improved range of viewing angles, and eliminate the need for back lights. A flat panel display utilizing field emission technology may comprise a flat vacuum cell with a matrix-addressable array of thin-film, microscopic cold field emitter cathode tips (also known as "micropoints", "microtips" or "emitter cones"). The tips are typically formed on the back plate of the cell. A phosphor-coated anode forms the front plate of the cell. Between the cathode and anode may be provided a third element, known as a "grid," "gate" or "web." Typically, the field emitter tip is in contact with an emitting electrode. Upon application of an appropriate voltage between the emitting electrode and the gate, quantum mechanical tunneling or other known phenomena cause the tip to emit electrons in the directions of the display surface, through holes or apertures in the grid or gate layer if one is present. The emitted electrons strike phosphors on the surface of the anode, causing the phosphors to luminesce. An image is produced by the luminescing phosphors on the inside of the display screen.

This process is a very efficient way of generating a lighted image. Flat panel FEDs are relatively thin compared to conventional, electron gun CRT displays, because the emitter tips, which perform the function of the electron gun in a CRT, are extremely small. Further, an FED does not require an aiming device. Each pixel has its own array of "electron guns," (i.e., array of emitters), positioned directly behind it. The emitter need only be capable of emitting electrons in a direction generally normal to the FED substrate.

Field emission cathode structures are disclosed by Spindt. et al. in U.S. Patent Nos. 3,665,241, and 3,755,704, and 3,789,472, and 3,812,559. Flat panel field emission displays and methods for making the same are disclosed by Biberian in U.S. Patent Nos. 4,763,187 and 4,884,010. A basic flat panel FED of the known art is shown in Fig. 1. The FED includes a substrate 10 having a cathode conductor 20 formed thereon. An insulator 30 and gate 40 are formed on the conductor 20. An electron emitting tip 60 is formed within a cavity in the insulator 3 and the gate 40. Spaced from the gate 40 is a glass cover plate 80. A conductor layer 70 is formed on a lower surface of the cover plate 80. A phosphor layer 65 is formed on the conductor layer 70. Electrons 9 emitted from the emitter tip 60 contact phosphor layer 65 producing light.

Notwithstanding the advantages that flat panel FEDs bring to the art of flat panel display devices, continuing development efforts in the technology have revealed two key problems. Both are related to device operation and are caused by excessive current drawn by the electron emitters: (1) reliability of tip emission, and (2) tip emission homogeneity over a large area. Essentially, some of the tips tend to fail prematurely. In addition, current tends to concentrate in certain areas of the device, resulting in flashover, which may damage or destroy the display. A resistive layer underneath the emitter tips, functioning as a ballast or current limiter, typically has been employed to overcome these problems. Four approaches for providing a ballast or current limiter to prevent excess current from being drawn by the electron emitters are known by the present inventors prior to the present invention.

First, a vertical resistive layer is provided, as disclosed by Borel et al., U.S. Patent Nos. 4,857,161 and 4,940,916; Meyer, U.S. Patent No. 5,194,780; Jones, U.S. Patent No. 5,529,524; Jones et al., U.S. Patent No. 5,534,743; and Westphal et al., U.S. Patent No. 5,656,886. This vertical resistor is inadequate, however, for practical applications, because it is prone to pinholes and other defects. Such defects cause a breakdown of the resistive layer between the cathode conductor and the emitter tips, disabling the overall current-limiting effect of the structure. A vertical resistor provides effective resistance to an individual emitter, but shorts can develop due to pinholes or defects in the resistive film. A direct short between the emitter and the cathode electrode may cause that emitter to emit prematurely at a much lower voltage. This effect can proceed rapidly out of control, resulting in substantial heat generation and eventually, a catastrophic failure of the emitter. Second, lateral resistive layer on top of cathode conductors that are formed into a lattice or mesh pattern is disclosed by Meyer, U.S. Patent No. 5,194,780; and Leroux et al., U.S. Patent No. 5,534,744. This lateral resistor overlying the lattice or mesh-like cathode conductor provides an improvement in breakdown resistance without requiring an increase in the thickness of the resistive layer. A limitation of this approach, however, is that the ballast resistance between a particular emitter and the cathode mesh structure varies with the position of the emitter within the array. Moreover, the mesh occupies a large fraction of the pixel area, thereby reducing the numbers of emitters per pixel. This in turn limits the maximum resolution and brightness of the display. Third, lateral resistive layer is provided either underneath or on top of cathode conductors formed into a pad and mesh structure, as disclosed by Taylor et al., U.S. Patent Nos. 5,507,676; 5,522,751 ; and 5,541 ,466. The cathode is formed in a pad and mesh configuration and is located either above or below the lateral resistive layer. This is an improvement over the approach of Meyer, above, because the pad structure provides an equal potential to all emitters by virtue of their electrical connection to the conductive plate. The variation of the ballast resistance between the individual emitters within the array is thus eliminated. Unfortunately, this configuration permits electrical current stealing by a preferred emitter from other emitters within the array. Current stealing can occur regardless of the placement of the resistive layer: if the resistive layer is above the pad and mesh cathode structure, then no resistance is provided to prevent current stealing; if the resistive layer is below the pad and mesh cathode structure, then there is too little resistance provided to effectively prevent current stealing. In this configuration of the cathode and current limiter, all emitters within a pixel share a single pad of the cathode. The lateral resistor must have sufficiently low resistance so as to allow the sum of all the emission current to flow. With this low resistance, then, current stealing by a preferred emitter makes the current limiting effort inefficient. This is particularly a problem in high-resolution FEDs with high emitter packing density.

In addition, both approaches using lateral resistors in conjunction with a mesh structure cathode electrode suffer from a common limitation: the narrower stripe of the cathode mesh competes for space with the array of emitters.

Fourth, resistive base or post is provided below the emitter, as disclosed by Huang, U.S. Patent No. 5,451,830; MacDonald, U.S. Patent No. 5,363,021; and Jones et al, U.S. Patent No. 5,534,743.

Huang discloses a current limiter for a high resolution flat panel FED. The emitter in Huang has a resistive base whereby any short between the gate and cathode melts a resistive base first, resulting in a higher resistive path between the gate and cathode. This would sustain the gate- cathode voltage and help prevent dead shorts. The emitter tip and base disclosed by Huang, however, require that the emitter tip be extremely small, on the order of 10 to 100 Angstroms. Because the total deposition of the emitter structure (base and tip combined) is about 10,000 Angstroms, this design allows for less than a 1% variation in the emitter tip structure. This level of fabrication precision is not practical. An additional problem with this current limiter structure is leakage of current due to surface conduction at the perimeter of the resistive base, which may disable the current limiter. Other designs employ resistors below the individual emitters.

Each of these four approaches fails to solve adequately the emitter tip reliability and homogeneity problems. There remains a need for a current limiter which provides adequate resistance to ensure emitter tip reliability and tip homogeneity without adding to the complexity of the FED. The present invention meets these needs and provides other benefits as well.

Objects of the Invention It is therefore an object of the present invention to provide a current limiter for a flat panel field emission display that achieves uniform emission of emitters.

It is another object of the present invention to provide a current limiter for a flat panel field emission display that provides a blow-out guard.

It is another object of the present invention to provide a current limiter having a two layer structure that combines the advantages of a vertical resistor and a lateral resistor.

It is another object of the present invention to provide independent resistance control. It is another object of the invention to provide for slow burn of any emitter tip that does short because of a pinhole or other defect in the resistive layer, to the point where that emitter becomes non-emissive. It is another object of the present invention to reduce current stealing by providing individual emitter tips with a resistance by the second resistive layer.

It is another object of the present invention to lengthen the life of the phosphors in the flat panel field emission display on the screen by improving emitter tip functioning.

It is another object of the present invention to improve emission reliability and emitter homogeneity without using any special processing techniques. It is another object of the present invention to maximize the available area for the emitter array.

It is another object of the present invention to provide improved electron conduction. It is another object of the present invention to permit a wider selection of materials to be used for the resistive layers of the current limiter, by virtue of the two-layer resistor structure.

Summary of the Invention The present invention is directed to a field emission display device. The display device may include an insulating substrate, a cathode conductive layer formed on the insulating substrate, a first resistive layer formed on the cathode conductive layer, and a second resistive layer formed on the first resistive layer. The cathode conductive layer may be formed into a ladder pattern having a first side rail, a second side rail, and a linear array of conductive pads spaced between the rails. A dielectric insulating layer may be formed on the second resistive layer. A conductive gate layer may be formed on the dielectric insulating layer.

An array of micro-cavities may be etchably provided through the dielectric insulating layer and the conductive gate layer. An emitter may be formed in each of the micro-cavities.

The present invention is also directed to an electron source. The electron source may include an insulating substrate, a cathode conductive layer formed on the insulating substrate, a first resistive layer formed on the cathode conductive layer, a second resistive layer formed on the first resistive layer, a dielectric insulating layer, formed on the second resistive layer, a conductive gate layer formed on the dielectric insulating layer an array of micro-cavities etchably provided through the dielectric insulating layer and the conductive layer, and an array of emitters formed in the micro- cavities.

The gate layer may include a plurality of gate lines orthogonal to the alignment of the array of the side rails. The second resistive layer includes an upper surface and a lower surface. The emitter base is in contact with the upper surface of the second resistive layer. The first resistive layer may comprise a low-resistivity material. In the present invention, the pixel resistance ratio of the second resistive layer to the first resistive layer is from 10:1 to 1000:1. The first resistive layer preferably consists of low-resistivity material. The second resistive layer preferably consists of high-resistivity material. The second resistive layer may have a thickness between 0.1 and 10 microns. The first resistive layer may have a thickness between 10 nm and 10 microns. According to the present invention, a second dielectric insulating layer may be formed on the insulating substrate. Stripes of a metal conductive layer may be formed on the second dielectric insulating layer. An insulating layer may be formed on the stripes of the metal conductive layer.

The cathode conductive layer may include tapered edges. The tapered edges of the cathode conductive layer ladder connect to the stripes of the metal conductive layer. The first resistive layer may further comprise tapered edges. The second resistive layer may further comprise tapered edges. The tapered edges of the first resistive layer and the tapered edges of the second resistive layer connect with the tapered edges of the cathode conductive layer at the stripes of the metal conductive layer. The present invention is also directed to method fabricating the current limiter. The method for fabricating a current limiter for a field emission structure includes the steps of forming an insulating substrate, forming a cathode conductive layer or structure on the insulating substrate, forming a first resistive layer on the cathode conductive layer, forming a second resistive layer on the first resistive layer, forming a dielectric insulating layer on the second resistive layer, forming a conductive gate layer on the dielectric insulating layer, etching an array of micro-cavities through the dielectric insulating layer and the conductive layer, and forming an array of emitters in the microcavities.

The cathode conductive layer or structure is formed into a ladder pattern comprising a first side rail, a second side rail, and a linear array of conductive pads spaced between the rails. The ladder pattern of the cathode conductive layer or structure is formed by a photo lithographic liftoff process.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated herein by reference, and which constitute a part of the specification, illustrate certain embodiments of the invention, and together with the detailed description serve to explain the principles of the present invention.

Brief Description of the Drawings

The invention will be described in conjunction with the following drawings in which like reference numerals designate like elements and wherein:

Fig. L is a side view of a flat panel field emission display according to the prior art;

Fig. 2. is a perspective new of a cathode conductive layer according to the present invention; Fig. 3. is a side view of a field emission display according to the present invention employing the cathode conductive layer of Fig. 2;

Fig. 4. is a perspective view of a current limiter structure according to the present invention;

Fig. 5. is a side view of a field emission display according to the present invention employing the current limiter of Fig. 4; Fig. 6. is a partial equivalent circuit diagram of the disclosed current limiter embodiment shown in Fig. 5; and

Fig. 7. is an equivalent circuit diagram reduced from Fig. 6 pursuant to the analysis presented below.

Detailed Description of the invention Fig. 2 illustrates a cathode conductor layer 10 according to an embodiment of the present invention. The cathode conductor layer 10 is formed on a substrate 1, as shown in Fig. 3. The substrate 1 may be coated with a dielectric layer 2. The dielectric layer 2 may be formed from various kinds of chemical vapor depositions of oxides, such as atomspherical pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) of SiO₂ or Si₃N₄. The dielectric layer 2 is helpful in preventing conductive impurity migration from the substrate. Additionally, the dielectric layer 2 provides good adhesion for subsequent layers that form the field emission device according to the present invention.

A conductive layer 10 is deposited on the dielectric layer 2. The conductive layer 10 may be formed from metallic materials, including but not limited to Nb, Cr, Cu, Mo and noble metals. The ladder pattern of the conductive layer 10 is created by a conventional photo lithographic liftoff process. The ladder includes two rails 11 and 12. The rails 11 and 12 provide cathode conduction from one end of the array line to the other, as shown in Fig. 2. With this arrangement, it is possible to position a linear array of conductive pads 13 spaced between the rails 11 and 12, as shown in Fig. 2. Without sub-dividing a pixel by a conductive mesh, additional micro tips may be packed within a pixel. This arrangement is possible because it is not necessary to sub-divide a pixel with a conductive mesh as in prior art devices.

A current limiter 23 is formed on the conductive layer 10, as shown in Fig. 3. The current limiter 23 includes a first resistive layer 21 formed on top of the conductive layer 10. The first resistive layer 21 contributes to the lateral resistance part of the current limiter. Additionally, the first resistive layer 21 provides inter-pixel uniformity control and a blow-out guard. The first resistor layer 21 may be formed, for example, from silicon or Cr+SiO. If Cr+SiO is used, a 10%-30% Cr content can provide a practical lateral sheet resistivity range for most display designs. The first resistor layer of the present invention is not limited to the above-identified materials. Other suitable materials, including but not limited to Au+SiO, Pt+TaO₅, Ni+Cr, impurity doped Si or leaky Al₂O₃, are contemplated to be within the scope of the present invention. A second resistive layer 22 is deposited on top of the first resistive layer 21. The second resistive layer 22 forms a vertical resistor that individually current limits each single emitter. The second resistor layer 22 may also be Cr+SiO or some other conductor-doped tunnel barrier reduced insulator. If Cr+SiO is used, a 5%-15% Cr content can provide a practical vertical bulk resistivity range for most display designs. A layer of a dielectric planarization material 30 and a layer of a dielectric coating 40 are deposited over the second resistive layer 22. A conductive gate layer 50 overlays the dielectric planarization material 30 and the dielectric coating 40. The conductive gate layer 40 is deposited in a series of gate lines. The gate lines are orthogonal with respect to the alignment of the conductive rails 11 and 12. Arrays of micro-cavities 61 are etched through the gate lines into the layer of dielectric planarization material 30 and the dielectric coating 40, as shown in Fig. 3. A cone-shaped emitter 60 is formed in each cavity 61. The base of the emitter 60 is in contact with the second resistive layer 22. The tip of the emitter 60 is located in the aperture formed in the conductive gate layer 50. Fig. 5 illustrates an alternative embodiment of the present invention. As in the first embodiment, a substrate 10 may be coated with a dielectric layer 20. This dielectric layer 20 may be formed from, for example, SiO₂ or Si₃N₄. A metal conductor layer 700 is formed on the dielectric layer 20, as shown in Fig. 4. An insulating layer 800 is formed on the metal conductor layer 700. A conductive structure 100 is formed on the dielectric layer 20. As in the first embodiment, the conductive structure 100 may be formed from, for example, Nb, Cu, Cr or Mo.

In this alternative embodiment, a ladder pattern of the conductive structure 100 is created by a conventional photo lithographic liftoff process and includes two rails 110 and 120. The rails 110 and 120 provide cathode conduction from one end of the array line to the other, as shown in Fig. 4. A linear array of conductive pads 130 spaced between the rails 110 and 120, as shown in Fig. 4. In this alternative embodiment, the side rails 110 and 120 are formed with tapered edges which connect to the metal conductor layer 700 at the sides of the line.

As in the first embodiment, a current limiter 230 is formed on the conductive structure 100. The current limiter 230 includes a first resistive layer 210 formed on top of the conductive structure 100. In this alternative embodiment, the first resistive layer 210 has tapered edges which conform to the tapered edges of the side rails 110 and 120. The first resistive layer 210 contributes to the lateral resistance part of the current limiter. Additionally, the first resistive layer 210 provides inter-pixel uniformity control and a blow-out guard. The first resistor layer 210 may be formed, for example, from silicon or Cr+SiO. If Cr+SiO is used, a 10%-30% Cr content can provide a practical lateral sheet resistivity range for most display designs. The first resistor layer of the present invention is not limited to the above-identified materials. Other suitable materials, including but not limited to Au+SiO, Pt+TaO₅, Ni+Cr, impurity-doped Si or leaky Al₂O₃, are contemplated to be within the scope of the present invention.

A second resistive layer 220 is deposited on top of the first resistive layer 210. In this alternative embodiment, the second resistive layer 220 has tapered edges which conform to the tapered edges of the side rails 110 and 120. The second resistive layer 220 forms a vertical resistor that individually current limits each single emitter. The second resistor layer 210 may also be Cr+SiO or some other conductor-doped tunnel barrier reduced insulator. If Cr+SiO is used, a 5%-15% Cr content can provide a practical vertical bulk resistivity range for most display designs. As in the first embodiment, a layer of a dielectric planarization material 300 and a layer of a dielectric coating 400 are deposited. A conductive gate layer 500 overlays the dielectric planarization material 300 and the dielectric coating 400. The conductive gate layer 400 is deposited in a series of gate lines. The gate lines are orthogonal with respect to the alignment of the conductive rails 110 and 120. Arrays of micro-cavities are 610 are etched through the gate lines into the layer of dielectric planarization material 300 and the dielectric coating 400 as shown in Fig. 3. A cone-shaped emitter 600 is formed in each cavity 610. The base of the emitter 600 is in contact with the second resistive layer 220. The tip of the emitter 600 is located in the aperture formed in the conductive gate layer 500. The current limiters according to the present invention have two layers of different resistive films, (i.e., a vertical resistor and a lateral resistor). This is an improvement over the known current limiters that are one layer structures, because in these one-layer structures, the resistivity, the emitter base and pitch, the pixel size and the space between the rail (or mesh) and the pad are all inter-related. Where the current limiter structure is a single layer, the choice of the material and the thickness of the film for lateral resistivity is restricted by the choice of material for vertical resistivity and vice versa. To satisfy both vertical and lateral resistance requirements, each time a change of the base and pitch of the emitter takes place, the resistivity plus either the pixel size, or the space between the mesh and the pad, or both, have to be changed correspondingly. The problem lies in the increasing demand of new mask-making, especially if the emitter features are created by the maskless laser photo lithographic technology, which easily permits changing the base and pitch of the emitters.

In a preferred embodiment of the present invention, the top vertical resistive layer is more than 0.1 micron thick for practical field breakdown protection but also less than 10 microns thick for cost effective fabrication and the resistivity is determined by device requirement and geometric configuration. The bottom lateral resistive layer is more conductive than the top resistive layer, with a practical thickness range of 10 nm to 10 microns.

The advantage of the bilayer structure over the single layer structure for a current limiter becomes obvious through the following derivation and analysis. This analysis is intended only to demonstrate the advantage of a bilayer current limiter structure over a single layer current limiter structure, and does not attempt to describe exhaustively the current limiter mechanism. To formulate the mechanisms of the disclosed current limiter exhaustively, a more sophisticated model including non-ideal cases, operating conditions, emission characteristics, load line approach and so

on would be needed. Referring to Fig. 6, let R_L ^r, R , R_L ^B, Rz³, and n represent the lateral and

vertical resistance of top and bottom resistive layers 220 and 210, respectively, and total number of 5 the emitters per pixel, respectively. For an ideal case, assume that there is no pinhole or defect in the vertical resistor and that the resistance of the current limiter is sufficiently high to provide a ballast against excessive current drawn by the electron emitters. In the ideal case, the total current limiter resistance per emitter, R_CL can be simply written as

Ό n B

10 R r CLi. - R v^τ ₊ R v° ₊ ±./ ^ _r ^x ^ Ω ^B . (i)

; = 1

The total resistance consists of two parts: the predominant intra-pixel current limiting part (provided by the vertical resistance) and the blow out guard (provided by inter-pixel lateral resistance),

ι R Intra-pixel = R VJ ₊R_V V^B ( ^v2) '

and

20

where intra-pixel resistance is the resistance between the pad and an emitter within the pixel, whereas the inter-pixel resistance is measured from the pad to the cathode electrode. It is clear that the intra-pixel resistance is independently controlled by the top layer resistance and the inter-pixel resistance is from the bottom layer alone. The fact that the vertical and lateral resistors are 25 independent from each other gives a wider range of selection for resistive materials. Using two layers of resistive materials, the lateral resistor becomes independent from the vertical resistor, and thus the change of resistance value for lateral resistor can be achieved by simply changing the Cr+SiO concentration for Cr+SiO resistor or dopant concentration for Si resistor, which no longer requires new photo-masks. The resistivity for the second resistive layer 220 is determined by the device requirement on emission current density, the geometric configuration of the device including emitter base and pitch dimensions, and the resistive film thickness. In the ideal case, the current flow across the current limiter is equal to all of n emitters. The distance from the pad to the rail of the ladder is determined by the pixel resistance requirement. If the overall pixel resistance ratio between the top layer and the bottom layer is about 100:1 (10-1000:1 is the practical range), then the lateral resistivity effect will be 1% or less of the vertical resistance and can be ignored. Likewise, the vertical resistance at each emitter will be so large as to dwarf the lateral resistance, so it may be expressed as

*_* - R. (4)

For example, 500MΩ/emitter vertical resistance in 1000 emitter pixel would have a 0.5MΩ/pixel overall vertical resistance. If this display has a 50MΩ/pixel lateral resistance, the vertical resistance per pixel would only be 1% of the horizontal resistance. This permits the interpixel resistance to be controlled by the accurate horizontal resistance, while the emitters placed close together in each pixel are forced to share current, even if a single emitter exhibits a low threshold turn-on. The vertical resistance can vary across the substrate by 50% and only effect the pixel to pixel brightness variation by < 1%.

Fig. 7 shows an equivalent electrical circuit for the preferred current limiter structure after the analysis. It includes a vertical resistor so that the individual resistance to an emitter is provided. It also has a lateral resistor for each pixel, so that any direct short between an emitter and the cathode electrode is eliminated, although a short between the emitter and the pad due to a pinhole in the vertical resistance film is still possible. It is noteworthy that even where a pinhole exists, some non-preferred emitters may not be problematic, depending on emitter geometric configuration. For example, when an emission-preferred tip is on a pinhole, the lateral resistor will make up the difference. By providing some current limiting, although not sufficient to achieve a uniform display, the lateral resistor helps to slow down the burn-in process so that an emitter on a pinhole will be burned gradually in a controlled fashion and eventually will become non-emissive, without causing any catastrophic blow-out. The parameters of the burn-in process should be determined in such a way that emitters ranging from geometrically-preferred to non-preferred (referring to the structure without a current limiter) on the pinholes will be burned sequentially. Since a vertical short caused by a pinhole is no longer a problem after the burn-in process is completed, the rest of the emitters will enjoy the benefit of the vertical resistor, namely, an individual resistance for each single emitter. Then, a uniform display will be achieved.

The disclosed current limiter of the present invention, therefore, has three major advantages when compared with existing current limiter structures. First, it provides individual resistance for each emitter from the vertical resistor. Second, it prevents catastrophic blow-outs by means of the lateral resistor. Additionally, it provides independently-controlled resistances for the vertical and lateral resistors, means of the two layer structure, as illustrated by the equivalent electrical circuit of Fig. 7, which reveals the final stage after burn-in treatment, within <2% uncertainty. It will be apparent to those skilled in the art that various modifications and variations can be made in the preparation and configuration of the present invention without departing from the scope or spirit of the invention. Thus, it is intended that the present invention cover the modifications and variations of the invention, provided that they come within the scope of the appended claims and their equivalents.

Claims

What is claimed is:

1. A field emission display device, comprising: an insulating substrate; a cathode conductive layer formed on said insulating substrate; a first resistive layer formed on said cathode conductive layer; and a second resistive layer formed on said first resistive layer.

2. The field emission display device of Claim 1, wherein said cathode conductive layer is formed into a ladder pattern comprising a first side rail, a second side rail, and a linear array of conductive pads spaced between said rails.

3. The field emission display device of Claim 1, further comprising a dielectric insulating layer is formed on said second resistive layer.

4. The field emission display device of Claim 3, further comprising a conductive gate layer is formed on said dielectric insulating layer.

5. The field emission display device of Claim 4, further comprising an array of micro- cavities is etchably provided through said dielectric insulating layer and said conductive gate layer.

6. The field emission display device of Claim 5, wherein an emitter is formed in each of said micro-cavities.

7. The field emission display device of Claim 6, wherein said cathode conductive layer is formed into a ladder pattern comprising a first side rail, a second side rail, and a linear array of conductive pads spaced between said rails.

8. The field emission display device of Claim 6, wherein said insulating substrate is first coated with a dielectric layer.

9. The field emission display device of Claim 6, wherein said gate layer comprises a plurality of gate lines orthogonal to the alignment of said array of said side rails.

10. The field emission display device of Claim 6, wherein said second resistive layer comprises an upper surface and a lower surface.

11. The field emission display device of Claim 6, wherein said emitter base is in contact with said upper surface of said second resistive layer.

12. The field emission display device of Claim 6, wherein said first resistive layer consists of low-resistivity material.

13. A current limiter for a field emission flat panel display, comprising: an insulating substrate; a cathode conductive structure formed on said insulating substrate; a first resistive layer formed on said cathode conductive structure; a second resistive layer formed on said first resistive layer; a first dielectric insulating layer formed on said second resistive layer; and a conductive gate layer formed on said dielectric insulating layer.

14. The field emission display device of claim 13, wherein said cathode conductive structure is formed into a ladder pattern comprising a first side rail, a second side rail, and a linear array of conductive pads spaced between said rails.

15. The field emission display device of Claim 13, wherein the pixel resistance ratio of said second resistive layer to said first resistive layer is from 10:1 to 1000:1.

16. The field emission display device of claim 13, wherein said first resistive layer consists of low-resistivity material.

17. The field emission display device of claim 13, wherein said second resistive layer consists of high-resistivity material.

18. The field emission display device of Claim 13, wherein said second resistive layer has a thickness between 0.1 and 10 microns.

19. The field emission display device of Claim 13, wherein said first resistive layer has a thickness between 10 nm and 10 microns.

20. The field emission display device of Claim 13, wherein a second dielectric insulating layer is formed on said insulating substrate.

21. The field emission display device of Claim 20, wherein stripes of a metal conductive layer are formed on said second dielectric insulating layer.

22. The field emission display device of Claim 21, wherein an insulating layer is formed on said stripes of said metal conductive layer.

23. The field emission display device of Claim 13, wherein said cathode conductive ladder comprises first tapered edges.

24. The field emission display device of Claim 23, wherein said first tapered edges of said cathode conductive layer ladder connect to said stripes of said metal conductive layer.

25. The field emission display device of Claim 23, wherein said first resistive layer further comprises second tapered edges.

26. The field emission display device of Claim 25, wherein said second resistive layer further comprises third tapered edges.

27. The field emission display device of Claim 26, wherein said second tapered edges of said first resistive layer and said third tapered edges of said second resistive layer connect with said first tapered edges of said cathode conductive ladder at said stripes of said metal conductive layer.

28. A method for fabricating a current limiter for a field emission structure, said method comprising the steps of: forming an insulating substrate; forming a cathode conductive structure on said insulating substrate; forming a first resistive layer on said cathode conductive layer; forming a second resistive layer on said first resistive layer; forming a dielectric insulating layer on said second resistive layer; forming a conductive gate layer on said dielectric insulating layer; etching an array of micro-cavities through said dialectic insulating layer and said conductive structure; and forming an array of emitters in said microcavities.

29. The method of Claim 28, wherein said cathode conductive structure is formed into a ladder pattern comprising a first side rail, a second side rail, and a linear array of conductive pads spaced between said rails.

30. The method of Claim 29, wherein said ladder pattern of said cathode conductive structure is formed by a photo lithographic liftoff process.