WO1999000831A1 - Method of manufacturing semiconductor devices - Google Patents

Method of manufacturing semiconductor devices

Info

Publication number
WO1999000831A1
WO1999000831A1 PCT/JP1998/002907 JP9802907W WO9900831A1 WO 1999000831 A1 WO1999000831 A1 WO 1999000831A1 JP 9802907 W JP9802907 W JP 9802907W WO 9900831 A1 WO9900831 A1 WO 9900831A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
semiconductor device
surface
wiring
tool
method
Prior art date
Application number
PCT/JP1998/002907
Other languages
French (fr)
Japanese (ja)
Inventor
Nobuo Kayaba
Takashi Nishiguchi
Hidemi Sato
Tetsuo Ookawa
Hiroyuki Kojima
Yuko Kawamori
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers

Abstract

Conventional methods of manufacturing semiconductor devices are such that semiconductor devices are insufficient in flattening, great in surface step difference, and liable to cause wiring disconnections in the case of multilayer interconnection, causing reduction in yield. Also, with the conventional methods, fine wiring has been difficult due to insufficiency in depth of focus in lithography, and more complicated processing technique and an increase in the number of processes have posed problems. Further, with a flattening method by polishing, the larger wafers forming semiconductor devices, the larger polishers used, so that more auxiliary materials such as abrasive grain and polishing pads are needed and much labor is required for replacing polishing pads. Further, these methods have disadvantages that the flatness of worked surfaces is degraded due to abrasion of polishing pads during working and a polishing efficiency becomes unstable. Also, these methods involve such a problem that working with a grindstone may cut wiring due to a wavy wafer. A method of manufacturing semiconductor devices of the invention is characterized in that the warp on the surface of a semiconductor device is corrected based on the that surface or the top surface of wiring and cuts of predetermined sizes are provided between a tool and the surface of the semiconductor device or the top surface of wiring based on the surface of the semiconductor device or the top surface of wiring to flatten layer insulation films.

Description

Method for producing the art of Akira fine manual semiconductor device

This invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device for planarizing the interlayer insulation 緣膜 surface for insulating wiring and its upper wiring of a semiconductor device. BACKGROUND

Conventionally, in order to achieve the flattening of an interlayer insulation 緣膜 surface of the semiconductor device has been subjected to flattening with SO G in the interlayer insulation 緣膜 surface having the concave convex. While the teeth "^, and take to advance miniaturization and multi-layered pattern, focus margin of exposure light decreases, sufficient effect can not be obtained, in recent years, IBM Journal of Research and development vo I .36, No .5, and Sep t embe r 1992 p845, 199 3 fiscal Society for precision Engineering, as seen in the spring meeting of the academic lecture 佘 Proceedings P839, elastic rotating the workpiece while supplying a polishing liquid containing a processing abrasive grains pressed against the pad, while providing relative movement, are needed use also a chemical mechanical polishing (CMP) comprising a polishing method for polishing preferentially with abrasive the parts of the convex irregularities of the workpiece surface.

In the conventional method, planarization insufficient § Li, surface unevenness is large, the case of multilayer wiring, disconnection of wiring is causing the resulting easily yield loss. In addition, it difficult to miniaturization of wiring due to focal depth shortage of lithography. Further, complexity of process technology, the problem of an increase in number of steps there ivy. Furthermore, the planarization method using grinding, as the dimensions of the wafer to form a semiconductor device increases, by greater grinding machine used Li, becomes large amount of auxiliary material, such as abrasive grains Ya polishing pad. You can also require the exchange this multi-sized effort of the polishing pad, Li the flat stand of deterioration Nyori processing surface of the polishing pad during processing has deteriorated, polishing efficiency there is a problem that is not stable. In order that the wafer is wavy, the processing by the grindstone, there is a problem that arise as to cut the wire.

The present invention eliminates the need for polishing pads and abrasive grains, and an object of the invention to provide a method of manufacturing a semiconductor device planarization of high accuracy can be realized. Disclosure of the Invention

The present invention corrects the waviness of a semiconductor device, the processing after the semiconductor device had with wire top is flat fixed relative to the interlayer insulation 緣膜 top, by the cutting or grinding Li, the semiconductor device in parallel with the reference plane it is intended to. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a perspective view of a first embodiment of a processing apparatus used in the method of manufacturing a semiconductor device of the present invention, FIG. 2, the expansion of the processing apparatus according to a first embodiment of the present invention is a sectional view, FIG. 3 is a sectional view of a second embodiment of the processing apparatus used to manufacture how the semiconductor device of the present invention, Fig. 4, a method of manufacturing a semiconductor device of the present invention a cross-sectional view of a third embodiment of the processing apparatus used in, Fig. 5, § sectional view of a fourth embodiment of the pressurized E apparatus used in the method of manufacturing a semiconductor device of the present invention Li, FIG. 6 is a sectional view of a fifth embodiment of the processing apparatus used in the method of manufacturing a semiconductor device of the present MizunotoAkira, FIG. 7 is a semiconductor device which is processed flattened by the present invention it is a cross-sectional view. BEST MODE FOR CARRYING OUT THE INVENTION

In order to Setsujutsu by Li the present invention in detail, explain this I adversaries in the accompanying drawings.

Figure 1 is a processing device for implementing the method of manufacturing a semiconductor device according to the present invention, 1 0 the body of the processing apparatus, 2 0 corrects the semiconductor device (wafer) 5 0 sac Neri, flat fixed waviness correction unit for, 3 0 the tool for flat processing the surface of the semiconductor device 5 0, superabrasive or Ranaru grindstone example diamond like, 4 1 had use the metal bond diamond wheel as the tool 3 0 electrolytic Doretsushin grayed electrode for maintaining the sharpness of the diamond wheel when, 4 4 machining liquid supply unit consisting of pure water cooling and lubrication of machining tools 3 0 and the semiconductor device 5 0 purposes, 6 0 apparatus for measuring a semiconductor device 5 0 of the surface shape, 7 0 is a fixed apparatus for Keru Attach the waviness correction unit 2 0 in the processing apparatus main body 1 0.

Circular or semiconductor device 5 0 attached to it re 矯 Tadashibu 2 0 I is on the indexing table 8 0 where the linear shape, after correcting the waviness under profilometer 6 0, machining tool 3 0 is moving downward, is processed. Figure 2 is an enlarged view of the waviness correction unit 2 0 in the case of the first Nagaune Li correction method, the surface reference fixing jig 71 is capable remove from the fixed device 7 0, thin such as steel on one surface of 鈑 7 3, port one lath ceramic Bed-locking unit 7 2 is fixed, through drilled holes in the ceramic ring 7 4 dense outer peripheral, a structure that can be sucked into the vacuum ing. A position corresponding to the back of 銷板 7 3 Paula scan ceramic blocks 7 2, ceramic pro click group 7 5 is arranged.

Li by the above processing apparatus, a method of manufacturing a planar semiconductor device 5 0 of the surface will be described below. ♦

In FIG. 2 (a), the fixing device 7 0, then vacuum adsorbed on the basis of the interlayer Ze' film 5 second surface of the semiconductor device 5 0, opening the vacuum suction valve 7 8 semi conductor device 5 0 backside of the silicon substrate 5 3, the surface reference fixing jig 71 to vacuum suction Nyori fixed. The semiconductor device solid ¾ SumiOsamu device 71 to re secured by the vacuum suction to the back surface of the semiconductor device 5 0, the ceramic blocks 7 5 in a state where the surface reference fixing jig 71 is modeled on the back surface of the semiconductor device 5 0 the processed flattened, parallel to processing the semiconductor device 5 0 surface.

Next, by closing the vacuum suction valve 7 8, turn vacuum system of fixing device 7 0 in a state of being adsorbed to the semiconductor device 5 0 on the surface reference fixing jig 71, for surface reference fix the semiconductor device 5 0 It is inverted while being in close contact with the jig 71 is fixed by vacuum sucking the cell la Mick blocks 7 5 on the fixed device 7 0. Their to, during processing tool 3 0 and the semiconductor device 5 0, pure water from the working-fluid supply unit 4 4 rotates both while supplying, continue to reduce both the gap. In this case, as the super abrasive grains 3 1 does not damage the interlayer insulation 緣膜 5 2 of the semiconductor device 5 0 falling off, bond material and main barrel like to hold the superabrasive grains 3 1 of the processing tool 3 0 and then, as the processing precision grinding force by collapsing the eyes of the super abrasive grains 3 1 increases is not deteriorated, the particle size is preferably used less superabrasive 5 mu m. Moreover, the super abrasive grains 3 1 and to ^ cutting resistance due to clogging between the superabrasive 3 1 prevents the you increase the superabrasive 3 1 opposing electrolytic dressing electrode 4 1 part provided, also the partition walls 4 5 provided around the electrode 4 1, do sprayed the electrolytic solution 4 3 is et applied between the working tools 3 0 as the electrolytic solution does not scatter electrodes 4 1. - Note that the contact of the processing tool 3 0 and the semiconductor device 5 0, and by re-detecting sensor 7 6 arranged below the fixing device 7 0, semiconductor device 5 0 Moshiku machining tool 3 0 from the position any of the, Ri by the be displaced by an amount to be processed, leaving the interlayer insulation 緣膜 5 2 thick on the wiring 5 1 be only force [E fixed amount.

According to the processing of the above embodiment, as shown in FIG. 2 (b), a flat semiconductor device 5 0 interlayer insulating film 5 2 is obtained. Figure 3 is a large figure waviness correction unit 2 0 in the case of the second Nagaune Li correction method, the upper surface of the thin eg steel 2 3 the semiconductor device 5 0 of the porous ceramic for vacuum suction block group 2 4 are arranged, blocks 2 5 consisting of a rigid body such as ceramics position opposing the block group 2 4 porous ceramic is arranged on the lower surface. The bottom of the block group 2 5 Akuchiyueta 2 1, such as to correspond to each proc for example piezo element is arranged, Akuchiyue Ichita 2 1 proc group 2 5 also varying with the displacement Kuraishi, Akuchiyue Ichita the steel plate 2 3 corresponds to 2 1 has a structure that can be freely deformed.

By the processing device, a method of manufacturing a planar semiconductor device 5 0 of the surface below.

First, dummy semiconductor device 5 5 (, not shown) by and re fixed to the vacuum adsorption on the porous ceramic Bed-locking unit 2 4 waviness correction unit 2 0, the semi-conductor device 5 5 diamond processed by the tool 3 0 consisting of super abrasive grains 3 1 etc., and measures the surface shape measuring apparatus 6 0, allowed to store the shape in the computer 2 8 (Figure 1).

Then, vacuum suction with vacuum suction Nyori fixing the semiconductor device 5 0 on the porous ceramic pro click group 2 4 waviness correction unit 2 0, a gap 2 9 with blocks 2 5 and Akuchiyue Ichita 2 1 and, contacting the each block 2 5 and each Akuchiyue Ichita 2 1, the semiconductor device 5 0 is fixed in a state that follows the tip of Akuchiyue Ichita 2 1. The surface shape coordinates of the deposited interlayer insulation 緣膜 5 second surface on the semiconductor device 5 0 by measuring device 6 0 or semiconductors devices 5 0 wiring formed 5 1 coordinates on the measures, the computer 2 8 to the height from the reference plane that has been stored is applied to be constant in each Akuchiyue over data 2 1, the proc is on Riakuchiyue one data 2 1 by the dimensional change of Akuchiyue Ichita 2 1 2 5 and a porous ceramic each proc 2 4 is displaced, by correcting the semiconductor device 5 0 Nagaune Li, interlayer insulation 緣膜 5 2 surface of the semiconductor device 5 0, or wires 5 1 of the upper surface in advance in the computer 2 8 stored so that the surface shape and the same state was allowed.

In this state, a gap 2 9 with blocks 2 5 by vacuum suction, thereby the fixing block 2 4 close contact between the block 2 5 and the wall 2 7, and fixed. Next, the semiconductor device 5 0 while correcting the waviness, is rotated as indicated by an arrow A of FIG. 3, also made of super abrasive grains 3 1 such as diamond tools

3 0 also rotated as indicated by an arrow B of FIG. 3, the semiconductor device 5 0 and the tool 3 0 of both the gap while supplying pure water from the machining liquid supply unit 4 4 between superabrasive 3 1 Noto the reduced gradually.

In this case, as the super abrasive grains 3 1 does not damage the interlayer insulation 緣膜 5 2 of the semiconductor device 5 0 fall off, abrasive grains of the metal or the like to the tool 3 0 of bonding material to hold the superabrasive grains 3 1 using a large bonding material holding force, as superabrasive 3 1 eye collapsed Nyo processing precision Li grinding resistance is increased is not deteriorated, the particle size is preferably used less superabrasive 5 mu m. Further, in order to prevent the grinding resistance due to clogging Mari between superabrasive 3 1 and superabrasive 3 1 increases, the electrolytic dressing electrode 4 1 is provided in a portion facing the superabrasive 3 1, the partition wall around the electrode 4 1

4 5 is provided, the electrolytic solution is applied while blowing the electrolytic solution 4 3 between the tool 3 0 and the electrode 4 1 not scattered, is processed while dressing. The semiconductor device 5 0 and superabrasive 3 1 and the gap is small for re tool 3◦, when they are in contact, the contact resistance, deformation semiconductor device 5 0, the porous ceramic are more close contact with the vacuum suction since block group 2 4 and block group 2 5 is displaced, had there Akuchiyueta 2 1 under the block group 2 5 Li by the that you set up the gap sensor 1 8, the semiconductor device 5 0 and the tool 3 0 It can detect the contact between the superabrasive 3 1. The either of the semiconductor device 5 0 or tools 3 0 from that position, processed should amount only by the be displaced 'Li, the interlayer insulation 緣虡 5 2 of the semiconductor device 5 on the wiring 5 1 is formed on the surface of the 0 thickness It can be processed by a certain amount.

In this case, by processing reluctant such measures the thickness of the interlayer insulating film 5 2 profilometer 6 ◦, it can be processed into Yoridaka accuracy.

Figure 4 is a another embodiment, advance measurement the relationship Akuchiyue Ichita 2 1 displacement amount and the voltage when a force is bought or the Akuchiyueta 2 1 such as a piezoelectric element, always feedback during processing can be flat processed based on Li, semiconductor device 5 0 top or upper surface of the interlayer insulation 緣膜 5 second wiring 5 1 by the applying.

Further, at this time, along with the kill in detecting the position of contact by the displacement of Akuchiyue Ichita 2 1, after detecting the contact position, it is displaced by an amount to be pressurized E all Akuchiyue Ichita 2 1, deformation caused by processing pressure by the correcting the Li, the interlayer insulating film thickness of 5 4 on the wiring 5 1 can be processed into precisely constant.

Next, another embodiment will be described with reference to FIG. 5. 1 1 is a spindle for rotating the tool 3 0, it is supported by the fluid 1 5 and the bearing outer periphery 1 2. Spindle 1 1 and gap sensors 1 8 position opposing the flange portion 1 4 is arranged, which measures the flange 1 4 and the bearing outer periphery 1 2 of the axial gap 1-9. Attaching the near while the machining tool 3 0 and the semiconductor device 5 0 to times ¾. Contact resistance Nyori with both contacts, the main shaft 1 1 that attach the working tool 3 0 is displaced, detects by connexion contact to the gap between the main shaft flange 1 4 and the bearing outer periphery 1 2 is changed, the processing amount return by the increasing the rigidity of the fluid bearing by increasing the pressure of the fluid 1 5 when displaced by Li, the main shaft flange 1 4 the distance 1-7 between the bearing outer periphery 1 2 as 1 9 are the same, real qualitatively the semiconductor device 5 0 cuts during processing tool 3 0 is given, the surface of the semi-conductor device 5 0 is processed.

It will be described with reference to Figure 6 another embodiment. 7 7 'by a gap sensor for measuring the displacement of the correction unit 2 0, semiconductor devices' tool 3 0 or ridges Li' after correction of 5 0 of waviness, small gaps of the semiconductor device 5 0 and the tool 3 0 have Ki and the tool 3 0 or ridges when by measuring the amount of displacement of the tool 3 0 or waviness correction unit 2 0 in the gap sensor 7 7 Li, the semiconductor device 5 0 and the tool 3 0 is in contact contact is detected from the change of the displacement amount due to the inclination of Li correction unit, the tool 3 0 and even cowpea to provide a predetermined depth of cut between the semiconductor device 5 0, the interlayer insulating film thickness on the wiring 5 1 5 4 can be processed into a constant. Also, as in the embodiment shown in FIG. 5, by measuring the vibration of the tool spindle 1 1 by measuring means 4 2 detects the contact of the tool 3 0 and the semiconductor device 5 0, E instrument 3 0 and semiconductor even cowpea to providing cuts between the device 5◦, can be processed interlayer insulating film thickness of 5 4 on the wiring 5 1 constant.

For both embodiments described heretofore, is rotated while correcting the waviness of the semiconductor device 5 0 using a diamond byte (optional) instead of superabrasive grinding wheel to the tool 3 0, and diamond byte even cowpea to give a cut between the semiconductor device 5 0 can be processed interlayer insulation 緣膜 5 2 thick on the wiring 5 1 constant. Industrial Applicability

As described above, according to the present invention, the polishing pad and abrasive grains can be reduced cost becomes unnecessary, suitable residual management can and Do Re, as a manufacturing method of flatness semiconductor device with high ing.

Claims

Billed the range. Correcting undulations of the semiconductor device surface, based on the semiconductor device surface or the wiring upper surface, a predetermined amount between the tool and the semiconductor instrumentation 置表 plane or wiring upper surface relative to the semiconductor device surface or the wiring upper surface the method of manufacturing a semiconductor device characterized by flattening the re interlayer insulation 緣膜 by the giving cuts. . The method of manufacturing a semiconductor device in the range 1 wherein according to planarize the interlayer insulation 緣膜 semiconductor device, on the wiring after the wiring and the its upper wiring depositing an interlayer insulating film for insulating a semiconductor the device surface is fixed to the reference made Tan Taira surface, as E to flat machined deformation free fixture rear surface adsorbed to Semiconductors device back surface while correcting the waviness of the surface of the semiconductor device If, given a cut between the fixture rear surface of the reference to the tool and the semiconductor device surface, a step for detecting contact between the tool and the semiconductor device surface, a predetermined amount of switching between the tool and the semi-conductor device surface the method of manufacturing a semiconductor device characterized by comprising a step of providing a re included.
. The method of manufacturing a semiconductor device in the range 1 wherein according to planarize the interlayer insulation 緣膜 semiconductor device, on the wiring after the wiring and the its upper wiring depositing an interlayer insulating film for insulating the wiring measuring a top surface of the coordinates and or layers Maze' 緣膜 upper surface of the coordinate, and the back surface or found by displacing the semiconductor device by a plurality of Akuchiyue Ichita disposed 內部 of the jig for supporting the semiconductor device wiring upper surface or between about E for correcting undulation of interlayer insulation 緣膜 top, giving a cut between the tool and the semiconductor device surface, a step for detecting contact between the tool and the semiconductor device surface, the tool and the semiconductor device surface producing how the semiconductor device according to claim only comprising the step of flat removing a predetermined amount of the interlayer insulation 緣膜 surface of the semiconductor device by applying a predetermined amount of included Setsuri to.
. In the method for manufacturing 丰 ¾ body apparatus range Γ claim wherein according to planarize the interlayer insulation 緣膜 semiconductor device, on the wiring after the wiring and the its upper wiring was deposited interlayer insulation 緣膜 for insulating a step of measuring the coordinates of the coordinates and or layers Maze' 緣膜 upper surface of the wiring upper surface, wiring backside or we displace the semiconductor device by a plurality of Akuchiyue Ichita disposed within a jig that supports the semiconductor device more E for correcting an upper surface or waviness of the interlayer insulating film upper surface and gives a predetermined amount of included Setsuri between the tool and the semiconductor body surface of the device while measuring the thickness of the interlayer insulation 緣膜 surface of the semiconductor device, a semiconductor the method of manufacturing a semiconductor device characterized by comprising an interlayer Ze' film surface of the device and a step of planarizing removed by a predetermined amount.
. The method of manufacturing a range item 3 or 4 Kouki mounting of the semiconductor device according to planarize the interlayer insulation 緣膜 semiconductor device, the wiring upper surface or the interlayer by displacing the semiconductor device from the back by using a piezoelectric element to Akuchiyue Ichita to correct the waviness of absolute 緣膜 top, and characterized in that fixed while the flat wires upper surface or the interlayer insulation 緣膜 upper surface of the semiconductor device is only flatly remove a predetermined amount of the interlayer insulating film surface of the semiconductor device the method of manufacturing a semiconductor device to be.
. The method of manufacturing a range item 3 or 4 Kouki mounting of the semiconductor device according to planarize the interlayer insulating film of a semiconductor device, the wiring upper surface or the interlayer by displacing the semiconductor device from the back by using a piezoelectric element to Akuchiyue Ichita to correct the waviness of the insulating film top surface, based wiring upper surface or the interlayer insulation 緣膜 upper surface of the semiconductor device, to measure the semiconductor device table surface deformation amount due to processing power in the semiconductor device surface treatment, corrected by the piezoelectric element the method of manufacturing a semiconductor device, characterized in that only flat remove a predetermined amount of the interlayer insulation 緣膜 surface of the semiconductor device while.
7. The method of manufacturing a semiconductor device interlayer insulation 緣膜 semiconductor device ranging binomial or 3 Kouki mounting according to planarize the, a piezoelectric element disposed in the jig inner supporting the semiconductor device, the tool and the semiconductor device surface semiconductors and detecting the contact with a predetermined quantity of a given inclusive Setsuri, semiconductor device surface and the tool by a change in voltage of the Pied zone element when the tool is applied a force against the semiconductor device surface between the manufacturing method of the device.
8. The method of manufacturing a semiconductor device interlayer insulation 緣膜 range solid binomial or 3 Kouki mounting of the semiconductor device according to flattening of a plurality of gap sensors disposed jig inside which supports the semiconductor device, the tool and characterized but the detection child contact with Nyori semiconductor device surface and a tool to measure the displacement of the jig that secures the tool or a semiconductor device when a force Te person standing is applied to the semiconductor device surface the method of manufacturing a semiconductor device to be.
9. The method of manufacturing a semiconductor device in a range binomial or 3 Kouki mounting according to planarize the interlayer insulation 緣膜 semiconductor device, tool when force Te person standing is applied to the semiconductor device surface, supporting rotating tools method of manufacturing a semiconductor device and detecting shaft is made to, or by the displacement of the workpiece shaft supporting the jig for fixing the semiconductor device Li, the contact between the semi-conductor device surface and the tool .
1 0. The method of manufacturing a semiconductor body apparatus interlayer insulation 緣膜 description range @ 9 previous claims planarizing a semiconductor device, using a fluid bearing in the bearing of the tool shaft or the workpiece axis, the displacement Nyo re contact axis after detecting, a method of manufacturing a semiconductor device characterized by providing a predetermined amount of included Setsuri between the tool and the semiconductor device surface by changing the pressure of the fluid.
1 1. The method of manufacturing a semiconductor device of the interlayer insulation 緣膜 description range E 2 or Section 3 of claims planarizing a semiconductor device, when the tool is applied is connexion force per a semiconductor ^ device surface, the tool the change in the vibration of the shaft or the workpiece axis, a method of manufacturing a semiconductor equipment, characterized in that for detecting the contact between the surface of the semiconductor device and the tool.
2. A semiconductor device characterized in that it is produced with the production method Li flat surface as claimed in any one of claims 1, wherein to 1 1, wherein the.
PCT/JP1998/002907 1997-06-30 1998-06-29 Method of manufacturing semiconductor devices WO1999000831A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9/173522 1997-06-30
JP17352297 1997-06-30
JP17998798A JPH1174242A (en) 1997-06-30 1998-06-26 Manufacture of semiconductor device
JP10/179987 1998-06-26

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387807B1 (en) 2001-01-30 2002-05-14 Speedfam-Ipec Corporation Method for selective removal of copper

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7800232B2 (en) 2007-03-06 2010-09-21 Denso Corporation Metallic electrode forming method and semiconductor device having metallic electrode
JP4618295B2 (en) * 2007-07-26 2011-01-26 株式会社デンソー Metal electrode forming method of a semiconductor device
JP4858636B2 (en) 2009-09-29 2012-01-18 株式会社デンソー Metal electrode forming method and the metal electrode forming apparatus of a semiconductor device

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Publication number Priority date Publication date Assignee Title
JPH06196456A (en) * 1992-12-24 1994-07-15 Fujitsu Ltd Wafer polishing device and method
JPH06333891A (en) * 1993-05-24 1994-12-02 Sony Corp Substrate polishing apparatus and substrate holding table
JPH07130689A (en) * 1993-11-06 1995-05-19 Sony Corp Grinding device of semiconductor substrate
JPH07130686A (en) * 1993-10-29 1995-05-19 Nec Corp Grinding device of semiconductor substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06196456A (en) * 1992-12-24 1994-07-15 Fujitsu Ltd Wafer polishing device and method
JPH06333891A (en) * 1993-05-24 1994-12-02 Sony Corp Substrate polishing apparatus and substrate holding table
JPH07130686A (en) * 1993-10-29 1995-05-19 Nec Corp Grinding device of semiconductor substrate
JPH07130689A (en) * 1993-11-06 1995-05-19 Sony Corp Grinding device of semiconductor substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6387807B1 (en) 2001-01-30 2002-05-14 Speedfam-Ipec Corporation Method for selective removal of copper

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