WO1998039802A1 - Procede de production de circuit integre - Google Patents
Procede de production de circuit integre Download PDFInfo
- Publication number
- WO1998039802A1 WO1998039802A1 PCT/JP1998/000892 JP9800892W WO9839802A1 WO 1998039802 A1 WO1998039802 A1 WO 1998039802A1 JP 9800892 W JP9800892 W JP 9800892W WO 9839802 A1 WO9839802 A1 WO 9839802A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- integrated circuit
- circuit device
- semiconductor integrated
- manufacturing
- oxide film
- Prior art date
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Classifications
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28158—Making the insulator
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- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28158—Making the insulator
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- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- Y10S438/00—Semiconductor device manufacturing: process
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Definitions
- the present invention relates to a method for manufacturing a semiconductor integrated circuit device (semiconductor device and the like), and particularly to a technology effective when applied to the formation of a gate oxide film (insulating film) such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
- a gate oxide film insulating film
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- bubbling in which a carrier gas such as oxygen was passed through the water in a bubbler, was widely applied.
- this method has the advantage of covering a wide area and covering the water range, it cannot avoid the problem of contamination, and has recently been hardly used. Therefore, for the time being, the oxyhydrogen combustion method, that is, the Pyrogenic system, has been widely spread as a means for avoiding the disadvantages of this bubbler.
- Example 1 (1) Omi's Japanese Patent Application Laid-Open No. 6-163517 discloses a low-temperature oxidation technique for lowering the temperature of a semiconductor process.
- hydrogen was added from 100 ppm to 1% in a gas atmosphere consisting of about 99% argon and about 1% oxygen, and the combustion temperature of hydrogen was 700 ° C or less, that is, 45 ° C.
- a method for obtaining water vapor by the action of a stainless steel catalyst at a temperature of 0 degrees or less is shown.
- Example 2 thermal oxidation of silicon at an oxidation temperature of 600 ° C. under normal pressure or high pressure was shown in an atmosphere consisting of 99% of oxygen and 1% of steam generated by a catalyst. I have.
- Japanese Unexamined Patent Publication No. Hei 7-3211102 discloses an extremely low moisture concentration in order to avoid various problems caused by moisture, that is, an extremely low moisture region of about 0.5 ppm. Or high temperature thermal oxidation of silicon surface at oxidation temperature of 850 degrees Celsius in dry region It is shown.
- Japanese Patent Application Laid-Open No. 5-152282 discloses that the inner surface of a hydrogen gas inlet pipe is filled with N i ( It discloses a thermal oxidation device which is made of a nickel (Ni) or Ni-containing material and has a means for heating a hydrogen gas inlet tube.
- N i nickel
- Ni-containing material nickel
- hydrogen active species and oxygen water
- water is generated by reacting with oxygen-containing gas. That is, since water is generated by the catalytic method without combustion, the tip of the hydrogen-introduced quartz tube is not melted to generate particles.
- Japanese Patent Application Laid-Open No. 6-115903 discloses a mixed gas preparation step of mixing oxygen, hydrogen and inert gas to form a first mixed gas, By introducing the first mixed gas into a reactor tube made of a material having a catalytic action capable of radicalizing oxygen and heating the reactor tube, hydrogen and oxygen contained in the first mixed gas are removed.
- a catalyst-based water generation method comprising a water generation step of generating water by reaction is disclosed.
- a furnace tube having a core tube, a furnace tube heating means for heating the inside of the furnace tube, a gas inlet tube connected to and connected to the gas inlet, and a heating means for heating the gas inlet tube.
- a heat treatment apparatus is disclosed in which at least the inner surface of the gas introduction pipe is made of Ni (or a Ni-containing material).
- This thermal oxidizer is used to generate hydrogen activated species from hydrogen gas or a gas containing hydrogen without generating plasma, at a position upstream of the position of the object placed inside the furnace tube.
- a generating means is provided, and hydrogen gas or a gas containing hydrogen is introduced into the hydrogen active species generating means to generate hydrogen active species. For this reason, if a silicon substrate on which an oxide film is formed is placed as an object to be treated in the furnace core tube, hydrogen active species diffuse in the oxide film, and dangling bonds in the oxide film and at the oxide film Z silicon interface are formed. Termination, it is expected that a highly reliable gate oxide film will be obtained.
- Omi's Japanese Unexamined Patent Publication No. Hei 5-144804 discloses a heat treatment technique for a silicon oxide film by using hydrogen active species generated by a nickel catalyst.
- Page 3 shows a silicon oxidation process in a strongly reducing atmosphere, mainly composed of hydrogen generated by hydrogen radicals and moisture generated by a catalyst for application to the tunnel oxide film of flash memory.
- Gate oxide be formed to an extremely small thickness of 10 nm or less in order to maintain the electrical characteristics of miniaturized devices.
- the gate oxide film thickness is about 9 nm, but when the gate length is 0.25 ⁇ , it is expected to be as thin as about 4 nm.
- a thermal oxide film is formed in a dry oxygen atmosphere.
- a conventional method using a wet oxidation method generally, a moisture content method
- pressure ratio of several tens./. Or more has been used.
- water is generated by burning hydrogen in an oxygen atmosphere, and this water is supplied together with oxygen to the surface of a semiconductor wafer (a wafer for integrated circuit manufacturing or simply an integrated circuit wafer) to form an oxide film.
- a semiconductor wafer a wafer for integrated circuit manufacturing or simply an integrated circuit wafer
- sufficient oxygen is supplied beforehand to avoid the danger of explosion before igniting the hydrogen.
- the water concentration of the water + oxygen mixed gas which is an oxidizing species, is increased to about 40% (the partial pressure of water in the total atmospheric pressure).
- the combustion method described above ignites the hydrogen ejected from the nozzle attached to the tip of the quartz hydrogen gas inlet tube and performs combustion. If the amount of hydrogen is reduced too much, the flame approaches the nozzle too much For this reason, it has been pointed out that the heat melts the nozzles and generates particles, which are a source of contamination of the semiconductor wafer.
- the conventional oxide film forming method is capable of forming an ultra-thin gate oxide film having a high quality and a film thickness of 5 plates or less (the same effect can be expected for a film thickness of 5 nm or more). It is difficult to form a film with a uniform thickness with good reproducibility. Needless to say, there are various inadequacies where the film thickness is larger than the force. To form an ultra-thin oxide film with a uniform thickness and good reproducibility, reduce the oxide film growth rate compared to forming a relatively thick oxide film and perform film formation under more stable oxidation conditions.
- the method of forming an oxide film using the combustion method described above can only control the water concentration of the mixed gas of water and oxygen, which is an oxidizing species, within a high concentration range of about 18% to 40%. Therefore, the growth rate of the oxide film is high, and a thin oxide film is formed in an extremely short time.
- oxidation is performed by lowering the wafer temperature to 800 ° C or less to reduce the oxide film growth rate, the quality of the film deteriorates. It is needless to say that the present invention can be applied if the adjustment is made to).
- the actual oxide film includes the natural oxide film and the initial oxide film in addition to the oxide film formed by the original oxidation.
- the film is of lower quality than the intended native oxide film. Therefore, high quality
- the proportion of these low-quality films in the oxide film must be as low as possible.However, if an ultra-thin oxide film is formed using a conventional oxide film forming method, these low-quality films can be obtained. Rather, the proportion of the film increases.
- the native oxide film and the initial oxide film in this oxide film have a thickness of 0.7 nm and 0.8 nm, respectively.
- the ratio of the original oxide film to this oxide film is about 83. 3%.
- the native oxide film and the initial oxide film have the same thickness of 0.7 nm and 0.8 nm, respectively.
- Has a thickness of 4— (0.7 + 0.8) 2.5 nm, the ratio of which is reduced to 62.5%. That is, if an attempt is made to form an ultra-thin oxide film using a conventional oxide film formation method, not only cannot uniformity and reproducibility of the film thickness be ensured, but also the quality of the film deteriorates.
- 0 to 1 Oppm in terms of the partial pressure ratio of water belongs to the dry region and exhibits the so-called dry oxidation property, and the required film quality such as a gate oxide film in a future fine process will be reduced. It was clarified that the gain was not as good as the so-called ⁇ -oxidation.
- the ultra-low moisture region with a water partial pressure ratio of 1 Oppm or more and 1.0 X 10 3 ppm or less (0.1% or less) basically shows almost the same properties as dry oxidation. Revealed.
- a low moisture region having a water partial pressure ratio of 0.1% or more to 10% or less (of which The thermal oxidation in the water partial pressure ratio of 0.5% to 5% or less in the low-pressure region is caused by other regions (dry region, regions commonly used in combustion methods of 10% or more, and bubblers, etc.). It has been found by the present inventor that a relatively good property is exhibited as compared with a high moisture area having a water concentration of several tens% or more.
- An object of the present invention is to provide a technique capable of forming a high-quality ultrathin oxide film with a uniform film thickness with good reproducibility.
- the method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps (a) and (b).
- the oxide film is a MOS FET gate oxide film.
- the thickness of the oxide film is 3 nm or less.
- the heating temperature of the semiconductor wafer is from 800 ° C. to 900 ° C.
- the main surface of the semiconductor wafer is subjected to an oxynitridation process to segregate nitrogen at an interface between the oxide film and the substrate.
- the formation of the oxide film is performed by single-wafer processing.
- the formation of the oxide film is performed by batch processing.
- the method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps (a) and (b).
- the concentration of the water is 40% or less. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the concentration of the water is 0.5 to 5%.
- the method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps (a) to (c).
- the second oxide film may be formed on a surface of the semiconductor wafer between a time after the removal of the first oxide film and a time when the second oxide film is formed.
- the total thickness of the initial oxide film is 2 of the total thickness of the second oxide film. 1 or less.
- the total thickness of the natural oxide film and the initial oxide film is one third or less of the entire thickness of the second oxide film.
- the method for manufacturing a semiconductor integrated circuit device includes the steps of: forming a first oxide film on a first region and a second region of a semiconductor wafer; and forming the first oxide film on the first region of the semiconductor wafer. And forming a second oxide film on the first insulating film remaining in the first region and the second region of the semiconductor wafer, wherein the first and second oxidations are performed. At least one of the films is formed by the above method.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- the ratio of the partial pressure of the synthesized water to the total pressure of the atmosphere is in the range of 0.5% to 5%, and the silicon on the wafer is in an oxidizing atmosphere where hydrogen is not dominant.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the ratio of the partial pressure of the synthesized water to the atmospheric pressure of the entire atmosphere is in the range of 0.5% to 5%, and in an oxidizing atmosphere containing oxygen gas and on a silicon wafer.
- a silicon oxide film to be a gate insulating film of a field effect transistor is formed on the above silicon surface by thermal oxidation under a condition where the surface is heated to 800 ° C. or more. Process.
- the method for manufacturing a semiconductor integrated circuit device further includes the following steps;
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- the partial pressure ratio of the synthesized water to the atmospheric pressure of the entire atmosphere is in the range of 0.5% to 5%, and in an oxidizing atmosphere containing oxygen gas, and the silicon surface on the wafer is Celsius.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- the ratio of the partial pressure of the synthesized water to the atmospheric pressure of the entire atmosphere is in the range of 0.5% to 5%, and the oxidizing atmosphere containing oxygen gas is used.
- a silicon oxide film to be a gate insulating film of a field-effect transistor is formed on the silicon surface in the oxidation processing section while supplying the wafer heated above through a narrow portion provided between the moisture synthesis section and the oxidation processing section around the wafer. Step of forming by thermal oxidation.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the method for manufacturing a semiconductor integrated circuit device further comprises the following steps;
- the method of manufacturing the above semiconductor integrated circuit device may further include the following. The process of;
- the method for producing a semiconductor integrated circuit device further comprises the following steps;
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the method for manufacturing a semiconductor integrated circuit device further comprises the following steps;
- the method for producing a semiconductor integrated circuit device further comprises the following steps;
- An electrode material to be a gate electrode is formed by vapor phase deposition without exposing the surface-treated wafer to the open air or other oxidizing atmosphere. About.
- the method for manufacturing a semiconductor integrated circuit device further comprises the following steps;
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- the method for producing a semiconductor integrated circuit device further comprises the following steps;
- the method for producing a semiconductor integrated circuit device further comprises the following steps:
- the method for producing a semiconductor integrated circuit device further comprises the following steps;
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the method for producing a semiconductor integrated circuit device further comprises the following steps;
- step (d) After the step (b), flattening the silicon surface to expose a portion of the silicon surface where a thermal oxide film is to be formed.
- the planarization is performed by a chemical mechanical method. And a method of manufacturing a semiconductor integrated circuit device.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the silicon surface on the wafer is heated with a lamp in an oxidizing atmosphere in which the ratio of the partial pressure of water to the atmospheric pressure is in the range of 0.5% to 5%.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the silicon surface on the introduced wafer is heated by a lamp under an oxidizing atmosphere in which the ratio of the partial pressure of moisture to the entire atmospheric pressure is 0.1% or more.
- the non-oxidizing atmosphere is mainly composed of a small amount of nitrogen gas.
- the non-oxidizing atmosphere may be a semiconductor integrated circuit device which is introduced into the oxidation processing section after being preheated to such an extent that water does not condense. Production method.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- the ratio of the partial pressure of water to the atmospheric pressure is in the range of 0.5% to 5%, and the silicon surface on the wafer is 800 ° C or more in an oxidizing atmosphere containing oxygen gas.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps;
- the ratio of the partial pressure of moisture to the atmospheric pressure in the entire atmosphere is in the range of 0.5% to 5%, and it becomes a flash memory tunnel insulating film on the silicon surface on the wafer in an oxidizing atmosphere containing oxygen gas. Forming a silicon oxide film to be formed by thermal oxidation.
- a first thermal oxide film is formed on the first silicon surface region on the wafer in the first oxidation processing section while supplying an atmosphere gas containing water generated by the catalyst to the first oxidation processing section.
- step (c) a step of generating moisture by burning oxygen and hydrogen before the step (a) or after the step (b);
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the wafer In an oxidizing atmosphere in which the ratio of the partial pressure of water to the atmospheric pressure in the entire atmosphere is in the range of 0.5% to 5%, the wafer is held in a state where the main surface of the wafer is kept substantially horizontal. Forming a silicon oxide film to be a gate insulating film of the MOS transistor by thermal oxidation on the silicon surface on the above main surface.
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps:
- the ratio of the partial pressure of the synthesized water to the entire atmospheric pressure is 0.5% to 5% in an oxidizing atmosphere, and the silicon surface on the wafer is 700 ° C or more. Under a heated condition, a silicon oxide film to be a field effect gate insulating film is formed on the silicon surface by thermal oxidation. (Other outlines of the present invention)
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps (a) and (b);
- a method of manufacturing a semiconductor integrated circuit device comprising the following steps (a) and (b); (a) a step of generating water by catalytic action from hydrogen and oxygen,
- a method for manufacturing a semiconductor integrated circuit device comprising the following steps (a) to (c);
- N The method of manufacturing a semiconductor integrated circuit device according to the item L, wherein the second oxide film is formed between a time after the removal of the first oxide film and a time when the second oxide film is formed.
- a total film thickness of the first oxide film and the second oxide film is not more than half of a film thickness of the entire second oxide film.
- a method for manufacturing a semiconductor integrated circuit device comprising:
- FIG. 1 is a fragmentary cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 2 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 3 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 4 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 5 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 6 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 7 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 8 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 9 is a schematic view of a single-wafer oxide film forming apparatus used for forming a gate oxide film.
- FIG. 10 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 11A is a schematic plan view showing an example of the configuration of the oxide film forming chamber
- FIG. 11B is a cross-sectional view taken along the line BB ′ of FIG.
- FIG. 12A is a schematic plan view showing another example of the configuration of the oxide film forming chamber
- FIG. 12B is a cross-sectional view taken along the line BB ′ of FIG.
- FIG. 13 is a schematic diagram showing a catalytic water-generation apparatus connected to a chamber of an oxide film formation chamber.
- FIG. 14 is a schematic view showing a part of FIG. 13 in an enlarged manner.
- FIG. 15 is an explanatory diagram showing an example of a sequence of forming a gate oxide film.
- FIG. 16 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 17 is a graph showing the dependency of the water concentration on the growth rate of the oxide film.
- FIG. 18 is a graph showing the dependency of the moisture concentration on the initial withstand voltage of the oxide film of the MOS diode.
- FIG. 19 is a graph showing the dependency of the water concentration on the amount of voltage change when a constant current is applied between the electrodes of the MS diode.
- FIG. 20 is an explanatory diagram showing a film thickness distribution of a gate oxide film in a wafer surface.
- FIG. 21 is a graph showing a breakdown of the components of the gate oxide film.
- FIG. 22 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 23 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 24 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 25 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 26 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 1 of the present invention.
- FIG. 27 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 2 of the present invention.
- FIG. 28 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 2 of the present invention.
- FIG. 29 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 2 of the present invention.
- FIG. 30 is a cross-sectional view showing another example of the configuration of the oxide film forming chamber.
- FIG. 31 is an explanatory diagram illustrating an example of a sequence of forming a gate oxide film.
- FIG. 32 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to Embodiment 2 of the present invention.
- FIG. 33 is a schematic view showing another example of the oxide film forming method according to the present invention.
- FIG. 34 is a fragmentary cross-sectional view showing another example of the method for manufacturing the semiconductor integrated circuit device according to the present invention.
- CM ⁇ SFET Complementary Metal Oxide Semiconductor Field Effect Transistor
- a semiconductor substrate 1 made of single-crystal silicon having a specific resistance of about 10 Qcm is heat-treated to form a thin silicon oxide film 2 with a thickness of about 1 Onm on its main surface (thermal oxidation process).
- a silicon nitride film 3 having a thickness of about 10 Onm is deposited on the silicon oxide film 2 by a CVD method.
- a photoresist 4 having an element isolation region opened is formed on the silicon nitride film 3, and the silicon nitride film 3 is patterned using the photoresist 4 as a mask.
- the silicon oxide film 2 and the semiconductor substrate 1 are sequentially etched using the silicon nitride film 3 as a mask, so that the semiconductor substrate 1 has a depth of about 35 Onm. Then, a thermal oxidation process at 900 to 115 ° C. is performed to form a silicon oxide film 6 on the inner wall of the groove 5a (thermal oxidation process A2).
- a silicon oxide film 7 of about 0 Onm As shown in FIG. 5, the silicon oxide film 7 is polished by a chemical mechanical polishing (CMP) method, and the silicon nitride film 3 is polished as shown in FIG.
- CMP chemical mechanical polishing
- the element isolation trench 5 is formed by leaving the silicon oxide film 7 only inside the trench 5a. Subsequently, a heat treatment at about 1,000 ° C. is performed to densify the silicon oxide film 7 inside the element isolation trench 5.
- a photoresist 8 in which a p-channel MOS FET formation region (left side of the figure) is opened is formed.
- an impurity for forming an n-type well is ion-implanted into the semiconductor substrate 1, and an impurity for adjusting the threshold voltage of the p-channel MOS FET is further ion-implanted.
- the impurity for adjusting the threshold voltage for example, P is used, and ions are implanted at an energy of 40 keV and a dose of 2 ⁇ 10 12 m 2 .
- Impurities for forming a p-type well are ion-implanted into the semiconductor substrate 1 using the photoresist 9 as a mask in the region where the SFET is formed (on the right side of the figure), and the threshold of the n-channel MOSFET is further increased.
- Implant impurities to adjust the voltage For example, B (boron) is used as an impurity for forming a p-type well, and ion implantation is performed at an energy of 200 keV and a dose of 1.0 ⁇ 10 13 / cm 2 .
- As the impurity for adjusting the threshold voltage for example, boron fluoride (BF 2 ) is used, and ions are implanted at an energy of 40 keV and a dose of 2 ⁇ 10 12 / cm 2 .
- the semiconductor substrate 1 is heat-treated at 950 ° C. for about 1 minute to expand and diffuse the n-type impurity and the p-type impurity, thereby obtaining a p-type impurity.
- An n-type well 10 is formed on the semiconductor substrate 1 in the channel type M-S FET formation region, and a p-type channel region 12 is formed near the surface thereof.
- a p-type well 11 is formed on the semiconductor substrate 1 in the n-channel type MOS FET formation region, and an n-type channel region 13 is formed near the surface thereof.
- a gate oxide film is formed on each surface of the n-type well 10 and the p-type well 11 by the following method (thermal oxidation process A3).
- FIG. 9 is a schematic diagram of a single-wafer oxide film forming apparatus used for forming a gut oxide film.
- the oxide film forming apparatus 100 is connected to a stage subsequent to a cleaning apparatus 101 for removing an oxide film on the surface of the semiconductor wafer 1A by a wet cleaning method before forming a gate oxide film.
- the semiconductor wafer 1A that has been subjected to the cleaning process in the cleaning apparatus 101 is transported to the oxide film forming apparatus 100 in a short time without being brought into contact with the atmosphere. Therefore, formation of a natural oxide film on the surface of the semiconductor wafer 1A during the time from the removal of the oxide film to the formation of the gate oxide film can be suppressed as much as possible.
- Semiconductor wafer 1 A loaded in the loader 1 02 of the cleaning device 1 01 is first transferred to the cleaning chamber 1 03 is subjected to cleaning treatment by for example NH 4 OH + H 2 ⁇ 2 + H 2 ⁇ like washing solution
- the wafer is transported to the hydrofluoric acid cleaning chamber 104, where it is subjected to a cleaning process using dilute hydrofluoric acid (HF + H 2 ⁇ ) to remove the silicon oxide film on the surface (Fig. 10).
- the semiconductor wafer 1A is transported to the drying chamber 105 and subjected to a drying process to remove water on the surface.
- the moisture remaining on the surface of the semiconductor wafer 1 A is Oxide film Since it causes structural defects such as Si-H and Si-OH at the Z-silicon interface and causes the formation of charge traps, it must be sufficiently removed.
- the semiconductor wafer 1A that has been dried is immediately transferred to the oxide film forming apparatus 100 through the buffer 106.
- the oxide film forming apparatus 100 is configured in a multi-chamber system including, for example, an oxide film forming chamber 107, an oxynitride film forming chamber 108, a cooling stage 109, a rhodano unloader 110, and the like.
- the transfer system 112 at the center of the apparatus is equipped with a robot hand 113 for loading (unloading) the semiconductor wafer 1A into (from) the above-mentioned processing chambers.
- the inside of the transfer system 112 is maintained in an atmosphere of an inert gas such as nitrogen in order to minimize formation of a natural oxide film on the surface of the semiconductor wafer 1A due to mixing with the air.
- the inside of the transfer system 112 is kept in an ultra-low moisture atmosphere of ppb level in order to minimize the adhesion of moisture to the surface of the semiconductor wafer 1A.
- the semiconductor wafer 1A carried into the oxide film forming apparatus 100 is first conveyed to the oxide film forming chamber 107 one by one or two by a robot hand 113.
- FIG. 11 (a) is a schematic plan view showing an example of a specific configuration of the oxide film formation chamber 107
- FIG. 11 (b) is a view taken along the line B—B ′ in FIG. 11 (a).
- FIG. 11 (a) is a schematic plan view showing an example of a specific configuration of the oxide film formation chamber 107
- FIG. 11 (b) is a view taken along the line B—B ′ in FIG. 11 (a).
- the oxide film forming chamber 107 includes a chamber 120 composed of a multi-walled quartz tube, and heaters 121 a and 122 for heating the semiconductor wafer 1 A are provided at an upper part and a lower part thereof. 1b is installed. Inside the chamber 120, a disk-shaped heat equalizing ring 122 for uniformly dispersing the heat supplied from the heaters 122a and 121b to the entire surface of the semiconductor wafer 1A is accommodated. A susceptor 123 holding the semiconductor wafer 1A horizontally is mounted on the upper part thereof.
- the heat equalizing ring 122 is made of a heat-resistant material such as quartz or silicon carbide (SiC), and is supported by a support arm 124 extending from the wall of the chamber 120.
- thermocouple 125 for measuring the temperature of the semiconductor wafer 1A held by the susceptor 123 is provided near the soaking ring 122.
- a heating method using a lamp 130 as shown in FIG. 12, for example, may be adopted in addition to a heating method using the heaters 12a and 12lb.
- Some of the walls of chamber 120 have water, oxygen and purge inside chamber 120
- One end of a gas introduction pipe 126 for introducing gas is connected.
- the other end of the gas introduction pipe 126 is connected to a catalytic moisture generator described later.
- a partition wall 128 having a large number of through holes 127 is provided, and gas introduced into the chamber 120 passes through the partition wall 128. Pass evenly into chamber 120 through hole 127.
- the other end of the wall of the chamber 120 is connected to one end of an exhaust pipe 129 for discharging the gas introduced into the chamber 120.
- FIG. 13 and FIG. 14 are schematic diagrams showing a catalytic-type water generating apparatus connected to the chamber 120.
- the moisture generator 140 includes a reactor 144 formed of a heat-resistant and corrosion-resistant alloy (for example, Ni alloy known as “Hastelloy”).
- a coil 144 made of a catalytic metal such as (platinum), Ni (nickel) or Pd (palladium) and a heater 144 for heating the coil 142 are housed.
- a process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen or Ar (argon) are stored in gas storage tanks 144a and 144b, Introduced from 144 c through piping 1 45.
- mass flow controllers 146a, 146b, 146c for adjusting the amount of gas, and on-off valves for opening and closing the gas flow path 147a, 147b, 1 47 c is installed, and the amount and the component ratio of the gas introduced into the reactor 14 1 are precisely controlled by these.
- the process gas (hydrogen and oxygen) introduced into the reactor 141 is excited by contact with the coil 144 heated to about 350 to 450 ° C, and hydrogen radicals are generated from hydrogen molecules. (H 2 ⁇ 2H + ), and oxygen radicals are generated from oxygen molecules (O 2 ⁇ 2 ⁇ —). These two radicals in order to be chemically very active, rapidly react to form water (2 H + + 0- ⁇ H 2 0). This water is mixed with oxygen in the connection section 148 and diluted to a low concentration, and is introduced into the chamber 120 of the oxide film formation chamber 107 through the gas introduction pipe 126.
- the oxygen film forming chamber 107 together with oxygen can be used.
- the concentration of water introduced into 20 can be controlled over a wide range and with high accuracy from an extremely low concentration of ppt or less to a high concentration of about 10%.
- the process gas is introduced into the reactor 141, water is instantaneously generated, so that a desired moisture concentration can be obtained in real time. Therefore, hydrogen and oxygen can be simultaneously introduced into the reactor 141, and there is no need to introduce oxygen prior to the introduction of hydrogen as in a conventional water generation system employing a combustion method.
- the catalyst metal in the reactor 141 a material other than the above-described metals may be used as long as it can radically convert hydrogen and oxygen.
- the catalyst metal in the form of a coil it can be processed into a hollow tube or a fine fiber filter, for example, and a process gas can be passed through it.
- the chamber 120 of the oxide film forming chamber 107 is opened, and the semiconductor wafer 1A is loaded on the susceptor 123 while introducing a purge gas (nitrogen) into the inside.
- the time from loading the semiconductor wafer 1A into the chamber 120 to loading it on the susceptor 123 is 55 seconds.
- the chamber 120 is closed, and purging gas is continuously introduced for 30 seconds to sufficiently exchange the gas in the chamber 120.
- the susceptor 123 is previously heated by heaters 121a and 122b so that the semiconductor wafer 1A is quickly heated.
- the heating temperature of the semiconductor wafer 1A is in the range of 800 to 900 ° C., for example, 850 ° C. When the wafer temperature is 800 ° C or lower, the quality of the gate oxide film is degraded. On the other hand, when the temperature is 900 ° C. or more, the surface of the wafer is likely to be roughened.
- FIG. 17 is a graph showing the dependency of the water concentration on the growth rate of the oxide film, wherein the horizontal axis represents the oxidation time and the vertical axis represents the oxide film thickness.
- the oxide film growth rate is the lowest when the moisture concentration is 0 (dry oxidation), and increases as the moisture concentration increases. Therefore, in order to form an ultra-thin gate oxide film with a thickness of about 5 nm or less with good reproducibility and a uniform film thickness, it is necessary to lower the moisture concentration and slow down the oxide film growth rate to achieve stable oxidation. It is effective to form a film under the conditions.
- Figure 18 is a graph showing the dependence of the moisture concentration on the initial withstand voltage of the oxide film of the M ⁇ S diode composed of the semiconductor substrate, the gate oxide film, and the gate electrode.
- the horizontal axis is one of the M ⁇ S diodes.
- the voltage applied to the electrode (gate electrode), and the vertical axis indicates the defect density in the gate oxide film.
- a good initial breakdown voltage was exhibited as compared to any of the formed gate oxide films.
- FIG. 19 is a graph showing the dependency of the water concentration on the amount of voltage change when a constant current (Is) is passed between the electrodes of the MOS diode.
- Is constant current
- FIG. 20 shows the thickness distribution of the gate oxide film formed using the oxide film forming apparatus 100 in the wafer surface.
- the wafer temperature is set at 850 ° C. and the oxidation is performed at a water concentration of 0.8% for 2 minutes 30 seconds is shown.
- the lower limit is the concentration at which the withstand voltage can be obtained, and the upper limit when the conventional combustion method is used should be within the range of about 40%, especially an ultra-thin gut oxide film with a film thickness of about 5 nm or less. It was concluded that the water concentration should be within the range of 0.5% to 5% in order to form a film with uniform thickness, good reproducibility and high quality. Can be
- FIG. 21 shows a breakdown of the components of the gate oxide film obtained by thermal oxidation.
- the graph on the right side of the figure shows the gate oxide film having a thickness of 4 nm formed by the method of the present embodiment described above.
- the graph on the right shows a gate oxide film with a thickness of 4 nm formed by the conventional method using the combustion method, and the graph on the left shows the gate oxide film with a thickness of 9 nm formed by the same conventional method.
- an integrated cleaning and oxidation treatment system is employed to minimize the contact with oxygen in the atmosphere between the pre-cleaning and the formation of the oxide film.
- the thickness of this native oxide film Prior to the formation of a controllable oxide film in the apparatus, the thickness of this native oxide film is increased from 0.7 nm (17.5% of the total film thickness) of the conventional method to 3 nm (total film thickness). (7.5%).
- the oxide film A purge gas is introduced into the chamber 120 of the formation chamber 107 for 2 minutes and 20 seconds, and the oxidizing species remaining in the chamber 120 is exhausted. Subsequently, the semiconductor wafer 1A is unloaded from the susceptor 123 in 55 seconds, and is unloaded from the chamber 120.
- the semiconductor wafer 1A is transported to the oxynitride film forming chamber 108 shown in FIG. 9, and the semiconductor wafer 1A is thermally processed in an NO (nitrogen oxide) or N 20 (nitrogen oxide) atmosphere. As a result, nitrogen is segregated at the interface between the gate oxide film 14 and the semiconductor substrate 1.
- the thickness of the gate oxide film 14 When the thickness of the gate oxide film 14 is reduced to about 5 nm, distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 becomes apparent due to a difference in thermal expansion coefficient therebetween, thereby inducing the generation of hot carriers. Nitrogen segregated at the interface with the semiconductor substrate 1 alleviates this distortion, so that the above oxynitridation can improve the reliability of the ultra-thin gate oxide film 14.
- the thickness of the gate oxide film 1 4 is increased about l nm.
- a gate oxide film having a thickness of 3 nm is formed in the oxide film formation chamber 107 and then subjected to an oxynitriding treatment, whereby the gate oxide film thickness can be set to 4 nm.
- NO when used, the oxynitriding process hardly increases the thickness of the gate oxide film.
- this CVD device is connected to the subsequent stage of the oxide film forming device 100, and the process from the formation of the gate oxide film to the deposition of the conductive film for the gate electrode is continuously and continuously performed. Contamination can be effectively prevented.
- a gate electrode 15 having a gate length of 0.25 ⁇ m is formed on the gate oxide film 14.
- the gate electrode 15 is formed by sequentially depositing a 15-nm-thick n-type polycrystalline silicon film and a 150-nm-thick non-doped polycrystalline silicon film on the semiconductor substrate 1 by CVD. These films are formed by patterning by dry etching using a mask.
- a p-type impurity for example, B (boron) is ion-implanted into the formation region of the p-channel MOSFET from a vertical direction and an oblique direction, and the region is formed.
- a p-type semiconductor region 16 and a p-type semiconductor region 17 are formed in the n-type well 10 on both sides of the gate electrode 14.
- an n-type impurity for example, P (phosphorus) is ion-implanted into the formation region of the n-channel type MOSFET from the vertical direction and the oblique direction, and n-type impurities are implanted into the p-type wells 11 on both sides of the gate electrode 14.
- the type semiconductor region 18 and the n-type semiconductor region 19 are formed.
- a silicon oxide film deposited on the semiconductor substrate 1 by the CVD method is anisotropically etched to form a 0.15 / m thick silicon oxide film on the side wall of the gate electrode 14.
- An inner spacer 20 is formed.
- the gate oxide film 14 on the p-type semiconductor region 17 and the gate oxide film 14 on the n-type semiconductor region 19 are removed.
- a p-type impurity for example, B (boron) is ion-implanted into a formation region of the p-channel type MOSFET to form a p + type semiconductor region 21 in the n-type well 10 on both sides of the gate electrode 14. I do.
- an n-type impurity for example, P (phosphorus) is ion-implanted into a region for forming the n-channel type MOSFET to form an n + type semiconductor region 22 on the p-type well 11 on both sides of the gate electrode 14.
- P phosphorus
- the TiSi 2 layer 23 is formed by heat-treating a Ti film deposited on the semiconductor substrate 1 by a sputtering method to react with the semiconductor substrate 1 and the gate electrode 14, and then etching the unreacted Ti film. Remove and form.
- a p-channel type MOSF ET (Qp) and an n-channel type MISF ET (Qn) are completed.
- connection holes 25 to 28 are formed in the silicon oxide film 24 deposited on the semiconductor substrate 1 by the plasma CVD method, and then, the sputtering method is formed on the silicon oxide film 24.
- the CMOS process of the present embodiment is almost completed.
- the manufacturing method of the MOS SFET of this embodiment will be described with reference to FIGS. 27 to 32.
- the Conventional isolation is used instead of isolation (Shal low Trench Isolation; STI).
- STI Shallow Trench Isolation
- the MFETSFET is, in principle, isolated around its periphery unless it shares the source or drain with other transistors. It will be surrounded by the area.
- a semiconductor substrate 1 is heat-treated to form a thin silicon oxide film 2 having a thickness of about 1 O nm on its main surface (thermal oxidation process B 1).
- a silicon nitride film 3 having a thickness of about 10 O nm is deposited by CVD.
- a photoresist 4 having an element isolation region is formed on the silicon nitride film 3, and the silicon nitride film 3 is patterned using the photoresist 4 as a mask.
- the semiconductor substrate 1 is heat-treated to form a field oxide film 40 in the element isolation region (thermal oxidation process B2).
- the first embodiment is applied to the surface of the active region of the semiconductor substrate 1.
- An ultra-thin gate oxide film 14 with a thickness of 5 nm or less is formed (thermal oxidation process B 3) in the same manner as described above (Fig. 32).
- FIG. 31 shows an example of a gate oxide film forming sequence using the vertical oxide film forming apparatus 150.
- the sequence in this case is almost the same as that in Fig. 15, but there is a slight time difference in loading and unloading the wafer.
- a hot-wall method is generally used, so that it is relatively important to add a small amount of oxygen gas to the purge gas so as not to substantially oxidize.
- MOSFET is formed on the main surface of semiconductor substrate 1 in the same manner as in the first embodiment. (Common items related to oxidation process, etc.)
- FIG. 9 is a schematic view of a single-wafer oxide film forming apparatus (multi-chamber method) used for forming a gate oxide film.
- the oxide film forming apparatus 100 performs cleaning for removing an oxide film (generally a surface film) on the surface of the semiconductor wafer 1A by a wet cleaning method (a dry method may be used) before forming a gut oxide film. Connected after device 101.
- a wet cleaning method a dry method may be used
- the semiconductor wafer 1A subjected to the cleaning processing in the cleaning apparatus 101 is degraded to the air (deteriorating other surface conditions such as an undesired oxidizing atmosphere).
- a general atmosphere can be transferred to the oxide film forming apparatus 100 in a short time without contact with the surface of the semiconductor wafer 1A between the time the oxide film is removed and the time the gate oxide film is formed. Formation of a natural oxide film can be suppressed as much as possible.
- the semiconductor wafer 1A that has been dried is immediately transferred to the oxide film forming apparatus 100 through the buffer 106.
- the oxide film forming apparatus 100 is configured by a multi-chamber system including, for example, an oxide film forming chamber 107, an oxynitride film forming chamber 108, a cooling stage 109, a loader / unloader 110, and the like.
- the transfer system 112 at the center of the apparatus is equipped with a robot hand 113 for loading (unloading) the semiconductor wafer 1A into (from) the above-mentioned processing chambers.
- an inert gas atmosphere such as nitrogen
- the pressure is made positive with an inert gas or the like, it is effective to prevent the mixing of undesired gas from the outside and from each processing chamber).
- the inside of the transfer system 112 is extremely low moisture atmosphere of ppb level (generally included in well-maintained vacuum degassing). Moisture is less than a few ppm).
- the semiconductor wafer 1A carried into the oxide film forming apparatus 100 is first transferred to the oxide film forming chamber 107 via the robot hand 113 in units of one or two wafers (generally, a single wafer is used). The force to indicate one or two sheets When specifying one or two sheets, they are transported as single sheet or two sheets, respectively.) As described above, FIG.
- FIG. 11 (a) is a schematic plan view showing an example of a specific configuration of the oxide film forming chamber 107 (the single-wafer apparatus in FIG. 9), and FIG. 11 (b) is a plan view of FIG. (a) is a cross-sectional view (oxidizing apparatus 1; hot-wall type single-wafer oxidizing furnace) along the line BB 'of (a).
- the oxide film forming chamber 107 includes a chamber 120 composed of a multi-wall quartz tube, and heaters 121 a and 122 b for heating the semiconductor wafer 1 A are provided above and below the chamber 120. (For hot wall type) is installed. Inside the chamber 120, there is housed a disk-shaped heat equalizing ring 122 for uniformly dispersing the heat supplied from the heaters 122a and 121b to the entire surface of the semiconductor wafer 1A. The semiconductor wafer 1A is held horizontally on top of it (by arranging the wafer surface almost horizontally with respect to the vertical gravity, the effect of the concentration distribution of the mixed gas can be eliminated. This is particularly important in increasing the diameter of the susceptor.
- the soaking ring 122 is made of a heat-resistant material such as quartz or SiC (silicon carbide), and is supported by a support arm 124 extending from the wall of the chamber 120.
- a thermocouple 125 for measuring the temperature of the semiconductor wafer 1A held by the susceptor 123 is provided.
- Heating of the semiconductor wafer 1A can be achieved by a heating method using heaters 121a and 121b as well as a lamp 13 as shown in Fig. 12 (oxidizer 2; A heating method based on 0 may be adopted.
- lamp heating can be started after the wafer is in the specified position, and when the lamp is turned off, the temperature on the wafer surface drops rapidly.
- the formed initial oxide film and the like can be reduced to a negligible extent.
- water is added by a lamp, it is effective to prevent the dew condensation by preheating not only the water introduction part but also the oxidation furnace itself to about 140 degrees Celsius.
- One end of a gas introduction pipe 126 for introducing water, oxygen, and purge gas into the chamber 120 is connected to a part of the wall surface of the chamber 120.
- the other end of the gas introduction pipe 126 is connected to the catalyst type water generator.
- a partition wall 128 having a large number of through holes 127 is provided in the vicinity of the gas inlet pipe 126, and gas introduced into the chamber 120 passes through the partition wall 128. It is evenly distributed in the chamber 120 through the hole 127.
- One end of an exhaust pipe 129 for discharging the gas introduced into the chamber 120 is connected.
- FIGS. 13 and 14 are schematic diagrams showing a catalytic-type water generating apparatus connected to the chamber 120.
- the water generator 140 includes a reactor 144 made of a heat and corrosion resistant alloy (for example, Ni alloy known as “Hastelloy”), and has a Pt inside thereof.
- a coil 144 made of a catalytic metal such as (platinum), Ni (nickel) or Pd (palladium), and a heater 144 for heating the coil 142 are housed.
- a process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen or Ar (argon) are stored in gas storage tanks 144a, 144b, 144b. Introduced from c through piping 1 4 5. In the middle of piping 1 45, mass flow controllers 1 46 a, 1 46 b, and 1 46 c that adjust the amount of gas, and on-off valves 1 4 7 a and 1 4 7 that open and close the gas flow path b and 147 c are installed, and the amount and the component ratio of the gas introduced into the reactor 141 are precisely controlled by these.
- the process gas (hydrogen and oxygen) introduced into the reactor 141 is about 350 to 450 ° C (for example, hydrogen at a hydrogen concentration of 4% or more in the presence of sufficient oxygen at normal pressure). Considering the safety of mass production equipment, it is desirable to introduce an oxygen-rich oxygen-hydrogen mixed gas into the reactor so that hydrogen does not remain.)
- hydrogen molecules generate hydrogen radicals (H 2 ⁇ 2 H + )
- oxygen molecules generate oxygen radicals (0 2 ⁇ 20.
- These two types of radicals Is very chemically active and reacts quickly to form water (2 H + + ⁇ - ⁇ H 20 ), which is mixed with oxygen in connection 148 It is diluted to a concentration and introduced into the chamber 120 of the oxide film formation chamber 107 through the gas introduction pipe 126. It is. In this case, it is also possible to dilute with Arugo down instead of oxygen. That moisture 1% as an atmosphere supplied to the oxidation reactor, a 99% argon.
- the oxygen film formation chamber 107 together with oxygen can be controlled.
- the concentration of water introduced into 20 can be controlled over a wide range and with high accuracy from an extremely low concentration of ppt or less to a high concentration of about 10%.
- hydrogen and oxygen can be simultaneously introduced into the reactor 141 (in general, oxygen is introduced slightly earlier for safety), as in the conventional water generation system that employs the combustion method. It is not necessary to introduce oxygen before introducing hydrogen.
- the catalyst metal in the reactor 141 any material other than the above-mentioned metals may be used as long as it can radicalize hydrogen or oxygen.
- the catalyst metal may be processed into, for example, a hollow tube or a fine fiber filter and the process gas may be passed through the inside.
- the moisture generation furnace 140, hydrogen sensor, filter, dilution unit, purge gas or dilution gas supply unit, and oxidation furnace connection are set to about 140 degrees Celsius to prevent dew condensation. Temperature controlled or heated.
- the hydrogen sensor is for detecting hydrogen remaining without being synthesized.
- the filter is a gas filter inserted so as to act as a kind of orifice so that if hydrogen combustion occurs in the oxidation furnace, it is not transmitted to the synthesis furnace. It is preheated to a temperature at which neither the purge gas, the diluent gas, nor moisture condenses (generally about 100 to 200 degrees Celsius) and supplied to the oxidation furnace.
- the diluent gas is also synthesized after preheating In the lamp heating furnace as shown in Fig. 12, it is necessary to consider the preheating of the furnace itself or the wafer itself. In this case, it is possible to preheat the wafer in the oxidation furnace by using the purge gas. In the case of lamp heating furnaces, it is necessary to pay special attention to the preheating mechanism to prevent condensation at the wafer introduction part. In case of misalignment, heating or controlling the temperature to about 140 degrees Celsius is relatively effective. In general, the oxidation process is performed in a steady state while supplying a predetermined atmosphere gas to the oxidation processing section at a constant flow rate, and constantly supplementing the consumed components with a new atmosphere gas. An example of a sequence for forming a gut oxide film using the oxide film forming apparatus 100 (FIG. 9) will be further described with reference to FIG.
- the chamber 120 (FIG. 11) of the oxide film forming chamber 107 (FIG. 9) is opened, and a purge gas (nitrogen) is introduced into the chamber (as shown in FIG. 15). Is A slight amount of oxygen or the like may be added to prevent surface roughness such as thermal etching of the wafer.)
- a purge gas nitrogen
- Load semiconductor wafer 1A onto susceptor 123 The time from loading the semiconductor wafer 1A into the chamber 120 to loading it on the susceptor 123 is 55 seconds.
- the chamber 120 is closed, and a purge gas is continuously introduced for 30 seconds to sufficiently exchange the gas in the chamber 120.
- the susceptor 123 is previously heated with a heater 121 a and 12 lb so that the semiconductor wafer 1 A is quickly heated.
- the heating temperature of the semiconductor wafer 1A is in the range of 800 to 900 ° C., for example, 850 ° C.
- the wafer temperature is 800 ° C or lower, the quality of the gate oxide film is degraded.
- the surface of the wafer tends to be rough.
- a combustion-type water generator 160 as shown in Fig. 33 (Oxidizer 4; Oxygen / Hydrogen combustion type or Hydrogen combustion type oxidation furnace) is attached to a Tuchi type oxide film formation device (Oxidation furnaces 1 to 3). It can also be formed.
- an oxidizing species containing a relatively high concentration of water is generated in the water generator 160, and oxygen is added to the oxidizing species to obtain an oxidizing species with a low moisture concentration.
- the valve (Vvent) is closed and the valve (Vprocess) is opened to send the oxidizing species to the oxide film forming apparatus.
- the above method requires that there be a dust source such as a valve just before the oxide film forming device, Although there are disadvantages as compared with the above-described catalytic method, such as a dead space caused by the provision of the catalyst, it is possible to realize a low moisture concentration of the oxidizing species and suppression of the initial oxide film.
- the method of forming an oxide film according to the present invention includes a tunnel oxide film 43 (thermal oxidation process C 1) and a second gate oxide film 4 of a flash memory having a floating gate 44 and a control gate 42. It can be applied to the case where 4 (thermal oxidation process C 2) is formed with a thin film thickness of 5 or less.
- the oxide film forming method of the present invention forms two or more types of gate oxide films having different film thicknesses on the same semiconductor chip, such as an LSI in which a memory LSI and a logic LSI are mixed on the same semiconductor chip. It can also be applied to the case.
- both a thin gate oxide film having a thickness of 5 nm or less (thermal oxidation process D 1) and a relatively thick gate oxide film having a thickness of 5 nm or more (thermal oxidation process D 2) are formed by the method of the present invention.
- a thin gate oxide film may be formed by the method of the present invention, and a thick gate oxide film may be formed by a conventional method.
- oxidation processes A3, B3, C1, C2, 01, etc. are the most effective processes using the catalytic moisture generation thermal oxidation method and the low moisture oxidation method.
- any of the oxidation apparatuses 1 to 4 shown in the present application can be applied to the first and second oxidation steps.
- the operating pressure during oxidation of each oxidation treatment apparatus is generally at normal pressure (600 Torr to 900 Torr), but may be reduced.
- the oxidation rate is easily set to be low, and there are additional effects such as the possibility of hydrogen explosion being reduced. It is also possible to perform high pressure oxidation. In this case, there is an advantage that a high oxidation rate can be realized at a relatively low temperature.
- a high-quality ultrathin gate oxide film having a thickness of 5 nm or less and a uniform thickness can be formed with good reproducibility, so that the gate length is 0.25 ⁇ or
- the reliability and manufacturing yield of a semiconductor integrated circuit device having a smaller MOSFET than that can be improved.
Description
Claims
Priority Applications (20)
Application Number | Priority Date | Filing Date | Title |
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TW093110289A TWI250583B (en) | 1997-03-05 | 1998-02-27 | Manufacturing method for semiconductor integrated circuit device |
TW090114046A TW577128B (en) | 1997-03-05 | 1998-02-27 | Method for fabricating semiconductor integrated circuit device |
TW094103535A TWI278932B (en) | 1997-03-05 | 1998-02-27 | Manufacturing method of semiconductor integrated circuit device |
TW089119829A TW471068B (en) | 1997-03-05 | 1998-02-27 | Method for fabricating semiconductor integrated circuit device with insulation film |
TW091102373A TWI233164B (en) | 1997-03-05 | 1998-02-27 | Method of making semiconductor integrated circuit device |
TW091102374A TWI227530B (en) | 1997-03-05 | 1998-02-27 | Manufacturing method of semiconductor integrated circuit device |
TW095107658A TWI278933B (en) | 1997-03-05 | 1998-02-27 | Method of making semiconductor IC device |
TW091102375A TWI227531B (en) | 1997-03-05 | 1998-02-27 | Manufacturing method of semiconductor integrated circuit device |
TW096101926A TW200746302A (en) | 1997-03-05 | 1998-02-27 | Method of making semiconductor IC device |
TW087102898A TW462093B (en) | 1997-03-05 | 1998-02-27 | Method for manufacturing semiconductor integrated circuit device having a thin insulative film |
TW090114047A TW577129B (en) | 1997-03-05 | 1998-02-27 | Method for fabricating semiconductor integrated circuit device |
US09/380,646 US6239041B1 (en) | 1997-03-05 | 1998-03-04 | Method for fabricating semiconductor integrated circuit device |
KR1019997008059A KR100551650B1 (ko) | 1997-03-05 | 1998-03-04 | 반도체 집적 회로 장치의 제조 방법 |
EP98905758A EP0973191A4 (en) | 1997-03-05 | 1998-03-04 | METHOD FOR PRODUCING A SEMICONDUCTOR INTEGRATED CIRCUIT |
US10/774,589 US6962881B2 (en) | 1997-03-05 | 2004-02-10 | Method for fabricating semiconductor integrated circuit device |
US10/774,588 US7008880B2 (en) | 1997-03-05 | 2004-02-10 | Method for fabricating semiconductor integrated circuit device |
US10/774,406 US6962880B2 (en) | 1997-03-05 | 2004-02-10 | Method for fabricating semiconductor integrated circuit device |
US11/132,289 US7250376B2 (en) | 1997-03-05 | 2005-05-19 | Method for fabricating semiconductor integrated circuit device |
US11/132,306 US7053007B2 (en) | 1997-03-05 | 2005-05-19 | Method for fabricating semiconductor integrated circuit device |
US11/808,805 US7799690B2 (en) | 1997-03-05 | 2007-06-13 | Method for fabricating semiconductor integrated circuit device |
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US09/494,036 Continuation US6518201B1 (en) | 1997-03-05 | 2000-01-31 | Method for fabricating semiconductor integrated circuit device |
US09/494,036 Division US6518201B1 (en) | 1997-03-05 | 2000-01-31 | Method for fabricating semiconductor integrated circuit device |
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US (14) | US6239041B1 (ja) |
EP (1) | EP0973191A4 (ja) |
KR (5) | KR100544258B1 (ja) |
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