WO1998038766A1 - Sample rate converter - Google Patents

Sample rate converter Download PDF

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Publication number
WO1998038766A1
WO1998038766A1 PCT/US1998/000832 US9800832W WO9838766A1 WO 1998038766 A1 WO1998038766 A1 WO 1998038766A1 US 9800832 W US9800832 W US 9800832W WO 9838766 A1 WO9838766 A1 WO 9838766A1
Authority
WO
WIPO (PCT)
Prior art keywords
sample
input
output
value
accumulator
Prior art date
Application number
PCT/US1998/000832
Other languages
French (fr)
Inventor
Peter Bo Holmqvist
Original Assignee
Ericsson, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson, Inc. filed Critical Ericsson, Inc.
Priority to EP98903524A priority Critical patent/EP0963633B1/en
Priority to EEP199900368A priority patent/EE9900368A/en
Priority to JP53763698A priority patent/JP4376973B2/en
Priority to KR10-1999-7007628A priority patent/KR100386549B1/en
Priority to AU60274/98A priority patent/AU732601B2/en
Priority to BRPI9807771-6A priority patent/BR9807771B1/en
Publication of WO1998038766A1 publication Critical patent/WO1998038766A1/en
Priority to HK00106064A priority patent/HK1026989A1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00Networks using digital techniques
    • H03H17/02Frequency selective networks
    • H03H17/06Non-recursive filters
    • H03H17/0621Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing

Definitions

  • This invention relates to the field sample rate converting of digital signals.
  • the present invention relates to a sample rate conversion method
  • Digital words, or samples represent the value of the data at a regular time
  • This regular interval is often referred to as the sample rate, and is typically
  • decimation A first common technique for sample rate reduction is called decimation. It is a first common technique for sample rate reduction. It is a first common technique for sample rate reduction. It is a first common technique for sample rate reduction. It is a first common technique for sample rate reduction. It is a first common technique for sample rate reduction. It is a first common technique for sample rate reduction. It is a first common technique for sample rate reduction. It is a first common technique for sample rate reduction. It is
  • the decimator reduces the input sample rate by an integer
  • an anti-aliasing filter may be very
  • Interpolation is the method frequently used for increasing the sample
  • the basic interpolator To increase the sample rate by /, the basic interpolator
  • samples are then filtered through an anti-aliasing low pass filter at the higher rate.
  • the interpolation method has some of the same basic drawbacks as
  • the desired rate is related to the available rate
  • the data may first be
  • interpolation and decimation factors put very tough constraints on the required low pass filters. To reduce the filter requirements, the interpolation and decimation may
  • decimation enables a wider range of rate conversions that is not limited to integer
  • x n is the n:th input sample
  • y m is if the m:th output sample
  • T x is the input sample period
  • T y is the output sample period
  • One drawback of the first order interpolation method is that it may be difficult
  • the present invention is a method and apparatus for sample rate conversion
  • invention is an interpolation method that provides the robustness of a table based
  • the method utilizes a integer accumulator to generate an output data stream
  • the method uses the integer accumulator to track the timing relation between input samples and output samples. Based on the value of the
  • the method determines if the correct input samples are being used to
  • the output sample is calculated as a
  • the apparatus of the present invention includes an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an input sample register, an
  • integer accumulator and preferably a bit shift register, all configured so as to
  • Figure 1 is a diagram depicting linear interpolation.
  • FIG. 2 is a logical flowchart of the present sample rate conversion method.
  • Figure 3 is a diagram depicting the timing relation between input samples
  • FIG. 4 is a logical flowchart of a simplified sample rate conversion method
  • FIG. 5 is a logical flowchart of a simplified sample rate conversion method
  • Figure 6 is block diagram of a preferred embodiment of the apparatus for a
  • FIG. 7 is a logical flowchart of a preferred embodiment of the controller for
  • the present inventive method is a variation of interpolation that uses an
  • integer accumulator 220 to facilitate calculation of the relative position in time of
  • a and B are chosen such that the ratio of A
  • a / B T x / T y
  • the input sample period T x is quantized into A steps.
  • A could be 1024 if B is 1296. However, if A is 64 then only 6
  • variable "ace" which tracks the relative positions in time for a pair of input samples
  • ace serves two functions. First, ace is
  • Figure 2 shows a logical flow chart for the present invention.
  • the integer accumulator 220 is set to zero and the variables m and n
  • Variable m is an integer counter representing the
  • n is an integer counter
  • the accumulator 220 contains an integer value representing the variable
  • the ace value check of box 30 represents a determination of
  • the current input sample period is defined as
  • period is from 4 seconds to 5 seconds.
  • the ace value check of box 70 represents a determination of
  • box 100 until there are no more samples (box 100), at which point it stops (box
  • sample rate is faster than the output sample rate, meaning that A is smaller than B.
  • A is 10 and B is 14, corresponding to an input sample rate of 1.4 kHz and an output sample rate of 1.0 kHz. Further, assume that
  • ace equals -4.
  • ace is incremented by A such that ace now equals 6 (-4).
  • ace is incremented by A so as to equal -2 (-12).
  • x n is that y m fell between x n and x n+1 .
  • variable ace is used to dynamically
  • variable ace is used by the process to verify that the
  • Figure 4 shows a simplified logical flow chart for when A is known to be
  • Figure 5 shows a simplified logical flow chart for when A is known
  • a value for A can be selected that
  • the division can be
  • A could equal 64 and B could equal 81. If so, then the input sample period T x
  • A were increased to 1536 and B were correspondingly increased to 1944.
  • A would be a large power of two such as 1024 (2 10 ), meaning that B would be 1296. If A is 1024, then division could be implemented as a binary
  • a plurality of integer accumulators 220 may be
  • one accumulator 220 can be employed to track the
  • the output sample value would still be a function of at least a
  • the sample rate converter 200 includes a
  • controller 210 an integer accumulator 220, a multiplexer 230, adders 240, 250, a
  • the controller 210 controls the overall function of the converter 200.
  • the accumulator 220 tracks the relative position in time of input and output samples
  • the multiplexer 230 is connected to sources 180, 190 for
  • the input samples are sequentially fed to the register 290.
  • bit shifter 300 performs the appropriate bit shift to reflect division by A and outputs
  • controller 210 may be distributed within the functions of the controller 210 .
  • subtractor 260 may be any suitable subtractor 260, multipliers 270, 280, and input sample register 290.
  • the Figure 7 shows a simplified flowchart of the preferred operation of the
  • controller 210 of Figure 6 for the method described in Figure 4.
  • controller 210 instructs the accumulator 220 to clear and the input sample
  • the controller 210 causes the input sample register 290 to load the next input sample (box 360).
  • the converter 200 of Figure 6 is a simple hardware implementation of the
  • the converter 200 is capable of converting the sample rate of an
  • programmable constants the same sample rate converter 200, may be

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Complex Calculations (AREA)
  • Analogue/Digital Conversion (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Television Systems (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Other Investigation Or Analysis Of Materials By Electrical Means (AREA)

Abstract

A sample rate converter (200) is described for converting an input data stream including a plurality of input samples (X) at one sample rate to an output data stream including a plurality of output samples (Y) at another sample rate. The converter uses an interpolation approach that utilizes an integer accumulator (220) to track the timing relation between input samples and output samples. Based on the value of the accumulator, the method determines if the correct input samples are being used to calculate the current output sample. If so, the output sample is calculated as a function of the input samples and the accumulator value. The converter provides the robustness of a table based conversion approach without the need to precalculate and store a table, simplifies the calculations involved, and is less sensitive to numeric round off errors.

Description

SAMPLE RATE CONVERTER
FIELD OF THE INVENTION
This invention relates to the field sample rate converting of digital signals.
More particularly, the present invention relates to a sample rate conversion method
that employs an integer accumulator to calculate the timing relation of input and
output samples.
BACKGROUND OF THE INVENTION
In many electronic applications, signals are represented and processed
digitally. Digital words, or samples, represent the value of the data at a regular time
interval. This regular interval is often referred to as the sample rate, and is typically
expressed in units of kilohertz (kHz) representing the reciprocal of the sample
interval time period.
There are situations when the available sample rate of the data is different
from the desired sample rate. Depending on the characteristics of the sample data
and how much the available and desired rates differ, several approaches may be
used to convert the signal at one sample rate to a signal at another sample rate
without intentionally altering the meaning of the signal.
A first common technique for sample rate reduction is called decimation. It is
the method of choice when the available sample rate is an integer multiple of the
desired sample rate. The decimator reduces the input sample rate by an integer
number d to create an output sample rate. If the input signal contains high
frequency components, they must be first removed by a low pass filter to avoid aliasing effects. The rate reduction is performed by simply discarding d-1 input
samples for every .th output samples.
The main drawback of decimation is that the rate reduction is limited to an
integer number. In addition, an anti-aliasing filter, if necessary, may be very
computationally intensive.
A second common technique for sample rate conversion is known as
interpolation. Interpolation is the method frequently used for increasing the sample
rate by an integer multiple. To increase the sample rate by /, the basic interpolator
inserts 1-1 samples with a value of zero between every input sample. The resulting
samples are then filtered through an anti-aliasing low pass filter at the higher rate.
The interpolation method has some of the same basic drawbacks as
decimation. The rate increase is limited to an integer number and the low pass
filtering, which is necessary for interpolation, is costly.
By themselves, interpolation and decimation can only achieve changes in
sample rate of an integer number. In many cases, this does not give the necessary
flexibility. By combining interpolation and decimation, perhaps in several stages, it
becomes possible to fine tune the sample rate conversion. For example, if the input
sample rate is 194.4 kHz and the desired sample rate is 153.6 kHz, the rates do not
differ by an integer factor. Instead, the desired rate is related to the available rate
by the ratio 64/81 . To achieve the desired sample rate, the data may first be
interpolated by a factor of 64 and then decimated by a factor of 81 ; however, large
interpolation and decimation factors put very tough constraints on the required low pass filters. To reduce the filter requirements, the interpolation and decimation may
be performed in several stages, for example: interpolation by 8, followed by
decimation by 9, followed by interpolation by 8, followed by decimation by 9, resulting in a total of a 64/81 conversion. Using a combination of interpolation and
decimation enables a wider range of rate conversions that is not limited to integer
numbers. However, the big drawback of such an approach is the cost of filtering.
Another technique for sample rate conversion method that is useful when
input and output rates are close is known as linear interpolation. This method uses
a first order linear interpolation approach to estimate each output sample as a
function of two input samples and the relative position in time of the input and
output samples. Referring to Fig. 1 , the value of the m:th output sample would be
calculated according to the following formula:
ym = Xn * k + xn+1* (1-k)
where k = ((n+1) * TX - m* Ty)/Tx
In these formulas, xn is the n:th input sample, ym is if the m:th output sample,
Tx is the input sample period, and Ty is the output sample period. Given Tx is the
input sample period, the time of the n:th input sample is: txn = n * Tx. Similarly, the
time of the m:th output sample is: tym = m * Ty. To calculate output sample number
, chose n so that: n * TX < m * Ty < (n+1) * Tx.
One drawback of the first order interpolation method is that it may be difficult
to tell which particular input samples to use for calculation of an output sample. Tx
and Ty are seldom integers and round off errors may cause the wrong samples to be chosen. The calculation of k, which involves the subtraction of two numbers that
grow very large when m and n grow, also gets susceptible to errors due to limited
numeric precision.
These drawbacks can be mitigated by using a table with / -values.
Continuing with the example of 194.4 kHz input and 153.6 kHz output rate, the
samples relative positions in time repeat over a period of 81 input samples. Thus, it
is possible to pre-calculate and store the k- values in a table. Using a table would
eliminate the need to calculate k for every sample at the expense of storing pre-
calculated values. The drawback with using a pre-calculated table is that the
values for the tables must be pre-calculated and stored, which requires additional
hardware resources. This is particularly problematic when the same converter is to
be used with various input sample rate and output sample rate combinations.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for sample rate conversion
that overcomes some of the drawbacks of the prior art. The method of the present
invention is an interpolation method that provides the robustness of a table based
approach without the need to pre-caiculate and store a table. The method also
simplifies the calculations involved and is less sensitive to numeric round off errors.
The method utilizes a integer accumulator to generate an output data stream
including a plurality of output samples at one sample rate based on an input data
stream including a plurality of input samples at another sample rate. More
particularly, the method uses the integer accumulator to track the timing relation between input samples and output samples. Based on the value of the
accumulator, the method determines if the correct input samples are being used to
calculate the current output sample. If so, the output sample is calculated as a
function of the input samples and the accumulator value. By employing simple
integer arithmetics to maintain the accumulator value, the present inventive method
avoids unnecessarily large computations otherwise required to confirm that the
proper input samples are being used while maintaining the flexibility and
compactness of a non-table based approach.
The apparatus of the present invention includes an input sample register, an
integer accumulator, and preferably a bit shift register, all configured so as to
practice the present inventive sample rate conversion method.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a diagram depicting linear interpolation.
Figure 2 is a logical flowchart of the present sample rate conversion method.
Figure 3 is a diagram depicting the timing relation between input samples
(...xn.3, xn.2l x^, xn, xn+1, ...) and output samples (...ym.2, y^, ym, ym+1, ...).
Figure 4 is a logical flowchart of a simplified sample rate conversion method
applicable when A is known to be smaller than B.
Figure 5 is a logical flowchart of a simplified sample rate conversion method
applicable when A is known to be larger than B. Figure 6 is block diagram of a preferred embodiment of the apparatus for a
sample rate converter.
Figure 7 is a logical flowchart of a preferred embodiment of the controller for
the apparatus of Figure 6 using the method of Figure 4.
DETAILED DESCRIPTION OF THE INVENTION
The present invention is described more fully hereinafter by referring to the
drawings, in which a preferred embodiment is depicted. However, the present
invention can take on many different embodiments and is not intended to be limited
to the embodiments described herein.
The present inventive method is a variation of interpolation that uses an
integer accumulator 220 to facilitate calculation of the relative position in time of
input and output samples. For linear interpolation, the method employs two positive
integer constants, A and B, to calculate the timing relation of two input samples and
one output sample. If the sample period of the input signal is Tx and the sample
period of the output signal is Ty, then A and B are chosen such that the ratio of A
and B satisfies the following equation:
A / B = Tx / Ty
The actual value, or size, of A and B depends on the desired level of precision and
other considerations. In effect, the input sample period Tx is quantized into A steps.
By keeping the steps small (keeping A large), the added quantization noise can be
kept small. However, using a large number of bits to represent A may waste hardware resources. For example, assume that the input signal is available at a
194.4 kHz sample rate and the desired output sample rate is 153.6 kHz, then
A / B = Tx / Ty = ((1/194,400) /(1/153.600)) = 153,600 / 194,400 = 64 / 81
Thus, the input sample period could be quantized into 64 steps (A = 64), or any
multiple of 64 steps and still maintain the proper ratio while allowing both A and B to
be integers. Thus, A could be 1024 if B is 1296. However, if A is 64 then only 6
bits are required to represent the value (26 = 64), but if A is 1024, 10 bits are
required (210 = 1024). Note that one additional bit may be required to represent
sign for both.
The values of A and B are employed to iteratively calculate the value of a
variable "ace" which tracks the relative positions in time for a pair of input samples
and a given output sample. In simple terms, ace serves two functions. First, ace is
used to determine if the proper pair of input samples is being used to calculate the
current output sample. Second, ace is used to assign the proper weighting to each
member of the input sample pair so as to properly estimate the output sample
value. The details of how ace performs these functions will become apparent
through the following description.
Figure 2 shows a logical flow chart for the present invention. At the start of
the process, the integer accumulator 220 is set to zero and the variables m and n
are also set to zero (box 10). Variable m is an integer counter representing the
sequence number of the current output sample. Variable n is an integer counter
representing the sequence number of the current input sample. As will become apparent from the following description, the only purpose of m and n in the flow
diagram is to aid the reader in understanding the algorithm by clarifying how the
input and output samples are related. Neither m nor n need be stored or calculated
to practice the present inventive method.
The accumulator 220 contains an integer value representing the variable
"ace." The main processing loop begins by adding A to the integer value in the
accumulator 220 (see box 20). Ace is then checked to see if it is less than zero
(box 30). If so, then n is incremented by one (box 40), the next input sample is
selected to assume the role of the current input sample, and the process returns to
box 20. If ace is not less than zero, then the output sample is calculated (box 50).
In simple terms, the ace value check of box 30 represents a determination of
whether the particular output sample being calculated falls within the current input
sample period, i.e., between the two currently selected input samples (n and n+1)
or exactly at input sample xn+1.
For purposes of the invention, the current input sample period is defined as
the time period from the current input sample to the next subsequent input sample.
Thus, if the input sample rate is 1 Hz, and the current input sample is number four
(in the sequence zero, one, two, three, four, ... n) then the current input sample
period is from 4 seconds to 5 seconds.
Calculating the output sample (box 50) is accomplished via the formula:
ym = (ace * xn + (A - ace) * xn+1) /A This formula is a modified linear interpolation formula. In this formula, xn is the
value of the last input sample which occurs before the output sample and xn+1 is the
value of the, first input sample after the output sample. In the situations where an
output sample falls directly on top of an input sample, then ace will equal the integer
zero and formula will collapse to ym = (A * xn+1) / A = xn+1. Thus, the value of the
properly corresponding input sample, xn+1, will be used for the output sample (ym).
Note, however, that for the special case of the very first instance of direct overlap,
at the first input sample (x0) and first output sample (y0), ace wiii equal A, therefore
the formula for this one instance will collapse to y0 = (A * j /A = x0.
After the output sample is calculated (box 50), the value of ace is
decremented by B (box 60). In box 70, this new value of ace is checked to see if it
is greater than or equal to zero. If so, m is incremented by one and the process
returns to box 50. If not, then the both m and n are incremented by one (box 90).
In simple terms, the ace value check of box 70 represents a determination of
whether the next output sample occurs within the same pair of input samples.
The process continues looping through the main processing loop (box 20-
box 100) until there are no more samples (box 100), at which point it stops (box
110). In this manner the input sample rate of period Tx is converted to an output
sample rate of period Ty.
As an example of the method in action, see Figure 3. Assume that the input
sample rate is faster than the output sample rate, meaning that A is smaller than B.
For sake of discussion assume that A is 10 and B is 14, corresponding to an input sample rate of 1.4 kHz and an output sample rate of 1.0 kHz. Further, assume that
the conversion process is proceeding according to the present invention and is now
processing input sample xn.3 and output sample ym.2. At this point, entering box 20,
ace equals -4. At box 20, ace is incremented by A such that ace now equals 6 (-4
+10). Because 6 is larger than 0 (box 30), output sample ym.2 is calculated (box 50)
based on xn.3 and xn.2. Now, ace is decremented by 14 (box 60) so as to equal -8
(+6 -14). Because ace is not greater than 0, the main process loop begins again.
During this second pass through the main process loop, the value for ym.., is
calculated using xn.2 and xn_ and ace is adjusted to be -12 (-8 + 10 -14). At the third
pass through the main process loop, ace is incremented by A so as to equal -2 (-12
+ 10). Now, because ace is still less than 0, the current input sample (x^ at this
point) is discarded, the next input sample xn assumes the position of current input
sample, and ace is increased to 8 (-2 +10). Output sample ym is then calculated
using xn and xn+1. At the conclusion of the third pass through the main process loop
(box 100), ace equals -6 (8 -14). As shown in Figure 3, the reason input samples xn
and xn+1 were used to calculate output sample ym rather than input samples x^ and
xn is that ym fell between xn and xn+1.
As can be seen from this explanation, the variable ace is used to dynamically
track the timing relation between input samples and output samples. In this
example, where A is less than B, the input sample sequence is advanced by an
"extra" one or more position when ace is less than zero at box 30. In other
situations, when B is less than A, two or more output samples may be calculated
using the same input sample pair when ace is greater than or equal to zero in box 70. Thus, it can be seen that variable ace is used by the process to verify that the
correct input sample pair is being used to calculate each given output sample.
The algorithm of Figure 2 can be simplified slightly if the constant A is known
to be greater than the constant B, or vice versa. Using the same reference
numbers, Figure 4 shows a simplified logical flow chart for when A is known to be
smaller than B. Figure 5 shows a simplified logical flow chart for when A is known
to be larger than B. The flow charts of Figure 4 and Figure 5 show that a
comparison and loop back step can be eliminated when the relationship between A
and B is known, thereby simplifying the process.
For the above processes, the calculation of the output sample (ym) calls for
division by the constant A. Because division is sometimes expensive to implement
in hardware, it is possible to pre-calculate the value of 1/A instead, and use
multiplication. Alternatively, and more preferably, a value for A can be selected that
enables easy division. For example, if A is a power of two, the division can be
implemented as a simple binary bit shift.
For purposes of an example, assume that the input sample are available at
194.4 kHz and the desired sample rate is 153.6 kHz. This means that
A / B = Tx / Ty = 153,600 / 194,400 = 64 / 81
Thus, A could equal 64 and B could equal 81. If so, then the input sample period Tx
would be divided into 64 steps. Greater precision could be obtained if, for example,
A were increased to 1536 and B were correspondingly increased to 1944.
Preferably, however, A would be a large power of two such as 1024 (210), meaning that B would be 1296. If A is 1024, then division could be implemented as a binary
right shift of ten (10).
The discussion above assumes utilization of a linear interpolation approach.
However, the present inventive method is can also be utilized for other interpolation
approaches, such as second order or cubic or other methods known in the art.
Some of these other interpolation approaches require the use of more than two
input samples to calculate a given output sample. If only two input samples are
required, then only one integer accumulator 220 need be employed. If more than
two input samples are required, a plurality of integer accumulators 220 may be
used to track the various timing relations between input samples and output
samples. Alternatively, one accumulator 220 can be employed to track the
relationship between all the input samples required and the output sample to be
calculated; this is because once a timing relationship to one input sample is known,
the timing relationship to the other input samples will simply be an integer increment
of A farther away. If a different interpolation approach (other than linear) is used,
obviously a different formula would also be employed to calculate each given output
sample. However, the output sample value would still be a function of at least a
plurality of input samples and one or more accumulator values.
A block diagram of a possible hardware implementation of the sample rate
converter 200 is shown in Figure 6. The sample rate converter 200 includes a
controller 210, an integer accumulator 220, a multiplexer 230, adders 240, 250, a
subtractor 260, multipliers 270, 280, an input sample register 290, and a bit shifter
300. The controller 210 controls the overall function of the converter 200. The accumulator 220 tracks the relative position in time of input and output samples
using integer arithmetics. The multiplexer 230 is connected to sources 180, 190 for
values of A and B. The input samples are sequentially fed to the register 290. The
bit shifter 300 performs the appropriate bit shift to reflect division by A and outputs
the output sample value for each output sample.
Alternatively, the functions of the controller 210 may be distributed within the
converter 200 rather than collected in a single device as shown in Figure 6. Also,
two or more of the components of the converter 200, such as the adders 240, 250,
subtractor 260, multipliers 270, 280, and input sample register 290 may be
combined into an integrated arithmetic logic unit, but this may be more costly.
The Figure 7 shows a simplified flowchart of the preferred operation of the
controller 210 of Figure 6 for the method described in Figure 4. Upon initialization,
the controller 210 instructs the accumulator 220 to clear and the input sample
register 290 to load the first input sample (box 310). Note that this action
corresponds to box 10 of Figure 4. Then the controller 210 verifies that the next
input sample is available (box 320). If not, the controller 210 loops until the next
input sample is available. If so, then the controller 210 instructs the multiplexer 230
to load A and causes the accumulator 220 to increment by A (box 330). Note that
this action corresponds to box 20 of Figure 4. The controller 210 then checks the
sign bit of the accumulator 220 (box 340). Note that this action corresponds to box
30 of Figure 4. If the sign bit is positive, the controller 210 causes the output sample
(ym) to be calculated, the multiplexer to switch to -B, and the accumulator 220 to
add -B to the existing accumulator value (box 350). These actions correspond to boxes 50, 60, and 90 of Figure 4. Either after box 350 or if the sign bit is negative
at box 340, the controller 210 causes the input sample register 290 to load the next input sample (box 360).
The converter 200 of Figure 6 is a simple hardware implementation of the
linear interpolation sample rate conversion method described above for when A is a
power of two. The converter 200 is capable of converting the sample rate of an
input sample stream of x.,, x2, ... xn to an output sample stream of y,, y2, ... ym
having a different output sample rate using integer arithmetics. By making A and B
programmable constants, the same sample rate converter 200, may be
programmed to operate at several different input to output sample ratios.

Claims

CLAIMSWhat I Claim Is:
1. A sample rate conversion method for converting an input data stream
at a first sample rate to an output data stream at a second sample rate
comprising:
a) receiving an input data stream which includes a plurality of input
samples at a first sample rate; and
b) generating an output data stream which includes a plurality of
output samples at a second sample rate by interpolation of said input samples;
said generation step including:
i) selecting one or more input samples in said input data
stream;
ii) maintaining at least one accumulator total which is
indicative of the timing relationship between a selected input sample and the
output sample to be generated, wherein the value of the accumulator is always an
integer; and
iii) for each output sample, calculating said output sample
as a function of said accumulator total.
2. The method of claim 1 further comprising the step of comparing the
accumulator total to a known reference value so as to determine if the currently
selected input sample has the correct timing relationship to the output sample to
be generated before said calculation step.
3. The method of claim 1 further comprising the step of maintaining a
plurality of accumulator totals wherein each accumulator total is indicative of the
timing relationship between a different input sample in said input data stream and
the output sample to be generated and wherein the value of each accumulator is
always an integer.
4. The method of claim 1 wherein said calculation is a further function of
said currently selected input sample.
5. The method of claim 2 wherein said known reference value is zero.
6. A sample rate conversion method for converting an input data stream
at a first sample rate to an output data stream at a second sample rate
comprising:
a) receiving an input data stream which includes a plurality of input
samples at a first sample rate; and
b) generating an output data stream which includes a plurality of
output samples at a second sample rate by linear interpolation of said input
samples; said generation step including:
i) maintaining at least one accumulator total which is
indicative of the timing relationship between a current input sample in said input
data stream and the output sample to be generated, wherein the value of the
accumulator is always an integer; and
ii) for each output sample, calculating said output sample
as a function of the accumulator total.
7. The method of claim 6 further comprising the step of comparing the
accumulator total to a known reference value so as to determine whether the
output sample to be generated falls within a current input sample period before said calculation step.
8. The method of claim 6 wherein said calculation is a further function of
the current input sample and the next input sample.
9. The method of claim 8 further comprising the steps of:
a) establishing integer values A and B such that the ratio A / B is
equal to Tx / Ty where Tx is the input sample period and Ty is the output sample
period; and
b) calculating the output sample value Ym of the m th output sample
according to the formula
Ym = (L * Xn + (A - L) * Xn+1) / A
where L is the current value of said accumulator, Xn is the value of the current
input sample, and Xn+1 is the value of the next input sample after Xn.
10. The method of claim 9 further comprising the step of decrementing the
value of said accumulator by B after calculating an output sample value.
11. The method of claim 9 further comprising the step of incrementing the
value of said accumulator by A before calculating an output sample value.
12. The method of claim 9 wherein A is a power of two.
13. The method of claim 7 wherein said known reference value is zero.
14. A sample rate conversion method for converting an input data stream
at a first sample rate to an output data stream at a second sample rate
comprising:
a) receiving an input data stream which includes a plurality of input samples at a first sample rate;
b) generating an output data stream which includes a plurality of
output samples at a second sample rate by linear interpolation of said input
samples; said generation step including:
i) establishing integer values A and B such that the ratio
A / B is equal to Tx / Ty where Tx is the input sample period and Ty is the output
sample period;
ii) maintaining an accumulator total which is indicative of
the timing relationship between a current input sample in said input data stream
and the output sample to be generated, wherein the value of the accumulator is
always an integer; and
iii) for each output sample, comparing the accumulator
total to a known reference value so as to determine whether the output sample to
be generated falls within a current input sample period; if so, calculating said
output sample as a function of the accumulator total, the current input sample,
and the next input sample according to the formula
Ym = (L * Xn + (A - L) * Xn+1) / A where Ym is the value of the m:th output sample, L is the current value of said
accumulator, Xn is the value of the current input sample, and Xn+1 is the value of
the next input sample after Xn; and
iv) setting L to zero initially and then incrementing L by A
before calculating the first output sample value and decrementing L by B after
calculating each output sample value.
15. The method of claim 14 wherein A is a power of two.
16. The method of claim 14 wherein said known reference value is zero.
17. A sample rate converting device for converting an input data stream
which includes a plurality of input samples at a first sample rate to an output data
stream which includes a plurality of output samples at a second sample rate
comprising:
a) an input sample register;
b) at least one integer accumulator for calculating the timing
relation between input samples and output samples using integer arithmetics;
wherein the value of each of said output samples is calculated as a function of
said accumulator total and a plurality of said input samples.
18. The apparatus of claim 17 wherein said calculation is according to the
formula:
Ym = (L * Xn + (A - L) * Xn+1) / A where Ym is the value of the m:th output sample, L is the current value of said
accumulator, Xn is the value of the current input sample, and Xn+1 is the value of
the next input sample after Xn; and A is an integer value such that A and integer
value B have a ratio A to B of Tx to Ty where Tx is the input sample period and Ty
is the output sample period.
19. The device of claim 17 further comprising a bit shifter for the division
portion of said calculation.
PCT/US1998/000832 1997-02-26 1998-01-16 Sample rate converter WO1998038766A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP98903524A EP0963633B1 (en) 1997-02-26 1998-01-16 Sample rate converter
EEP199900368A EE9900368A (en) 1997-02-26 1998-01-16 Sampling frequency converter
JP53763698A JP4376973B2 (en) 1997-02-26 1998-01-16 Sample rate converter
KR10-1999-7007628A KR100386549B1 (en) 1997-02-26 1998-01-16 Sample rate converter
AU60274/98A AU732601B2 (en) 1997-02-26 1998-01-16 Sample rate converter
BRPI9807771-6A BR9807771B1 (en) 1997-02-26 1998-01-16 sampling rate conversion process and device.
HK00106064A HK1026989A1 (en) 1997-02-26 2000-09-25 Sample rate converter

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/806,853 1997-02-26
US08/806,853 US5818888A (en) 1997-02-26 1997-02-26 Sample rate converter

Publications (1)

Publication Number Publication Date
WO1998038766A1 true WO1998038766A1 (en) 1998-09-03

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EP (1) EP0963633B1 (en)
JP (1) JP4376973B2 (en)
KR (1) KR100386549B1 (en)
CN (1) CN1126320C (en)
AU (1) AU732601B2 (en)
BR (1) BR9807771B1 (en)
EE (1) EE9900368A (en)
ES (1) ES2264193T3 (en)
HK (1) HK1026989A1 (en)
MY (1) MY123934A (en)
WO (1) WO1998038766A1 (en)

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CN1249093A (en) 2000-03-29
KR100386549B1 (en) 2003-06-02
HK1026989A1 (en) 2000-12-29
US5818888A (en) 1998-10-06
BR9807771A (en) 2000-02-22
EP0963633A1 (en) 1999-12-15
EP0963633A4 (en) 2000-10-04
CN1126320C (en) 2003-10-29
ES2264193T3 (en) 2006-12-16
JP2001513295A (en) 2001-08-28
EP0963633B1 (en) 2006-07-05
KR20000075568A (en) 2000-12-15
JP4376973B2 (en) 2009-12-02
BR9807771B1 (en) 2010-05-18
AU732601B2 (en) 2001-04-26
AU6027498A (en) 1998-09-18
MY123934A (en) 2006-06-30
EE9900368A (en) 2000-04-17

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