WO1998018165A1

WO1998018165A1 - Memory storage cell and method of manufacturing a non-volatile storage cell

Info

Publication number: WO1998018165A1
Application number: PCT/DE1997/002127
Authority: WO
Inventors: Martin Kerber
Original assignee: Siemens Aktiengesellschaft
Priority date: 1996-10-18
Filing date: 1997-09-19
Publication date: 1998-04-30
Also published as: DE19643185A1; DE19643185C2

Abstract

A single method is specified for the optional manufacture of a dual-gate cell, a split gate-cell, or a stacked-gate cell, in which a microtrench (8) is created in a first polysilicon layer (4). The microtrench (8) and an interpolydielectric (10) ensure electrical insulation of areas of the first polysilicon layer (4) from a second polysilicon layer (11). By adjusting a mask (12), any one of the three storage cells can be selected for manufacture. In addition, a dual-gate cell requiring exceptionally little space is created.

Description

description

Memory cell and method for producing a non-volatile memory cell

The invention relates to a dual-gate memory cell with a selection transistor and a memory transistor. Furthermore, the invention relates to a method for producing a non-volatile memory cell with a floating gate, in particular a dual-gate memory cell.

Non-volatile memory cells are characterized in that the information content of the memory cells is retained for a long time even after the supply voltage has been switched off. In the case of floating gate memory cells, the charge is stored in a polysilicon structure that is completely insulated, the so-called floating gate. When programming and deleting the floating gate, relatively high voltages are applied to an overlying control gate, but also to an associated drain area. The different requirements for electrically programmable non-volatile flash memories with regard to maximum programming cycles, neighboring signal-to-noise ratio etc. mean that different embodiments of cells have to be provided simultaneously on one chip.

Known embodiments are the stacked gate cell, the split gate cell and the dual gate cell. The simplest cell is the stacked gate cell, in which the control gate only controls the transistor channel via the floating gate. The storage function is achieved by shifting the threshold voltage due to the non-volatile charge in the floating gate. In order to prevent a memory cell with a negative threshold voltage, such as can occur, for example, when "erasing" is too strong, a transistor is connected in series. This can be controlled by the control gate. Such an embodiment is achieved with the split gate cell. Alternatively, one can be connected in series. teter transistor can also be designed as a separately executed selection transistor. Such cells are called dual-gate cells. This cell is also called a FLOTOX memory cell.

In known production methods, a thin polysilicon layer is applied to a gate oxide in order to produce a floating gate. An interpolydielectric is applied and structured on it. After oxidation, another polysilicon layer is applied and structured to form a control gate. A different method is used for producing a dual-gate cell than for producing a stacked-gate cell. In particular, a somewhat larger area must be available in the production of a dual-gate cell, since the selection transistor is formed separately from the control gate and at least the distance that can be resolved by phototechnology lies between them.

The invention is based on the object of creating a dual-gate cell of the type mentioned at the outset which requires a particularly small area. Furthermore, a method for producing such a dual-gate cell is to be created, with which other embodiments of non-volatile memory cells with a floating gate can also be produced.

The object is achieved in that the memory transistor and the selection transistor are arranged closely adjacent to one another, and the selection transistor and the memory transistor are separated by a micro-trench.

The micro-trench, which is also referred to as a micro-trench, is advantageously arranged between a floating gate of the memory transistor and a selection gate of the selection transistor, a control gate of the selection transistor covering the floating gate and the selection gate Gate at least partially overlapped. This dual gate cell is extremely small and has the same functionality as an EEPROM memory cell.

In the method according to the invention for producing a non-volatile memory cell with a floating gate, a leakage oxide for implanting a channel doping is generated, the leakage oxide is removed in a tunnel area, a tunnel oxide is generated, a first polysilicon layer is applied, in the first polysilicon layer using a micro-trench technique a narrow trench is created in the tunnel area, an interpolydielectric which covers the trench, applied and then optionally structured, a second polysilicon layer is applied, and structuring to produce a split-gate cell, a dual-gate cell or a stacked - Gate cell performed.

According to the basic idea of the invention, the final structuring is combined with the underlying interpolydielectric layer and the tunnel area using a uniform method for all three cell types such that either a stacked-gate cell, a split-gate cell or a dual-gate Cell is generated. A further advantage is that the electrical isolation between a selection transistor and the control gate is self-aligned during the manufacture of the dual-gate cell, as a result of which a smaller area is achieved. The process management differs from known methods by the steps described in the structuring of the flash cells. The preceding process steps for the production of deep wells and of field oxide and also the subsequent process steps for the production of drains of the transistors and a metallization for metallic contacting are known.

The first polysilicon layer is advantageously thicker than the second polysilicon layer. This measure is taken because in some areas the final structuring of the second polysilicon layer already takes place Part of the first polysilicon layer is removed. The thickness of the polysilicon layers must be selected so that in this etching step the first polysilicon is not removed as far as the gate oxide underneath, since otherwise the gate oxide would also be removed when the interpolydielectric is subsequently removed. The thicker first polysilicon layer also achieves a better coupling factor and a larger outer surface of the floating gate.

The micro-trench technology is advantageously implemented in such a way that an intermediate layer is first applied, a nitride spacer is produced on the intermediate layer and the intermediate layer outside the nitride spacer is oxidized. The nitride spacer is then removed and the oxidized intermediate layer is used as a mask for anisotropic etching. In this way, a trench can be created, which is also called a microtrench, the width of which is determined by the width of the spacer and is thus significantly smaller than a structural fineness that can be achieved by phototechnology. Furthermore, it is expedient to produce an arsenic implant for the electrical insulation of the floating gate after the creation of the micro trench by producing an implantation region. This implantation is self-adjusted by the trench structure, so that a further photo technique is not necessary.

The interpolydielectric is preferably only structured when a split gate cell is produced. In the production of the other embodiments of the memory cells, the structuring of the interpolydielectric can be dispensed with and all contacts to the first polysilicon can be realized with the final structuring. The interpolydielectric is also advantageously deposited conformally, since this results in improved reliability, in particular at the edges of the first polysilicon layer.

The final structuring advantageously consists of a three-stage, isotropic etching process in which the first Step the second polysilicon layer, in the second step the interpolydielectric and in the third step the first polysilicon layer is structured.

The invention is explained in more detail below on the basis of an exemplary embodiment shown in the drawing. In detail, the schematic representations show in:

Figures 1 to 5 different stages of the method for producing a non-volatile memory cell;

Figure 6 is a split gate cell with the associated

Switch symbol;

Figure 7 shows a dual gate cell with the associated

Symbol and

Figure 8 shows a stacked gate cell with the associated

Circuit symbol.

After the usual process control, in which deep wells and a field oxide are produced, a scatter oxide 1 for implanting the channel doping for NMOS and PMOS transistors is oxidized. With a gate oxide mask 2, also called split GOX mask, the scatter oxide 1 is removed in a tunnel area in which a thin oxide will later be required. The gate oxide mask 2 is produced using a first photo technique. Figure 1 shows this state of the process.

A tunnel oxide 3 is then oxidized, which at the same time also forms the gate oxide for the low-voltage transistors. In the areas of the high-voltage transistors, the existing leakage oxide 1 is oxidized to the desired thickness. In these areas, the oxide is composed of the scatter oxide 1 and the tunnel oxide 3. This process status is shown in FIG. 2. As shown in FIG. 3, a first polysilicon layer 4 is deposited thereon. This first layer of silicon must be sufficiently thick. A micro trench is produced in the first polysilicon layer 4 in the region of the thinner tunnel oxide 3. This is done by first applying an intermediate layer 5, on which a thin nitride spacer 6 is produced in a known manner by nitride deposition on a phototechnically generated structural edge. A second photo technique is used. After the narrow nitride spacer 6 has been produced, the intermediate layer 5 is oxidized, the nitride spacer 6 acting as an oxidation barrier. Next, the nitride spacer 6 and the underlying, non-oxidized intermediate layer 5 are removed, so that the remaining intermediate layer 5 serves as an etching mask for anisotropic trench etching.

A micro-trench 8 produced in this way is shown in FIG. Arrows 7 show a self-adjusted arsenic connection implantation which is introduced into the trenches in order to increase a possibly critical contact resistance and to establish reliable insulation by means of an implantation region 9.

The result of the next steps is shown in FIG. 5. An interpolydielectric 10 is applied conformally to the first polysilicon layer 4, which conformally covers the micro trench 8, but does not necessarily fill it up. In the illustration in FIG. 5, however, the micro trench 8 is completely filled. With a third photo technique, the interpolydielectric 10 is removed wherever an electrical connection to the first polysilicon layer 4 is desired. The interpolydielectric 10 is generally structured such that it remains in the tunnel area in which only the thin tunnel oxide 3 is present and is removed outside this area. This is followed by the deposition of a second, somewhat thinner polysilicon layer 11, with which the micro-trenches 8 are completely filled at the latest. A mask 12 is applied for a fourth photo technique, with which the layer sequence of thin second polysilicon layer 12, interpolydielectric 10 and first polysilicon layer 4 is structured in a three-stage isotropic etching process. In areas where the interpolydielectric 10 was previously removed using the third photo technique, part of the thicker polysilicon layer 4 lying underneath is already etched during the first etching step. The thicknesses of the polysilicon layers 4 and 11 must therefore be selected such that the thicker polysilicon layer 4 is not removed as far as the underlying gate oxide 3 in this first etching step. After the polysilicon layer sequence has been structured, the second polysilicon layer 11 can be removed by means of a fifth photo technique and an isotropic etching step, wherever the first polysilicon layer 4 underneath is to be contacted, or where the capacitance between the polysilicon layers is to be as small as possible.

At this point, the manufacturing process for CMOS transistors and non-volatile memory cells is continued with the generation of the transistor drains and a metallization in a known manner.

By adjusting the mask 12 with respect to the tunnel area, the micro-trench 8 and the interpolydielectric 10, a split gate cell, a dual gate cell or a stacked gate cell is optionally produced.

FIG. 6 shows a split gate cell and an associated circuit symbol in the left area. This split gate cell is achieved by adjusting the mask 12 shown in FIG. A floating gate 13 is formed from a partial area of the first polysilicon layer 4. In order to produce the split gate cell, a prior structuring of the interpolydielectric 10 is necessary in order to establish the connection shown in the left area between the second poly to obtain silicon layer 11 and first polysilicon layer 4.

Alternatively, the dual gate cell shown in FIG. 7 can be generated with this method. A circuit symbol of this dual-gate cell is shown in the left-hand area of FIG. A selection transistor is arranged on the left and a memory transistor is arranged on the right.

The memory transistor is formed by the floating gate 13 and an overlying control gate, which is formed by the second polysilicon layer 11. A selection gate of the selection transistor is formed by a region of the first polysilicon layer 4 which is separated from the floating gate 13 by the micro trench 8.

FIG. 8 shows a stacked gate cell which can also be produced from the method shown in FIGS. 1 to 5. In the case of the dual-gate cell and the stacked-gate cell, structuring of the interpolydielectric is not absolutely necessary, so that the interpolydielectric is only structured together with the first polysilicon layer and the second polysilicon layer during the final structuring. In the staked gate cell, the micro trench is only required for the separation of the floating gates from memory cells adjacent in the direction of the control gates. The interpolydielectric 10 is used in all memory cells to isolate the floating gate 13 and control gate.

With the method described in FIGS. 1 to 5, all three memory cells shown in FIGS. 6 to 8 can be produced simultaneously. In addition, a dual-gate cell is produced which is particularly small and combines the selection transistor and the memory transistor in one structure.

Claims

claims

1. Dual-gate memory cell with a selection transistor and a memory transistor, so that the memory transistor and the selection transistor are arranged closely adjacent to one another and that the selection transistor and the memory transistor are separated by a micro-trench (8).

2. Dual-gate memory cell according to claim 1, characterized in that the micro-trench (8) is arranged between a floating gate (13) of the memory transistor and a selection gate of the selection transistor and that a control gate of the selection transistor is floating Gate (13) and the selection gate at least partially overlaps.

3. A method for producing a non-volatile memory cell, in particular a dual-gate cell according to one of claims 1 or 2, in which a scatter oxide (1) for implanting a channel doping is generated, the scatter oxide (1) is removed in a tunnel area If a tunnel oxide (3) is generated, a first polysilicon layer (4) is applied, in the first polysilicon layer (4) a micro-trench (8) is produced in the tunnel area using micro-trench technology, an interpolydielectric (10) which holds the micro-trench (8) is covered, applied and optionally structured, a second polysilicon layer (11) is applied, structuring for producing a split-gate cell (FIG. 6), a dual-gate cell (FIG. 7) or a stacked -Gate cell (Figure 8) is performed.

4. The method according to claim 3, so that the first polysilicon layer (4) is thicker than the second polysilicon layer (11).

5. The method according to any one of claims 3 or 4, d a d u r c h g e k e n n z e i c h n e t that for the micro trench technology first an intermediate layer

(5) is applied, a nitride spacer (6) is produced on the intermediate layer (5), the intermediate layer (5) is oxidized outside the nitride spacer, the nitride spacer (6) is removed and the oxidized intermediate layer (5) as a mask for anisotropic etching is used.

6. The method according to any one of claims 3 to 5, so that an arsenic implantation for electrical insulation is produced by creating an implantation region (9) after the generation of the micro trench (8).

7. The method according to any one of claims 3 to 6, that the interpolydielectric (10) is deposited conformally.

8. The method according to any one of claims 3 to 7, so that the interpolydielectric (10) is structured only when a split gate cell (FIG. 6) is produced.

9. The method according to any one of claims 3 to 8, characterized in that the final structuring consists of a three-stage isotropic etching process in which in the first step the second polysilicon layer (11), in the second step the in- terpolydielectric (10) and in the third step the first polysilicon layer (4) is structured.