WO1998000799A3 - Modular cell placement system with dispersion-driven levelizing system - Google Patents

Modular cell placement system with dispersion-driven levelizing system Download PDF

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Publication number
WO1998000799A3
WO1998000799A3 PCT/US1997/011099 US9711099W WO9800799A3 WO 1998000799 A3 WO1998000799 A3 WO 1998000799A3 US 9711099 W US9711099 W US 9711099W WO 9800799 A3 WO9800799 A3 WO 9800799A3
Authority
WO
WIPO (PCT)
Prior art keywords
regions
dispersion
nodes
cell placement
modular cell
Prior art date
Application number
PCT/US1997/011099
Other languages
French (fr)
Other versions
WO1998000799A2 (en
Inventor
Ranko Scepanovic
James S Koford
Alexander E Andreev
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/672,652 external-priority patent/US5870312A/en
Priority claimed from US08/672,334 external-priority patent/US5914888A/en
Priority claimed from US08/671,659 external-priority patent/US6085032A/en
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Publication of WO1998000799A2 publication Critical patent/WO1998000799A2/en
Publication of WO1998000799A3 publication Critical patent/WO1998000799A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Abstract

A system for optimizing the density of cells located on a surface of a semiconductor chip divided into a plurality of rectangular regions is provided herein. The corners of these regions define nodes. The system comprises computing an average local cell density for regions adjacent to each node and deforming these regions by relocating nodes to positions that minimize a cost function associated with the densities of the new deformed regions bordering the relocated nodes.
PCT/US1997/011099 1996-06-28 1997-06-26 Modular cell placement system with dispersion-driven levelizing system WO1998000799A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US08/672,652 US5870312A (en) 1996-06-28 1996-06-28 Advanced modular cell placement system with dispersion-driven levelizing system
US08/672,334 1996-06-28
US08/672,334 US5914888A (en) 1996-06-28 1996-06-28 Advanced modular cell placement system with coarse overflow remover
US08/671,659 US6085032A (en) 1996-06-28 1996-06-28 Advanced modular cell placement system with sinusoidal optimization
US08/671,659 1996-06-28
US08/672,652 1996-06-28

Publications (2)

Publication Number Publication Date
WO1998000799A2 WO1998000799A2 (en) 1998-01-08
WO1998000799A3 true WO1998000799A3 (en) 1998-02-05

Family

ID=27418235

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/011099 WO1998000799A2 (en) 1996-06-28 1997-06-26 Modular cell placement system with dispersion-driven levelizing system

Country Status (1)

Country Link
WO (1) WO1998000799A2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191542A (en) * 1989-06-23 1993-03-02 Kabushiki Kaisha Toshiba Automatic floorplan operation apparatus
US5495419A (en) * 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191542A (en) * 1989-06-23 1993-03-02 Kabushiki Kaisha Toshiba Automatic floorplan operation apparatus
US5495419A (en) * 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"TECHNIQUE TO ALLOCATE SPACE ON VLSI CHIPS FOR DESIGN CHANGES", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 34, no. 10A, 1 March 1992 (1992-03-01), pages 71 - 72, XP000302228 *

Also Published As

Publication number Publication date
WO1998000799A2 (en) 1998-01-08

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