WO1998000798A3 - Modular cell placement system with fast procedure for finding a levelizing cut point - Google Patents

Modular cell placement system with fast procedure for finding a levelizing cut point Download PDF

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Publication number
WO1998000798A3
WO1998000798A3 PCT/US1997/011098 US9711098W WO9800798A3 WO 1998000798 A3 WO1998000798 A3 WO 1998000798A3 US 9711098 W US9711098 W US 9711098W WO 9800798 A3 WO9800798 A3 WO 9800798A3
Authority
WO
WIPO (PCT)
Prior art keywords
region
cell
dividing
finding
minimum
Prior art date
Application number
PCT/US1997/011098
Other languages
French (fr)
Other versions
WO1998000798A2 (en
Inventor
Ranko Scepanovic
James S Koford
Alexander E Andreev
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/671,699 external-priority patent/US5870311A/en
Priority claimed from US08/671,651 external-priority patent/US6030110A/en
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Priority to DE69737771T priority Critical patent/DE69737771T2/en
Priority to EP97932299A priority patent/EP0978072B1/en
Publication of WO1998000798A2 publication Critical patent/WO1998000798A2/en
Publication of WO1998000798A3 publication Critical patent/WO1998000798A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A system for defining a cut point dividing a plurality of cells located on the surface of a semiconductor chip is disclosed herein. The surface has at least one region located thereon. The system comprises dividing each region into subregions, computing the capacity of each subregion, finding the maximum and minimum cell locations within each region, dividing the range spanning the maximum and minimum cell locations into a plurality of subintervals, calculating an index for each cell based on the subinterval containing the cell, accumulating cell heights for each subinterval, determining the values of cell heights for each region as the sum of cell heights for all prior regions, locating the minimum index such that the cell heights for each region are most closely proportional to the capacity of the associated subregion, and finding the cut line based on said minimum index and the maximum and minimum cell locations. The system further comprises a calculator which determines an offset of the cut line from the dividing line; a shifter which moves the location of said groups of cells by the offset such that the cut line coincides with the dividing line; and an overflow evaluator and compensator which shifts any cells outside said region to an edge of said region.
PCT/US1997/011098 1996-06-28 1997-06-26 Modular cell placement system with fast procedure for finding a levelizing cut point WO1998000798A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE69737771T DE69737771T2 (en) 1996-06-28 1997-06-26 MODULAR CELL PLACEMENT SYSTEM WITH FAST METHOD FOR FINDING A LEVELING INTERFACE
EP97932299A EP0978072B1 (en) 1996-06-28 1997-06-26 Modular cell placement system with fast procedure for finding a levelizing cut point

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/671,651 1996-06-28
US08/671,699 US5870311A (en) 1996-06-28 1996-06-28 Advanced modular cell placement system with fast procedure for finding a levelizing cut point
US08/671,651 US6030110A (en) 1996-06-28 1996-06-28 Advanced modular cell placement system with median control and increase in resolution
US08/671,699 1996-06-28

Publications (2)

Publication Number Publication Date
WO1998000798A2 WO1998000798A2 (en) 1998-01-08
WO1998000798A3 true WO1998000798A3 (en) 1998-02-12

Family

ID=27100589

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/011098 WO1998000798A2 (en) 1996-06-28 1997-06-26 Modular cell placement system with fast procedure for finding a levelizing cut point

Country Status (3)

Country Link
EP (1) EP0978072B1 (en)
DE (1) DE69737771T2 (en)
WO (1) WO1998000798A2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5513124A (en) 1991-10-30 1996-04-30 Xilinx, Inc. Logic placement using positionally asymmetrical partitioning method
JP2922404B2 (en) 1993-11-15 1999-07-26 富士通株式会社 Method for determining layout of integrated circuit
US5557533A (en) 1994-04-19 1996-09-17 Lsi Logic Corporation Cell placement alteration apparatus for integrated circuit chip physical design automation system
US5699265A (en) 1995-09-08 1997-12-16 Lsi Logic Corporation Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HAGEN L ET AL: "NEW SPECTRAL METHODS FOR RATIO CUT PARTITIONING AND CLUSTERING", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 11, no. 9, 1 September 1992 (1992-09-01), pages 1074 - 1085, XP000332292 *
KAZUHIRO TAKAHASHI ET AL: "MIN-CUT PLACEMENT WITH GLOBAL OBJECTIVE FUNCTIONS FOR LARGE SCALE SEA-OF-GATES ARRAYS", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 14, no. 4, 1 April 1995 (1995-04-01), pages 434 - 446, XP000536010 *

Also Published As

Publication number Publication date
WO1998000798A2 (en) 1998-01-08
EP0978072A2 (en) 2000-02-09
DE69737771D1 (en) 2007-07-12
EP0978072B1 (en) 2007-05-30
DE69737771T2 (en) 2008-01-31

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