WO1997041594A1 - Multilayer solder/barrier attach for semiconductor chip - Google Patents

Multilayer solder/barrier attach for semiconductor chip Download PDF

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Publication number
WO1997041594A1
WO1997041594A1 PCT/US1997/007155 US9707155W WO9741594A1 WO 1997041594 A1 WO1997041594 A1 WO 1997041594A1 US 9707155 W US9707155 W US 9707155W WO 9741594 A1 WO9741594 A1 WO 9741594A1
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WO
WIPO (PCT)
Prior art keywords
solder
attach
layer
electroplating
layers
Prior art date
Application number
PCT/US1997/007155
Other languages
French (fr)
Inventor
Carl Shine
Original Assignee
Carl Shine
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US845,582 priority Critical
Priority to US1643096P priority
Priority to US60/016,430 priority
Priority to US84558297A priority
Application filed by Carl Shine filed Critical Carl Shine
Publication of WO1997041594A1 publication Critical patent/WO1997041594A1/en

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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0215Metallic fillers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/1025Metallic discs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/0415Small preforms other than balls, e.g. discs, cylinders or pillars
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3473Plating of solder
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/60Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control
    • Y02P70/613Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control involving the assembly of several electronic elements

Abstract

A multilayer attach (21) including alternating layer of solder (204, 208, 212) and barrier metals (206, 210) is used to replace the conventional solder bumps or balls in flip-chip bonding. The thin solder layers undergo grain boundary sliding deformation rather than matrix deformation when the attach is subjected to lateral shear forces as a result of the differential thermal expansion of the chip (20) and the substrate (22). Grain boundary sliding deformation is relatively damage-free as compared to matrix deformation, which generates voids, cracks and fractures in the attach, ultimately leading to a defective electrical or thermal connection. In one embodiment, the attach includes three solder layers each of which is no more than 50 νm thick.

Description

MULTILAYER SOLDER/BARRIER ATTACH FOR SEMICONDUCTOR CHIP

This application claims priority based on Provisional Application No 60/016,430 filed

April 29, 1996.

FIELD OF THE INVENTION

This invention relates to structures and methods of forming an electrical, thermal or mechanical attachment between bodies which have different thermal coefficients of expansion This invention relates particularly to structures and methods of forming an electrical or thermal attachment between a semiconductor chip or package and a printed circuit board or other substrate

BACKGROUND OF THE INVENTION

Semiconductor chips are commonly attached to printed circuit boards (PCBs) by arrays of solder bumps or balls For example, in "flip-chip" bonding an array of solder bumps is formed on the front side of the chip The chip is then inverted and the solder bumps are heated (reflowed) to form a connection with pads on the PCB This structure provides a direct electrical connection which reduces noise and parasitics and increases speed as compared with, for example, the use of bonding wires to connect the chip and the PCB In the fabrication of multichip modules flip-chip bonding allows a better use ofthe available real estate on the PCB and eliminates the need for a separate chip package In a similar manner, a ball grid array consisting of solder balls can be used to connect pads on an "interposer" placed between a semiconductor chip and a PCB with pads on the PCB

The solder bumps employed in flip-chip bonding and ball grid arrays are typically 125- 200 mm in diameter and are frequently formed by electroplating or evaporation

A problem occurs when the chip and PCB (or interposer) are subjected to temperature variations Because these two bodies normally have different temperature coefficients of expansion, the solder bumps are subjected to shear stresses and exhibit defects after a number of thermal cycles A silicon chip has a thermal coefficient of expansion (α) of 2 6 x IO"6 in/in/°C while a PCB, for example, has an α of about 16 x IO'6 in/in/°C For example, in an array of bumps on a large (> 0.5") die, a C4 solder bump attach bonded to a copper substrate will last only about 100 thermal cycles (-60°C to 150°C). The problem of differential thermal expansion can be overcome to some extent by adding structural support for the solder bumps by filling the spaces between them with a plastic material (a process known as "underfilling"), but this solution is time-consuming and expensive. It also renders the structure non-repairable.

Ordinary solder bump structures last less than 100 thermal cycles (from -40°C to 125°C). With underfilling this can be increased to about 2500 thermal cycles Using very large, 250 mm-diameter solder bumps on 500 mm centers increases the lifetime of the bumps to about 1000 thermal cycles. This solution, however, consumes an excessive amount of space, and the resulting electrical connections are slower and noisier than is desirable Accordingly, there is a clear need for an economical technique of increasing the thermal lifetime of direct electrical connections between a semiconductor chip or an interposer and an underlying substrate such as a PCB.

SUMMARY OF THE INVENTION

According to this invention, a connection between a first body such as a semiconductor chip and a second body such as a PCB is formed by a multilayer structure or stack which includes solder layers interleaved with barrier layers The solder layers are made sufficiently thin that a grain boundary sliding form of deformation occurs when the first and second bodies thermally expand or contract at different rates Grain boundary sliding predominates when the solder is finely grained and is distinguishable from matrix deformation, which occurs when the grains of solder are relatively large. Grain boundary sliding is damage-free and reversible, whereas matrix deformation is irreversible. Matrix deformation permanently damages the granular structure of the solder and ultimately impairs the integrity of the electrical connection

Making the solder layers thin creates a thin granular structure and promotes grain boundary sliding In addition, the thinness ofthe solder layers restrains grain growth during thermal cycling, resulting in a stable fine-grained structure

In one group of embodiments the solder layers are less than 50 mm thick and there are at least three solder layers in the stack The solder layers are separated by barrier layers which can include one or more layers or sublayers of Ni, Cu, Co, Pd, Pt or Ru The stack of solder and barrier layers is fabricated by electroplating Small sizes and shapes ofthe connections can be defined using photolithographic processes The applicability of this invention extends far beyond the formation of an array of electrical connections between the respective pads on semiconductor chips (or interposers) and PCBs. This invention can also be used, for example, as a means of attaching a broader area of a semiconductor chip to a heat sink The use of this invention provides dramatically increased thermal lifetimes Replacing a conventional solder bump with a stack containing three solder layers increases the estimated lifetime of the connection from 100 to 2500 thermal cycles. If the number of solder layers is increased to five, the estimated lifetime increases to 5000 thermal cycles or more

BRIEF DESCRIPTION OF THE DRAWINGS

Figs IA and IB illustrate top and side views, respectively, of an array of attach bumps in accordance with this invention

Fig. IC illustrates a detailed view of one of the attach bumps

Fig. 2A illustrates a side view of an attach bump containing three solder layers before reflow.

Fig 2B illustrates a side view ofthe attach bump of Fig 2A after reflow. Fig. 3 illustrates a graph ofthe shear force versus strain rate for matrix deformation and for grain boundary sliding deformation in thick and thin solder layers

Fig 4 illustrates a graph of the strain rate corresponding to the "knee" (shown in Fig 3) as a function of the thickness of the solder layer

Fig. 5 illustrates a graph of the lifetime of a multilayer attach (in thermal cycles) as a function of the number of solder layers in the stack for solder layers of various thickness

Fig. 6 is a detailed side view of an attach bump of this invention containing three solder layers. Fig 7 is a detailed side view of an attach bump of this invention containing two solder layers.

Fig. 8 is a side view of an embodiment containing multilayer attach bumps in series with conventional solder balls

DESCRIPTION OF THE INVENTION

Figs. IA and IB are top and side views, respectively, of a semiconductor chip 10 which contains an array of multilayer attach bumps 12 in accordance with this invention Fig I C is a detailed view of one of the attach bumps 12, which includes a solder layer 13, a Ni/Cu barrier layer 14 and a solder layer 15. Solder layer 15 is in electrical contact with a metal bus

100 16 on the surface ofthe chip 10. (Note that Fig. IC is not drawn to scale.) Thus bump 12 contains two solder layers and an intervening barrier layer.

Figs. 2A and 2B show an attach bump 21 containing three solder layers that is formed on a pad 202 of a semiconductor chip 20. Attach bump 21 includes solder layers 204, 208, 212 and intervening copper layers 206, 210. In Fig. 2 A, attach bump 21 has not yet been

105 bonded to a pad 214 on substrate 22, which could be, for example, a PCB. Fig. 2B shows attach bump 21 after it has been bonded to pad 214 by reflowing the solder layers 204, 208, 212. Also, as is apparent from Fig. 2B, pad 214 has been displaced laterally with respect to pad 202 as a result of differential thermal expansion between chip 20 and substrate 22. The lateral displacement of solder layers 204, 208, 212 is also apparent.

1 10 Each of the solder layers in attach bumps 12 and 21 are preferably less than 50 mm thick. Keeping the solder layers below a thickness of 50 μm insures that the grains in the solder are small and that the predominant form of deformation as the chip and substrate are displaced laterally by temperature variations is grain boundary sliding deformation rather than matrix deformation.

1 15 Fig. 3 illustrates a graph showing the lateral shear force applied to the solder as a function ofthe rate of deformation (strain rate). Curve 30 shows the force vs. strain rate for matrix deformation. Curve 31 shows the force vs. strain rate for grain boundary sliding deformation when the layer is relatively thick (150 μm), and curve 32 shows the force vs strain rate for grain boundary sliding deformation when the solder layer is relatively thin (50

120 μm). A "knee" for the "thick" solder layer indicated at 33 represents the intersection of curves 30 and 31, and a "knee" for the "thin" solder layer indicated at 34 represents the intersection of curves 30 and 32. A thin solder layer cools more rapidly than a thick solder layer, resulting in a higher grain boundary density which shifts the knee to higher strain rates

For example, a differential thermal expansion which produces a shear force of Fj 125 results in a strain rate of Ai from grain boundary sliding deformation in a thin solder layer and a strain rate of A2 from matrix deformation. Since the intersection with curve 32 is below the knee 34, A2 is almost two orders of magnitude below Aj. Thus the predominant form of deformation in a thin solder layer is grain boundary sliding. In contrast, with a thick solder layer the point at which force Fi intersects curve 3 1 (dashed line) yields a strain rate of A3 for 130 grain boundary sliding deformation. The strain rate for matrix deformation remains at A2 since the relationship of strain rate and force for matrix deformation is independent ofthe thickness ofthe solder layer Since the intersection with curve 31 is above knee 33, A2 is somewhat greater than Ai, and matrix deformation predominates

Thus it is apparent from Fig 3 that when the maximum shear force intersects the force 135 vs strain rate curves below the applicable "knee", gram boundary sliding deformation will predominate over matrix deformation, and when the maximum shear force is above the applicable "knee", matrix deformation will predominate Since the "knee" for a thin solder layer is higher than the "knee" for a thick solder layer, grain boundary sliding deformation is more likely to predominate in a thin solder layer 140 During a thermal cycle on a 1/2-mch chip (-40°C to 140°C) the maximum strain rate generated may be estimated, which in Fig 3 is represented by Ai It is seen that when this strain rate is Ai, the maximum force generated in the thick solder joint is F2, and the maximum force generated in the thin solder joint is Fj This translates into a matrix strain rate in the thick solder joint of Ai, and a matrix strain rate in the thin joint of A2, which is lower by about 145 IV2 orders of magnitude Since the damage rate is proportional to the maximum matrix rate, this explains the 4/1 lifetime increase for this thermal cycle in the thin solder layers because most ofthe strain in these joints is generated in the form of grain boundary sliding instead of matnx deformation as is the case for the thick solder joint

The grains in a thin solder layer are much smaller than those in a thick solder layer, and 150 this explains the predominance of grain boundary sliding deformation in the thin layer Grain boundary sliding deformation is essentially "damage free" In contrast, matrix deformation generates voids, cracking and ultimate fracture from the dislocation climb process Moreover, the smaller grains in the thin solder layer recrystahze into small grains during thermal cycling Grain growth is inhibited Thus the thin solder layer insures that the grains are small initially 155 and insures that the small grain size is maintained thereby promoting a lower damage rate

Fig 4 illustrates a graph showing the experimentally determined location of the "knee" as a function ofthe thickness ofthe solder layer As indicated, the knee shifts upward by 2 to 3 orders of magnitude as the layer thickness decreases from about 200 μm to about 75 μm Fig 5 is a graph showing the lifetime of an attach bump as a function of both the 160 thickness of the solder layers and the number of solder layers in the stack The lifetime is represented as the number of thermal cycles (-40°C to 140°C) at which failure occurs For the 175 μm thick layer attach, the lifetime increases only linearly with the number of layers in the attach, increasing only from 50 to 200 thermal cycles (for a four-layer attach). For a 50 μm layer attach the lifetime increases exponentially from about 125 thermal cycles for a single- 165 layer attach to 750 thermal cycles for 2-layer attach to 2500 thermal cycles for a 3-layer attach to 5000 thermal cycles for a 4-layer attach. Similarly, power law increases in lifetime are found for the 37.5 and 25 μm layer attaches.

The multilayer structure of this invention is fabricated by electroplating a succession of solder and barrier layers. Initially, the locations ofthe attach bumps can be defined using 170 conventional photolithographic techniques Fig. IC, for example, shows a photoresist layer 18 (dashed lines) which is used as a mask to define the location of attach bump 12. It may be necessary also to etch an opening in a passivation layer to expose the metal bus or other metal layer to which the attach bump is to be connected. Alternatively, a multilayer laminate of solder and barrier layers can be plated initially and then etched to form the desired attach 175 bumps.

Referring to Fig. 6, a three solder layer attach bump 60 is formed on a silicon die 61, which is typically part of a silicon wafer Initially a TiW or TiCr adhesion/barrier layer 62 is sputtered onto the surface of silicon chip 61 Layer 62 can be in the range of 100-500 nm thick. This is followed by sputtering a 500 nm thick copper seed layer 63 180 This completes the preliminary processing of the silicon chip 61 Next a 2 μm copper layer 64 is electroplated using a sulfate solution This is followed by electroplating a 2 μm nickel layer 65 (high tin content solder) and another 2 μm copper layer 66, which is also electroplated using a sulfate solution

Then a 10-25 μm thick solder layer 67 is electroplated using an acid solution (e g , 185 sulfonic acid). 60/40 solder is preferred because it exhibits the grain boundary sliding mode of deformation for fine grained structures A 1 μm thick copper strike or adhesion layer 68 is electroplated using a copper cyanide solution before the next copper layer is plated.

This completes the processing for one solder layer. Next a copper layer 64A, a nickel layer 65A and a copper layer 66A are electroplated Layers 64A-66A are similar to layers 64- 190 66 This is followed by electroplating a solder layer 67A, which is similar to solder layer 67 and a copper layer 68A, which is similar to copper layer 68 A third solder layer is then formed by electroplating layers 64B-67B which are similar to layers 64-67, respectively

If a photoresist layer is used to define the attach bump, the photoresist is then removed Solder layers 67, 67A and 67B are then heated to a temperature in the range of 220°C to reflow the solder Normally, no sidewalls or other mechanical restraints are needed to confine or support the solder during reflow This produces a fine-grained solder and improves the intermetallic bonding between the solder and adjacent layers Next silicon chip 61 is diced from other chips on the wafer Chip 61 is loaded in a flip-chip bonder and aligned with a metal substrate interconnect 69, which could be a metal pad Conventional tests are then performed to verify the electrical and mechanical integrity ofthe connection between silicon chip 61 and metal substrate interconnect 69.

In the structure of Fig 6, layers 64-66 and 68, 64A-66A and 68A, and 64B, 66B are barrier layers. In this embodiment the barrier layers include copper and nickel layers, but in other embodiments one or more members ofthe group consisting of Co, Pd, Pt and Ru can be used in the barrier layers in addition to or substitution for the copper and nickel layers

Although a three-layer structure is shown in Fig 6, other embodiments may include more or less than 3 solder layers Attach bump 60 shown in Fig 6 has an estimated lifetime of 2500 thermal cycles

For example, Fig 7 shows a two-solder-layer attach bump 70 including a TiW or TiCr layer 72 and a copper seed layer 73 which are electroplated on a silicon chip 71 Layers 72 and 73 are similar to layers 62 and 63 shown in Fig 6 Similarly, layers 74-77 are similar to layers 74A-77A and correspond to layers 64-67 shown in Fig 6 The electroplated structure is reflow bonded to a metalized substrate such as metal pad 69 Alternatively, the electroplated structure can be bonded to a leadframe or heat sink The multilayer attach has an estimated lifetime of 750 thermal cycles

An attach bump in accordance with this invention can be used in other situations such as the one shown in Fig 8 There a ceramic chip carrier 81 is connected to metal pads 82 on a PCB 83 via conventional solder ball joints 84 in series with five-layer attach bumps 85 The solder layers in attach bumps 85 are 50 μm thick and are separated by copper or nickel barrier layers Whereas a single solder layer 150-250 μm thick has an experimental lifetime of only 50 thermal cycles the five-layer attach bumps 85 have a calculated lifetime of at least 5000 thermal cycles

A multilayer laminate structure containing solder and barrier layers can also be used to attach a chip to, for example, a heat sink A single thick solder layer (e g , 100 μm) has poor thermal fatigue resistance when used to connect a semiconductor chip to a copper substrate

By reducing the thickness from 100 μm to 50 μm, the thermal lifetime increases by a factor of two. Reducing the thickness to 25 μm increases the thermal lifetime by a factor of 4-5 As described above, it is the predominance of grain boundary sliding deformation in thin solder layers that accounts for this four- or fivefold improvement in lifetime.

230 Moreover, increasing the number of solder layers to 2, 3, or 4 decreases the operating strain rate linearly by a factor of 1/2, 1/3 or 1/4, respectively The operating strain rate is equal to Δα x (lΛ chip dimension/h) x ΔT/Δt, where Δα is the difference in the thermal coefficient of expansion between the chip and the substrate, h is the height of the solder joint, and ΔT/Δt is the maximum temperature rate of change. By extrapolating the data it is found

235 that the damage rate (i.e., the maximum matrix strain rate in a thermal cycle) decreases by a power of 3 as the number of solder layers increases This provides order-of-magnitude increases in the thermal lifetime of the structure

Multilayer attaches in accordance with this invention can also be used for attaching semiconductor chips to a substrate in chip-on-glass (COG) flat panel displays. This permits a

240 higher density of pixels for better resolution Construction is simplified at reduced costs, and the robustness ofthe display is increased

While specific embodiments according to this invention have been described, it will be understood by those skilled in the art that numerous alternative embodiments are within the scope of this invention

Claims

I claim
1 A multilayer attach for forming a connection between a first body and a second body, said attach comprising a plurality of solder layers and a plurality of barrier layers, adjacent ones of said solder layers being separated by at least one of said barner layers
2 The multilayer attach of Claim 1 wherein said first body comprises a semiconductor chip
3 The multilayer attach of Claim 1 wherein each of said solder layers has a thickness of 50 μm or less
4 The multilayer attach of Claim 3 wherein said barrier layers comprise copper
5 The multilayer attach of Claim 3 wherein said barrier layers comprise copper and nickel
6 The multilayer attach of Claim 3 wherein said barrier layers compπse one or more metals selected from the group consisting of Cu, Ni, Co, Pd, Pt and Ru
7 A combination comprising the multilayer attach of Claim 1 and a first body, said attach being attached to said first body
8 The combination of Claim 7 wherein said first body comprises a semiconductor
9 The combination of Claim 8 further comprising an adhesion layer interposed between said attach and said first body
10 The combination of Claim 9 wherein said adhesion layer comprises a material selected from the group which consists of TiW or TiCr
1 1 A method of forming an attach bump comprising the steps of electroplating a first solder over a semiconductor chip. elecroplating a first metal barrier layer on said first solder layer, and electroplating a second solder layer on said metal barrier layer
280
12. The method of Claim 1 1 wherein the step of electroplating a first metal barrier layer comprises electroplating a copper layer.
13. The method of Claim 1 1 wherein each ofthe steps of electroplating said first 285 and second solder layers comprises electroplating a solder layer less than 50 μm thick.
14 The method of Claim 1 1 wherein each of the steps of electroplating said first and second solder layers comprises electroplating a solder layer 10-25 μm thick
290 15. The method of Claim 11 wherein each ofthe steps of electroplating said first and second solder layers comprises electroplating a solder layer using an acid solution
16. The method of Claim 1 1 wherein the step of electroplating a first metal barrier layer comprises electroplating a copper layer using a copper cyanide solution
295
17. The method of Claim 1 1 further comprising the step of forming an adhesion/barrier layer between said semiconductor chip and said first solder layer
18 The method of Claim 17 wherein the step of forming an adhesion/barrier layer 300 comprises forming a layer of a material selected from the group consisting of TiW and TiCr
19 The method of Claim 1 1 comprising the further steps of electroplating a second metal barrier layer on said second solder layer, and electroplating a third solder layer on said second metal barrier layer
305
20. The method of Claim 19 comprising the further step of reflow bonding said attach bump to a metal conductive layer
PCT/US1997/007155 1996-04-29 1997-04-29 Multilayer solder/barrier attach for semiconductor chip WO1997041594A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US845,582 1986-03-28
US1643096P true 1996-04-29 1996-04-29
US60/016,430 1996-04-29
US84558297A true 1997-04-25 1997-04-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AU29278/97A AU2927897A (en) 1996-04-29 1997-04-29 Multilayer solder/barrier attach for semiconductor chip

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WO1997041594A1 true WO1997041594A1 (en) 1997-11-06

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WO (1) WO1997041594A1 (en)

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US6893799B2 (en) 2003-03-06 2005-05-17 International Business Machines Corporation Dual-solder flip-chip solder bump
US6897123B2 (en) 2001-03-05 2005-05-24 Agityne Corporation Bonding of parts with dissimilar thermal expansion coefficients
US8348139B2 (en) 2010-03-09 2013-01-08 Indium Corporation Composite solder alloy preform
WO2013016276A3 (en) * 2011-07-26 2013-04-11 Fujitsu Limited Hybrid interconnect technology
WO2013147808A1 (en) * 2012-03-29 2013-10-03 Intel Corporation Functional material systems and processes for package-level interconnects
WO2020070635A1 (en) * 2018-10-01 2020-04-09 Rise Technology S.R.L. Making multi-component structures with dynamic menisci

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