WO1997035342A1

WO1997035342A1 - Printed wiring board substrate for chip on board device and process for fabrication thereof

Info

Publication number: WO1997035342A1
Application number: PCT/US1997/004563
Authority: WO
Inventors: Graham J. H. Wells; Christopher L. Caron; Paul John Schwab
Original assignee: The Whitaker Corporation
Priority date: 1996-03-22
Filing date: 1997-03-17
Publication date: 1997-09-25

Abstract

A multilayer printed wiring board substrate (1) has conductive traces (2) thereon and a plurality of vias (3) therethrough. The substrate (1) has a topside soldermask (9) and a bottomside soldermask (10). The bottomside soldermask (10) has moisture relief areas (15) disposed over the vias (3). A process for improving yield of a chip on board device comprises the steps of applying a coating of soldermask to a surface of a printed wiring board substrate and creating an opening in the soldermask disposed over one or more vias.

Description

PRINTED WIRING BOARD SUBSTRATE FOR CHIP ON BOARD DEVICE AND PROCESS FOR FABRICATION THEREOF

The interest of miniaturization of electronic instrumentation has lead to the desirability of mounting integrated circuit die directly onto a printed wiring board substrate. Integrated circuit die contacts are wire bonded to conductive traces on the printed wiring board to create a circuit. The die and wire bonds are covered by an encapsulent, colloquially referred to as "glob top". The populated printed wiring board assembly is referred to as a "chip on board" device.

In practical use, the chip on board device has leads on a perimeter of the printed wiring board substrate. The leads are attached to a larger printed wiring board to create an assembly. The device therefore, is subjected to a solder reflow process for inclusion in a second and larger printed wiring board. To assure a working part, the chip on board device is subjected to an environmental qualification test. The environmental qualification test assures that the chip on board devices are able to withstand uncontrolled storage and two solder reflow operations. Accordingly, the environmental qualification testing for the chip on board device is comparable to environmental testing for a discrete device. A current relevant environmental qualification test for electronic devices calls for a temperature of 85° Celsius at 85% relative humidity with bias voltage applied for 1000 hours. As a result of this environmental testing, many chip on board devices fail thereby adversely affecting yield. The failures are caused by cracking and delamination between the encapsulent and the printed wiring board substrate. Delamination is sometimes referred to as "popcorning" and is a known phenomenon in the plastic IC packaging industry.

An article written by Yalamanchili, Gannamani, et al. entitled "Optimum Processing Prevents PQFP Popcorning" published in May 1995 identifies possible sources of failures in plastic IC packages. The article explains the failure mode as the result of the phase change and expansion of internally condensed moisture in the plastic during exposure to solder reflow temperatures. A solution suggested by the article is directed toward control of the temperature in the solder reflow operation. Disadvantageously, the ideal reflow profile removes the flexibility to use the parts with different reflow processes and requires an additional level of control and monitoring of the process that would not otherwise be required.

Delamination of chip on board devices occurs at one or more of the mechanical interfaces of the chip on board device such as between the soldermask layer and the surface of the printed wiring board substrate, between the conductive traces and the surface of the printed wiring board substrate, and between the encapsulent and the soldermask on the surface of the printed wiring board substrate. Delamination causes a multitude of failure modes, is unpredictable, and is one of the major obstacles to commercial practicability of chip on board devices. Delamination of the encapsulent can lift the die off the printed wiring board and shear the wire bond that connects the die to the conductive trace.

There is a need, therefore, to increase the yield of the chip on board devices by preventing delamination when the chip on board device is subjected to environmental qualification testing and/or solder reflow operations.

The aforementioned problems are solved by a chip on board printed wiring board substrate manufacturing process according to the teachings of the present invention comprising the steps of applying a coating of soldermask to a surface of the printed wiring board substrate and creating an opening in the soldermask disposed over one or more vias.

The aforementioned problems are solved by a chip on board device according to the teachings of the present invention in which a printed wiring board substrate having conductive traces thereon and a plurality of vias therethrough has a coating of soldermask thereon with moisture relief areas disposed over the vias on a surface of the printed wiring board substrate. Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:

Figure 1 illustrates a mask for a coating of soldermask on a top side of the chip on board device printed wiring board substrate.

Figure 2 - 7 are mask sets for each layer of a multilayer chip on board device printed wiring board substrate according to the teachings of the present invention. Figure 8 illustrates a mask for a coating of soldermask on a bottom side of the chip on board device printed wiring board substrate.

Figure 9 is an illustrative cross section of vias on a chip on board device according to the teachings of the present invention wherein a moisture relief area in the soldermask is disposed over the vias.

A chip on board device comprises printed wiring board substrate (1) having multiple layers of a polyimide electrically insulating material. Each layer of polyimide has conductive areas or traces (2) thereon. A preferred printed wiring board polyimide and prepreg is the N 7000-1 series manufactured by New England Laminates Company, Inc., a subsidiary of Park Electro Chemical Corporation. The N 7205-1 laminate and N 7305- l prepreg is preferred. Vias (3) on and through the substrate (1) provide electrical conductivity from a top side (4) of the printed wiring board substrate (1) shown in Figure 2 to intermediate layers shown :.n Figures 3 • 6 and/or to a bottom side (5) of the printed wiring board substrate (1) shown in Figure 7. In operation, a via (3) carries either ground potential or DC or RF signal to effect a desired circuit. The via (3) comprises an annular rim (6) of substrate (1) having an inner cylindrical surface (7) „ The inner cylindrical surface (7) is plated with a layer of a conductive material, typically metal and preferably copper. Electrical connection is made to one or more layers of the printed wiring board substrate (1) including for example ground plane (8) by contacting a conductive trace (2) to the plated inner cylindrical surface (7) . Signal and RF vias (3) are not electrically connected to a ground plane. The ground plane layers, shown in

Figures 3 and 5, have an insulating rim surrounding all signal and RF vias (3) . Due to conventional methods for creating a via (3) , the via (3) necessarily creates an evacuated area or hole through the printed wiring board substrate (1) .

It is conventional to coat the top and bottom sides (4,5) of the printed wiring board substrate (1) with a protective coating of soldermask (9,10). Soldermask covers all areas where solder or a wirebond electrical connection is not desired. A preferred soldermask is Probimer^® 52M available from CIBA-GEIGY. Soldermask provides an electrically insulating and environmentally protective coating over the printed wiring board substrate (1) . The conventional soldermask coating covers the vias (3) on both sides of the printed wiring board substrate (1) . On the top side (4) of the substrate (1) the top side soldermask (9) does not cover those areas to which a die (11) or wirebond (12) is to be attached. It is desirable, however, to cover the top side or die attached side of the via (3) with a layer of soldermask for chip on board devices. The coating of soldermask over the via (3) serves two functions. During assembly of the chip on board device, the printed wiring board substrate is held to a chuck using vacuum. The soldermask coating permits evacuation of air between the substrate (1) and the chuck which enables sufficient retention of the substrate (1) to the chuck for assembly of the device. The soldermask coating also prevents liquid encapsulent (13) from flowing through the vias (3) during the encapsulation or "glob top" process. The bottom side (5) of the printed wiring board substrate has a coating of bottom side soldermask (10) . In prior art chip on board devices, a curtain coat of soldermask is applied over substantially the entire surface on the bottom side of the printed wiring board substrate. Top and bottom side soldermask (9,10) is developed away from contact points on the perimeter of the substrate (1) only, to permit attachment of a lead frame. The vias (3) on prior art chip on board devices, therefore, are coated with soldermask on the top and bottom of the substrate. It has been discovered that a cause of the delamination problem is moisture trapped in the via (3) between the soldermask (9) on the top sid (4) of the substrate and soldermask (10) on the bottom side (5) of the substrate. Moisture existed in the via (3) either by way of entrapment upon application of the two soldermask coatings or by way of ingress through the soldermask during temperature and humidity qualification test. After the environmental test, the chip on board device is subjected to 235°C temperature extreme on two separate occasions, while simulating a temperature profile for a solder reflow operation and rework. The heating process caused rapid expansion of the moisture trapped in the via (3) between the soldermask layers

(9,10). The resulting build up of pressure inside the via (3) exerted an expansion force on opposite ends of the via (3) . The forces from the pressure in the via

(3) in some instances exceeded the adhesinn strength of the encapsulent (13) to the top side soldermask (9) . When this happened, the pressure caused a crack to occur and lifted the encapsulent (13) off the printed wiring board substrate (1) . As the wirebond (12) is suspended in the encapsulent (13) , the resulting movement of the encapsulent (13) caused the wirebond (12) to break away from the conductive trace (2) to which it had been electrically attached. The break caused an open circuit and a device failure. The solution to this problem according to the teachings of the present invention is to remove the layer of soldermask bottom side (10) on the printed wiring board substrate (1) that covers the. via (3) . Removal of the layer around the via (3) creates a moisture relief area (15) disposed over the vias (3) . Moisture is, therefore, not trapped in the via (3) and is permitted to out gas naturally during heating. It is preferred that the present invention be affected by a change in the artwork for the bottom side (5) of the printed wiring board substrate (1) which is shown in Figure 8 and which is described more fully herein.

Manufacture of the multilayer chip on board substrate (l) up to and including the metalization step that creates the conductive traces (2) and the plated vias (3) on the substrate (1) is conventional in the industry. See for example U.S. patent 5,359,767 to Chen, et al. After metalization of the substrate (1), a liquid via plug soldermask is silk screened over all vias (3) on the top side (4) of the substrate (1) in the form of circular plugs. For a via (3) having a 10 mil diameter the via plug has a 25 mil diameter for proper registration. The liquid silk screened via plug soldermask (9) is then permitted to cure. Thereafter, a curtain coat of a liquid photoimageable soldermask (9) is applied to the substrate (1) and is permitted to cure according to conventional practice. The top side soldermask (9) is selectively exposed to ultraviolet light through appropriate art work an advantage of which is shown in Figure 1. Alternative methods of forming an appropriate top side soldermask (9) include application of a curtain coat of either positive or negative photoimageable soldermask material. The present invention uses a negative photoimageable soldermasking process whereby the artwork soldermask comprises a mylar film having a pattern of darkened areas thereon corresponding to areas of the soldermask (10) that are to be removed. Exposure to UV light through the artwork polymerizes the soldermask (10) to be retained. After the selective exposure to ultraviolet light, the printed wiring board (1) is sent through developer chemistry to selectively remove the nonpolymerized areas of the soldermask (10) „ Advantageously, the top side of soldermask (9) is disposed over the vias and prevents the flow of liquid encapsulent through the via (3) during the chip on board population and encapsulation process. A curtain coat of negative photoimageable is applied to the bottom side (5) of the printed wiring board substrate (1) . The bottom side soldermask (10) is selectively exposed to UV light through artwork. With specific reference to Figure 8 of the drawings, artwork for a bottomside soldermask (10) according to the teachings of the present invention comprises darkened circular areas corresponding to vias (3) on the printed wiring board substrate. Selective exposure of UV light through the artwork polymerizes all areas of the bottom side soldermask (10) except the lead attached area (14) around the perimeter of the printed wiring board substrate (1) and the moisture relief areas (15) that align with the vias (3) are polymerized. The printed wiring board substrate (1) is sent through developer chemistry to develop away the nonpolymerized areas. The result is a bottom side soldermask (10) having moisture relief areas (15) disposed over all of the vias (3) , including ground, signal and RF vias (3) , on the printed wiring board substrate (1) . Preferably, a ten mil diameter via (3) would have a 30 mil darkened area or pad on the artwork for the bottom side soldermask (10) of the printed wiring board substrate (1) in order to create the moisture relief area (15) . The 30 mil clearance provides for proper registration to the 10 mil diameter via (3) . It is preferred, but not necessary for the via (3) to be fully clear. A partial clearance of the via (3) results in similar advantages provided that there is sufficient clearance for release of pressure built up in the via (3) . Alternatively, although less preferred, a drilling or other removal operation of the soldermask disposed over the vias (3) will provide a moisture relief advantage and prevent delamination. Clearance of the via (3) on the bottom side (5) of the substrate prevents entrapment of moisture that would create a pressure build up to cause delamination. In the conventional process, the bottom side soldermask (10) is removed in the lead attach area (14) . It is, therefore, not necessary to increase the time and or cost of processing by adding a processing step. The improvement is made by adding the moisture relief areas (15) to the bottom side soldermask artwork. Advantageously, a chip on board process according to the teachings of the present invention does not require an additional processing step.

Population of the chip on board printed wiring board substrate (1) comprises an epoxy application and die attach process to adhere the IC die (11) to the printed wiring board substrate (1) . After the epoxy has cured and the die is attached, contacts on the die (11) are wire bonded (12) to the conductive traces (2) on the printed wiring board substrate (1) . After population and interconnection, liquid encapsulent (13) is placed over the IC die (11) and wirebond (12) and in some cases vias (3) . The encapsulent (13) electrically insulates and protects the die (11) and wirebond (12) . A lead frame (not shown) is soldered to the lead attach area (14) of the chip on board device using solder having a eutectic temperature greater than the solder used to attach the chip on board device to the larger printed wiring board substrate. After attachment, the leads are trimmed and formed to complete the chip on board device. Other advantages of the invention are apparent from the detailed description by way of example, and from the accompanying drawings, and from the spirit and scope of the appended claims.

Claims

5342 PCI7US97/04563CLAIMS :

1. A printed wiring board comprising a substrate (1) having conductive traces (2) thereon, a plurality of vias (3) therethrough, and a soldermask (9,10) on the surface of said substrate (1) the improvement comprising moisture relief areas (15) disposed over he vias (3) .

2. A printed wiring board substrate as recited in claim 1 and further comprising a top side soldermask (9) disposed over the vias (3) and a bottom side soldermask (10) having the moisture relief areas (15) disposed over the vias (3) .

3. A printed circuit board comprising a substrate having conductive traces (2) thereon and a plurality of vias (3) therethrough, a plurality of encapsulated die (ll) interconnected by the traces (2) , a bottom side soldermask (10) on a surface of the substrate (1) the improvement comprising moisture relief areas (15) disposed over the vias (3) .

4. A printed wiring board substrate as recited in claim 3 and further comprising a top side soldermask (9) disposed over the vias (3) and a bottom s .de soldermask (10) having the moisture relief areas (15) disposed over the vias (3) .

5. A process for improving yield of a chip on board substrate (1) having vias (3) therethrough comprising the steps of applying a layer of soldermask (10) to a bottom side (5) of the substrate (1) the improvement comprising removing the soldermask (10) in an area disposed over the vias (3) .

6. A process for improving yeild of a chip on board substrate (1) as recited in claim 5 wherein the step of removing the soldermask (10) in an area disposed over the vias (3) further comprises the step of applying a negative photoimageable soldermask (10) on a bottomside (5) of the substrate (1) , selectively exposing the bottomside soldermask (10) to ultraviolet light, developing away the nonexposed soldermask in an area disposed over the vias (3) to create moisture relief areas (15) .

7. A process for improving yeild of a chip on board substrate (1) as recited in claim 5 wherein the step of removing the soldermask (10) in an area disposed over the vias (3) further comprises the step of applying a positive photoimageable soldermask (10) on a bottomside (5) of the substrate (1) , selectively exposing the bottomside soldermask (10) to ultraviolet light, developing away the nonexposed soldermask in an area disposed over the vias (3) to create moisture relief areas (15) .

8. A process for improving yield of a chip on board substrate (1) having vias (3) therethrough as recited in claim 5 wherein the step of removing the soldermask (10) in an area disposed over the vias (3) further comprises drilling a hole through the soldermask (10) in an area disposed over the vias (3) to create moisture relief areas (15) .

9. A process for improving yield of a chip on board substrate (1) as recited in claims 5, 6, 7 and 8, the substrate having vias (3) therethrough and further comprising the step of applying a layer of soldermask (9) to a topside (4) of the substrate (1) to cover the vias (3) .