WO1997022950A1 - Apparatus for filling an image - Google Patents

Apparatus for filling an image Download PDF

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Publication number
WO1997022950A1
WO1997022950A1 PCT/CZ1996/000025 CZ9600025W WO9722950A1 WO 1997022950 A1 WO1997022950 A1 WO 1997022950A1 CZ 9600025 W CZ9600025 W CZ 9600025W WO 9722950 A1 WO9722950 A1 WO 9722950A1
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WO
WIPO (PCT)
Prior art keywords
color
edge
level
colors
pixel
Prior art date
Application number
PCT/CZ1996/000025
Other languages
French (fr)
Inventor
Jan Z^¿ÁC^¿EK
Original Assignee
Dataline Technology Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dataline Technology Ltd. filed Critical Dataline Technology Ltd.
Priority to AU10292/97A priority Critical patent/AU1029297A/en
Publication of WO1997022950A1 publication Critical patent/WO1997022950A1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/002D [Two Dimensional] image generation
    • G06T11/40Filling a planar surface by adding surface attributes, e.g. colour or texture

Definitions

  • Filling accelerator for pixel displays with outline chaining compression, visibility counting and texturing relates to and is an advantage in the computer graphics and preferably in computer games, multimedia, DTP and CAD where high resolutions and full color palette are used.
  • character displays are used to display texts and pixel displays to display graphics whereby every picture point, called pixel is stored in the picture memory.
  • the picture memory is served by a picture processor which carries out saving of all points of a picture in memory, periodical reading of such data and displaying them on a monitor.
  • a picture processor which carries out saving of all points of a picture in memory, periodical reading of such data and displaying them on a monitor.
  • the volume of information stored also increases. Therefore, use of large picture memories is necessary and with increasing volume of information the displaying is significantly slower.
  • To decrease the time necessary for displaying a number of processors were invented that accelerate saving of the points in the picture memory, but the most rapid is to avoid entry of the redundant points.
  • the invention consists in a method how to create an image in the picture memory of a pixel display without the necessity to save the redundant points, how to unpack this image from the compressed form, method how to increase the number of colors, color change continuity, without necessity to increase the data volume, method how to facilitate visibility calculation and a device serving for such purposes.
  • the method how to create an image in a picture memory of a pixel display in a mode where each point corresponds to a byte in the video memory and can acquire values from 0 to 255 what is the logical color and represents an address of the pallet register, where the real color is stored, consists in the existence of a filling accelerator.
  • the principle is such that that one number, preferably 255 (FFh) is a repeater which repeats the previous color, i.e. a number, in the direction of screen line drawing.
  • FFh a repeater which repeats the previous color, i.e. a number, in the direction of screen line drawing.
  • the screen is erased, i.e. filled, with the repeater 255, at first. Thereafter, the left edges of objects are being drawn and during erasing only the edges can be erased by the number 255 i.e. by the repeater.
  • An advantage of this is a reduction in the stored data volume and consequently an increase of speed.
  • the serial color consists in a filling accelerator which uses a pixel display in the mode of logic colors, where one pixel corresponds to one byte, but the video memory contains real colors recorded serially one after another, in two bytes HiColor or in three bytes True Color where a color can be saved on any pixel but the following one or two bytes have to be repeated.
  • the filling accelerator consists in a color register which is inserted between the data pixel output from the video processor and a D/A converter or a RAMDAC palette converter.
  • the principle consists in that the data output from the video processor is connected to the logical member which in case of output of a chosen number, preferably 255 (FFh) , stops the clock signal, entering said pixel data into the register, whereby the previous number (color) remains in the register output for the time the chosen number is being repeated.
  • the color interpolation between edges for increasing the picture quality consists in that in the direction of the beam running the previous edge specifies the initial color and the current edge with an integration attribute specifies the color into which it will be integrated for a certain time. Therefore, in a determined distance the color intensity of the actual edge determines the rate of integration.
  • the integration will be finished when the specified color is reached or by interruption by the following edge, eventually by reaching the white or the black color.
  • the color interpolator consists of individual integrators of the color components R G B, where the analog variant is comprised of an analog switch switching on integration on a capacitor in the presence of indication of an integration in data or the digital one which is comprised of an adder and an accumulator adding the difference between the previous and the current edge, packed by so many binary orders as is the global distance for which the color is interpolated.
  • integrators representing individual levels that are connected so that always the highest non-zero one (zero corresponds to black - transparent level) is connected to the output D/A converter through the multiplexor.
  • the colors are entered to the integrators according to their level numbers that are stored in the palette registers or directly in data items.
  • a transfer to a higher level is carried out by entering the color into this higher level and the transition to the lower level (right object edge) is carried out by entering zero i.e. black into this level, eventually by entering the same number i.e. reset into this level.
  • the increase of the number of colors in the mode of 256 colors per pixel consists in that there are two or more levels - individual color registers, and colors of said levels are mixed preferably by multiplying the brightness component of one level, representing turning angle of the facet to the light source, with the color component of the other level, representing the surface - facet texture.
  • Drawing of a minute texture consists in that each texture assigned to a logic color represents a level, whereby such levels overlap each other ascendently, and each texture uses multilevel mixing with a color or brightness at the same time. Fine textures can be reached by brightness or color modulation of serially read bites zoomable - N-times repeated, parallelly saved immediately after the texture activator and by repeating of the texture up to the ending at this level.
  • the outline chaining compression consists in a method of packing data for the unpacking processor, whereby the beginning of the outline edge is defined as an entry point of position X,Y on the screen and by color and follow ⁇ a bit chain of deviations specifying the position or the direction of the subsequent point of the outline edge that delimits the area of one color or of one color gradient.
  • the chain fractal compression consists in that similar chains are saved only once in memory and the remaining occurrences reference to said chains specifying position, size and angle parameters.
  • the trimming buffer consists in creating a list of lines and in them a list of the right edge and the left edge points that merge, whereby a line list of no -continuous occupied sections is created and during every point entry a question is raised whether it is not placed in the occupied section.
  • edges - items of information - about the initial point, direction and repeating are entered into the erasing buffer, wherefrom they are read and drawn into the video memory by the repeater color during erasing.
  • Figure 1 is a block diagram of one embodiment of the filling accelerator.
  • Figure 2 shows a analog integrator of color components and
  • Figure 3 is a digital modification.
  • Figure 4 shows an example of the chaining compression format.
  • the invention can be realized as an external additional device attached to the graphic card.
  • the VGA feature connector can be used having an output of the logic color from the video processor, use another RAMDAC palette circuit and an analog integrator.
  • the whole device can be reduced to color registers and direct D/A converters.
  • the whole invention can be incorporated and realized within the RAMDAC circuit.
  • a digital integrator of better quality can be used.
  • some of the real color modes HiColor or TrueColor can be used.
  • the Figure 1 shows an example of the filling accelerator embodiment which is incorporated between the video processor output 1 and the RAMDAC input 3_ of the palette D/A converter.
  • the accelerator is comprised of a logic member _, which in case of the repeater 255 (FFh) presence stop ⁇ through the gate ⁇ the clock signal PCLK entering data into the D regi ⁇ ter 2-
  • FFh repeater 255
  • the accelerator is created from programmable components or directly on a chip, it is preferable to use other number as the repeater, e.g. COH, because of compatibility with Windows.
  • the Figure 2 shows a simplified modification of the analog integrator of one of the three RGB color components.
  • the integrators are connected between the RAMDAC and the monitor. If it does not integrate, the analog switch 1 is switched on and the ⁇ all capacity of the capacitor C 3 i ⁇ fed by a hard signal source. During integration, the analog switch is switched off and the voltage of the capacitor C 3 is integrated through the resistor R 2 up to the voltage value at the input for the time determined by the RC constant.
  • the emitter follower with transistor T. 4_ only adapts the load resistor between the monitor and the integrator. The simplicity of this diagram is counterbalanced by non-linearity of the capacitor charging rate that is exponential.
  • Figure 3 shows an example of the digital integrator where it is possible to reach sufficient linearity and edge sharpness with eight-bit converter. In addition, it is possible to the change integration time simply and eventually to continue in the integration with the given gradient further, up to the minimal intensity of the given RGB color component. If the edge is not integrated then its color - color component - is entered through the multiplexor 2 to the register 2 and is displayed on monitor through the D/ converter 6_. If the data items bear an attribute of integration and the edge is integrated, then the difference between the previous and the current edge is carried out through the multiplexor 3_ in the subtracter 5_ and it is entered into the register 4,. In the register 4. the value is packed, separated in binary form in accordance to what distance it will be integrated.
  • the negative difference from the register is subtracted from the existing data from the register 2. in the subtracter 5_ and is entered into register 2 through multiplexor 1 as new data items.
  • the integration is terminated if a color component at the input level is reached, what is found by the compilator 1, or if the maximum or the minimum value is reached.
  • the integration attribute can be in data, e.g. some bit specifies a group of the integration colors or can be saved in the palette.
  • the Figure 4 shows an example of data storage during the chained outline compression, where X,Y is the position of the chain introduction followed by a bit ⁇ chain of differences of the subsequent pixels which creates the outline edge.
  • the so stored data item ⁇ take minimum place in memory and enable that the central processor or the simple graphic accelerator rapidly unpacks a large quantity of information about the image. For example, if it is a two-bits chain it is the operation of adding or subtracting one.
  • the chain can have a different, pre-determined number of bit ⁇ .
  • the differences can be absolute or relative, the chains can grow into different directions or they can be limited to a direction, e.g. from above downwards, they can contain in the end a terminator or they can have a determined number N of the chain link ⁇ .
  • the chains can be transformed spherically, i.e. zoomed, rotated, and fractally associated, whereby in case of similar changes with attributes of transformation a reference can be made to such chains. This all can be done without any loss of the image quality and with high degree of compression of such image stored in memory.
  • the mix mode can be used.
  • the pixel display runs in the logic color mode, but the filling accelerator runs in the real color mode, whereby two (HiColor) or three (TrueColor) subsequent bytes are considered as a real color and the following one or two bytes have to be repeated.
  • color is stored in series in the video memory, whereby memory capacity is saved.
  • integrators can be grouped that represent levels and the highe ⁇ t non-zero one is displayed.
  • the highest non-zero (zero correspond ⁇ to black - transparent level) integrator is connected to the output D/A converter via a multiplexor. Colors are entered into integrators according to their respective level numbers, that are saved in the pallete registers or directly in the data items. Tran ⁇ er to a higher level (nearer to the observer) is carried out by recording this color into this higher level and transfer to a lower level (the right outline of the object) by recording of zero - black - on thi ⁇ level, eventually by recording the same number - reset - on this level.
  • this palette into four blocks that aree also levels, with 64 logic colors, whereby e.g. one block represent ⁇ 64 brightnesses and the other block 64 colors and by multiplying we obtain more than 4000 shades.
  • the separation of both components can be used preferably for independent drawing, whereby the brightness represents angle of the facet to the light source and color represents vectorized broad texture.
  • Another block can be used a ⁇ a level in the foreground for sprite fractal graphics and texts and another block for fine textures.
  • Minute textures associated e.g. to the upper quarter of logic colors, can represent independent levels that overlap upwards and information about what color or brightness bits are inverted, about zoom, repeating the texture bits and about the bit form itself of the texture is saved in memory which was originally allocated to the RGB color components. The texture is then repeatedly displayed till this level is finished whereby visibility of the texture with the highest number is ensured. Or in direct mode the number of logic color carries the information about ground color or brightnes ⁇ modulation and about the zoom ⁇ ize directly and the immediately following bytes contain ⁇ erial bite ⁇ hape of the texture. Repeating of thi ⁇ texture can be fini ⁇ hed by recording the brightness, color or of an empty texture. Big textures are convenient to create as vectorized.
  • the cutting and erasing buffer can be created both by software and hardware.
  • a list of occupied lines is formed in memory and thi ⁇ li ⁇ t make ⁇ a reference to a list of points of the right and the left edges, that merge and so a list of non-continuous occupied sections is formed.
  • a question is raised whether it is not situated in the occupied section. If not, it is displayed, if yes it is cut off shifted to the right to the end of the buffer, if it i ⁇ within the limits of the displayed facet.
  • the facets are displayed and sorted beginning with the front side.
  • the cutting buffer can be a two-level one, whereby the first level represents a quick ⁇ egment buffer having the occupied ⁇ egments marked (segment 8x8, 16x16 pixels) . All edges - information about the starting point, gradient and repeating are recorded in the erasing buffer, wherefrom they are read and drawn into the video memory by the repeater color during erasing.
  • the filling accelerator can be used for all computer systems, preferably for personal computers (PC) whereby it makes possible to use graphics in the same way as it is in case of the graphic working stations. It is an enhancement mainly in softwares for CAD visualization ⁇ , DTP and computer game ⁇ that depend mainly on the hardware speed. Moreover, the high data compression, if the fractal compression is used, makes possible to store much longer image sequences in the memory medium at high image quality and the possibility to connect shutter 3D spectacles make ⁇ possible to create scene ⁇ of virtual reality.

Abstract

Filling accelerator which is inserted between the video processor and the RAMDAC and makes possible to draw only edges of object on a pixel display. The principle is such that one number of a logical color, preferably 255 (FFh) represents a repeater by which the whole screen is filled. Thereafter, the left outlines of objects are drawn that are filled with the color of the edge by the filling accelerator. During erasing it is possible to erase only said edges by the repreater 255. The accelerator is a color register whereby its input clock is stopped when data corresponding to the repeater are being received. To increase the number of colors the serial input can be used, three consecutive bytes correspond to TrueColor and two pixels have to be repeated. If there is an interpolation attribute of data items, the previous edge determines the initial color and the current edge determines the color into which it will be integrated for a certain distance (time). The integration is finished when this color or white has been reached or by an interruption by the following edge. To simplify the calculation of visibility there are several integrators that represent levels and currently the highest non-zero one is displayed. The outline chain compression is defined as the point of introducing the X, Y edge and of a color and a bit chain of deviations follows specifying the position of the subsequent point. The chain fractal compression makes possible to reference to similar changes with parameters of position, size and angle. The number of shades can be increased by dividing the palette to color and brightness and by their multiplication. Fine textures can be displayed by modulation of the brightness or the color component by serial bits, stored parallely behind the edge. The cutting buffer makes a list of occupied uncontinuous sections and facets are drawn from the front side.

Description

Apparatus for filling an Image.
Field of the Invention
Filling accelerator for pixel displays with outline chaining compression, visibility counting and texturing relates to and is an advantage in the computer graphics and preferably in computer games, multimedia, DTP and CAD where high resolutions and full color palette are used.
Background of the Invention
In the field of computer technique character displays are used to display texts and pixel displays to display graphics whereby every picture point, called pixel is stored in the picture memory. The picture memory is served by a picture processor which carries out saving of all points of a picture in memory, periodical reading of such data and displaying them on a monitor. With increasing demands on the highest possible resolution ability and number of colors, what is required especially in the field of CAD visualization, the volume of information stored also increases. Therefore, use of large picture memories is necessary and with increasing volume of information the displaying is significantly slower. To decrease the time necessary for displaying a number of processors were invented that accelerate saving of the points in the picture memory, but the most rapid is to avoid entry of the redundant points.
Summary of the Invention
The invention consists in a method how to create an image in the picture memory of a pixel display without the necessity to save the redundant points, how to unpack this image from the compressed form, method how to increase the number of colors, color change continuity, without necessity to increase the data volume, method how to facilitate visibility calculation and a device serving for such purposes.
The method how to create an image in a picture memory of a pixel display in a mode where each point corresponds to a byte in the video memory and can acquire values from 0 to 255 what is the logical color and represents an address of the pallet register, where the real color is stored, consists in the existence of a filling accelerator. The principle is such that that one number, preferably 255 (FFh) is a repeater which repeats the previous color, i.e. a number, in the direction of screen line drawing. During drawing of an image the screen is erased, i.e. filled, with the repeater 255, at first. Thereafter, the left edges of objects are being drawn and during erasing only the edges can be erased by the number 255 i.e. by the repeater. An advantage of this is a reduction in the stored data volume and consequently an increase of speed.
The serial color consists in a filling accelerator which uses a pixel display in the mode of logic colors, where one pixel corresponds to one byte, but the video memory contains real colors recorded serially one after another, in two bytes HiColor or in three bytes True Color where a color can be saved on any pixel but the following one or two bytes have to be repeated. An advantage is the lower memory required at the expense of less focussed corners what is unperceivable in case of high resolution.
The filling accelerator consists in a color register which is inserted between the data pixel output from the video processor and a D/A converter or a RAMDAC palette converter. The principle consists in that the data output from the video processor is connected to the logical member which in case of output of a chosen number, preferably 255 (FFh) , stops the clock signal, entering said pixel data into the register, whereby the previous number (color) remains in the register output for the time the chosen number is being repeated.
The color interpolation between edges for increasing the picture quality consists in that in the direction of the beam running the previous edge specifies the initial color and the current edge with an integration attribute specifies the color into which it will be integrated for a certain time. Therefore, in a determined distance the color intensity of the actual edge determines the rate of integration. The integration will be finished when the specified color is reached or by interruption by the following edge, eventually by reaching the white or the black color. An advantage of it are the fully continuous color transitions and a decrease of the number of edges that are created by quantification of the color transitions.
The color interpolator consists of individual integrators of the color components R G B, where the analog variant is comprised of an analog switch switching on integration on a capacitor in the presence of indication of an integration in data or the digital one which is comprised of an adder and an accumulator adding the difference between the previous and the current edge, packed by so many binary orders as is the global distance for which the color is interpolated.
To make the visibility calculation more easy there are several integrators representing individual levels that are connected so that always the highest non-zero one (zero corresponds to black - transparent level) is connected to the output D/A converter through the multiplexor. The colors are entered to the integrators according to their level numbers that are stored in the palette registers or directly in data items. A transfer to a higher level (nearer to the observer) is carried out by entering the color into this higher level and the transition to the lower level (right object edge) is carried out by entering zero i.e. black into this level, eventually by entering the same number i.e. reset into this level.
The increase of the number of colors in the mode of 256 colors per pixel consists in that there are two or more levels - individual color registers, and colors of said levels are mixed preferably by multiplying the brightness component of one level, representing turning angle of the facet to the light source, with the color component of the other level, representing the surface - facet texture. By multiplying the color and the brightness values in this way you can obtain thousands of color shades by order.
Drawing of a minute texture consists in that each texture assigned to a logic color represents a level, whereby such levels overlap each other ascendently, and each texture uses multilevel mixing with a color or brightness at the same time. Fine textures can be reached by brightness or color modulation of serially read bites zoomable - N-times repeated, parallelly saved immediately after the texture activator and by repeating of the texture up to the ending at this level.
The outline chaining compression consists in a method of packing data for the unpacking processor, whereby the beginning of the outline edge is defined as an entry point of position X,Y on the screen and by color and followε a bit chain of deviations specifying the position or the direction of the subsequent point of the outline edge that delimits the area of one color or of one color gradient. The chain fractal compression consists in that similar chains are saved only once in memory and the remaining occurrences reference to said chains specifying position, size and angle parameters. The trimming buffer consists in creating a list of lines and in them a list of the right edge and the left edge points that merge, whereby a line list of no -continuous occupied sections is created and during every point entry a question is raised whether it is not placed in the occupied section. If yes, the left edge is cut off. The facets are drawn and classified from the front side. All edges - items of information - about the initial point, direction and repeating are entered into the erasing buffer, wherefrom they are read and drawn into the video memory by the repeater color during erasing.
Brief Description of the Drawings
To help understanding of this invention drawings are attached, whereby Figure 1 is a block diagram of one embodiment of the filling accelerator. Figure 2 shows a analog integrator of color components and Figure 3 is a digital modification. Figure 4 shows an example of the chaining compression format.
Example of the Invention Embodiment
The invention can be realized as an external additional device attached to the graphic card. In case of the VGA graphic card the VGA feature connector can be used having an output of the logic color from the video processor, use another RAMDAC palette circuit and an analog integrator. Eventually the whole device can be reduced to color registers and direct D/A converters. Preferably, the whole invention can be incorporated and realized within the RAMDAC circuit. In thiε case a digital integrator of better quality can be used. Eventually, some of the real color modes HiColor or TrueColor can be used. In this case, it is also more advantageous to use digital integrators and 8 bit converters for every color component. It is also possible to assign properties to each logic color if it repeats, if it is integrated, if there is brightness or texture and with what parameters, eventually at what level.
The Figure 1 shows an example of the filling accelerator embodiment which is incorporated between the video processor output 1 and the RAMDAC input 3_ of the palette D/A converter. The accelerator is comprised of a logic member _, which in case of the repeater 255 (FFh) presence stopε through the gate ϋ the clock signal PCLK entering data into the D regiεter 2- At the time when there is number 255, repeater, at the output of the video processor, there are the latest data items at the input of the RAMDAC 3_ before beginning the sequence with the number 255. Therefore, color of the latest edge in the line drawing direction by a beam is displayed. If the accelerator is created from programmable components or directly on a chip, it is preferable to use other number as the repeater, e.g. COH, because of compatibility with Windows.
The Figure 2 shows a simplified modification of the analog integrator of one of the three RGB color components. The integrators are connected between the RAMDAC and the monitor. If it does not integrate, the analog switch 1 is switched on and the ε all capacity of the capacitor C 3 iε fed by a hard signal source. During integration, the analog switch is switched off and the voltage of the capacitor C 3 is integrated through the resistor R 2 up to the voltage value at the input for the time determined by the RC constant. The emitter follower with transistor T. 4_ only adapts the load resistor between the monitor and the integrator. The simplicity of this diagram is counterbalanced by non-linearity of the capacitor charging rate that is exponential.
Figure 3 shows an example of the digital integrator where it is possible to reach sufficient linearity and edge sharpness with eight-bit converter. In addition, it is possible to the change integration time simply and eventually to continue in the integration with the given gradient further, up to the minimal intensity of the given RGB color component. If the edge is not integrated then its color - color component - is entered through the multiplexor 2 to the register 2 and is displayed on monitor through the D/ converter 6_. If the data items bear an attribute of integration and the edge is integrated, then the difference between the previous and the current edge is carried out through the multiplexor 3_ in the subtracter 5_ and it is entered into the register 4,. In the register 4. the value is packed, separated in binary form in accordance to what distance it will be integrated. In the subsequent cycles the negative difference from the register is subtracted from the existing data from the register 2. in the subtracter 5_ and is entered into register 2 through multiplexor 1 as new data items. The integration is terminated if a color component at the input level is reached, what is found by the compilator 1, or if the maximum or the minimum value is reached. The integration attribute can be in data, e.g. some bit specifies a group of the integration colors or can be saved in the palette.
The Figure 4 shows an example of data storage during the chained outline compression, where X,Y is the position of the chain introduction followed by a bitε chain of differences of the subsequent pixels which creates the outline edge. The so stored data itemε take minimum place in memory and enable that the central processor or the simple graphic accelerator rapidly unpacks a large quantity of information about the image. For example, if it is a two-bits chain it is the operation of adding or subtracting one. The chain can have a different, pre-determined number of bitε. The differences can be absolute or relative, the chains can grow into different directions or they can be limited to a direction, e.g. from above downwards, they can contain in the end a terminator or they can have a determined number N of the chain linkε. Apart from shifting by changing the X,Y the chains can be transformed spherically, i.e. zoomed, rotated, and fractally associated, whereby in case of similar changes with attributes of transformation a reference can be made to such chains. This all can be done without any loss of the image quality and with high degree of compression of such image stored in memory.
Considering the number of bytes entered, it is preferable to operate in the mode of logic colors, but if colors absent in the pallete are to be displayed the mix mode can be used. In this mode the pixel display runs in the logic color mode, but the filling accelerator runs in the real color mode, whereby two (HiColor) or three (TrueColor) subsequent bytes are considered as a real color and the following one or two bytes have to be repeated. In this case color is stored in series in the video memory, whereby memory capacity is saved.
To simplify the calculation of visibility several integrators can be grouped that represent levels and the higheεt non-zero one is displayed. The highest non-zero (zero correspondε to black - transparent level) integrator is connected to the output D/A converter via a multiplexor. Colors are entered into integrators according to their respective level numbers, that are saved in the pallete registers or directly in the data items. Tranε er to a higher level (nearer to the observer) is carried out by recording this color into this higher level and transfer to a lower level (the right outline of the object) by recording of zero - black - on thiε level, eventually by recording the same number - reset - on this level. During recording into the pixel field it is necessary to guard that the edge is not overwritten. If there is a crossing then the edge of higher level is stored and the edge of lower level is stored in the subsequent pixel to the right. To increase the number of colors in the 256 color mode it is possible for example to divide this palette into four blocks that aree also levels, with 64 logic colors, whereby e.g. one block representε 64 brightnesses and the other block 64 colors and by multiplying we obtain more than 4000 shades. The separation of both components can be used preferably for independent drawing, whereby the brightness represents angle of the facet to the light source and color represents vectorized broad texture. Another block can be used aε a level in the foreground for sprite fractal graphics and texts and another block for fine textures.
Minute textures, associated e.g. to the upper quarter of logic colors, can represent independent levels that overlap upwards and information about what color or brightness bits are inverted, about zoom, repeating the texture bits and about the bit form itself of the texture is saved in memory which was originally allocated to the RGB color components. The texture is then repeatedly displayed till this level is finished whereby visibility of the texture with the highest number is ensured. Or in direct mode the number of logic color carries the information about ground color or brightnesε modulation and about the zoom εize directly and the immediately following bytes contain εerial bite εhape of the texture. Repeating of thiε texture can be finiεhed by recording the brightness, color or of an empty texture. Big textures are convenient to create as vectorized.
The cutting and erasing buffer can be created both by software and hardware. In case of the cutting buffer a list of occupied lines is formed in memory and thiε liεt makeε a reference to a list of points of the right and the left edges, that merge and so a list of non-continuous occupied sections is formed. By merging the sectionε the number of comparisonε iε continuously diminished. As the buffer is small it remains in the cash memory and runs quickly. During every point input a question is raised whether it is not situated in the occupied section. If not, it is displayed, if yes it is cut off shifted to the right to the end of the buffer, if it iε within the limits of the displayed facet. The facets are displayed and sorted beginning with the front side. The cutting buffer can be a two-level one, whereby the first level represents a quick εegment buffer having the occupied εegments marked (segment 8x8, 16x16 pixels) . All edges - information about the starting point, gradient and repeating are recorded in the erasing buffer, wherefrom they are read and drawn into the video memory by the repeater color during erasing.
Industrial Use
The filling accelerator can be used for all computer systems, preferably for personal computers (PC) whereby it makes possible to use graphics in the same way as it is in case of the graphic working stations. It is an enhancement mainly in softwares for CAD visualizationε, DTP and computer gameε that depend mainly on the hardware speed. Moreover, the high data compression, if the fractal compression is used, makes possible to store much longer image sequences in the memory medium at high image quality and the possibility to connect shutter 3D spectacles makeε possible to create sceneε of virtual reality.

Claims

C 1 a i m ε
1. Filling accelerator which uses a pixel display in the mode where each pixel correspondε to one byte in the video memory and can acquire valueε 0 to 255 of a logic color, addreεεing pallete register, eventually in the real address mode, characterized in that one number, preferably 255 (FFh) represents a repeater which repeats the previous color - number in the direction of displaying the screen line and during drawing of the image the screen is erased (filled) by the repeater 255 at first and thereafter the left outlineε of objectε are drawn and only said outlines can be erased by number 255 during erasing.
2. Filling accelerator which uses a pixel display in the mode of logic colors where one pixel correεpondε to one byte, characterized in that the video memory contains real colors saved in a series one after another, in two bytes HiColor or in three bytes True Color where a color can be saved on any pixel but the following one or two bytes have to be repeated.
3. Color holding register which is inεerted between the data pixel output from the video proceεεor and a D/A converter or a RAMDAC palette converter, characterized in that the data output from the video proceεεor is connected to a logical member which in case of output of a chosen number, preferably 255 (FFh), stops the clock signal, entering said pixel data into the register, whereby the previouε number (color) remainε in the register output for the time the chosen number is being repeated.
4. Color interpolation between edges for increasing the picture quality characterized in that in the direction of the beam running the previous edge specifieε the initial color and the actual edge with an integration attribute specifies the color into which it will be integrated for a certain time - determined distance, and the color intensity of the actual edge therefore determines the rate of integration and the integration is finished when the specified color has been reached or by an interruption by the following edge, eventually by reaching the white or the black color.
5 Individual integrators of the color components R G B, characterized in that the analog alternative is comprised of an analog switch switching on integration on a capacitor in the presence of an integration attribute in data or the digital one which is comprised of an adder with an accumulator adding the difference between the previous and the current edge, packed by so many binary orders aε is the global distance for which the color is interpolated.
6. To make the visibility calculation more easy there are such integrators that are characterized in that several integrators, representing individual levels are connected so that always the highest non-zero one (zero corresponds to black - transparent level) is connected to the output D/A converter through the multiplexer, whereby the colors are entered into the integrators according to their level numberε that are εtored in the palette registers or directly in data and the transfer to the higher level (nearer to the observer) is carried out by entering the color into this higher level and the transition to the lower level (the right object edge) is carried out by entering zero, i.e. black, into this level, eventually by entering the same number - reset into this level.
7. The increase in number of colors in the mode of 256 colors per pixel, characterized in that there are two or more levels - individual color registers, and colors of said levels are mixed, preferably by multiplying the brightness component of one level, representing turning angle of the facet to the light source, with the color component from the other level, representing the surface texture of the facet.
8. Minute textures characterized in that each texture assigned to a logic color represents a level, whereby such levels overlap each other ascendantly, and each texture uses multilevel mixing with a color or brightness at the same time, by their modulation of serially read bites zoomable - N-times repeated, parallelly saved immediately after the texture activator and by repeating of the texture up to the end at this level.
9. The outline chaining compression, characterized in that the beginning of the outline edge is defined as an entry point by the position X,Y on the screen and by color and that it is followed by a bitε chain of deviations specifying the poεition or the direction of the εubεequent point of the outline edge that marks the area of one color or of one gradient of color whereby the chain fractal compression than means that similar chains are saved in memory only once and the remaining occurrences reference to εaid chains specifying position, εize and angle parameterε.
10 The cutting and erasing buffer characterized in that in case of the cutting buffer it createε a list of lines and in them a list of the right edge and the left edge points that merge, whereby a line list of non-continuous occupied εectionε is created and in every point entry a question is raised whether it is not placed in the occupied section, and if it is, the left edge is cut off and the facets are drawn and classified from the front side and all edges - items of information about the initial point, direction and repeating are entered into the erasing buffer, wherefrom they are read and drawn into the video memory by the repeater color during erasing.
PCT/CZ1996/000025 1995-12-19 1996-12-19 Apparatus for filling an image WO1997022950A1 (en)

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CZ953377A CZ337795A3 (en) 1995-12-19 1995-12-19 Method of representation by filling accelerator and the filling accelerator per se
CZPV3377-95 1995-12-19

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4988985A (en) * 1987-01-30 1991-01-29 Schlumberger Technology Corporation Method and apparatus for a self-clearing copy mode in a frame-buffer memory
US5357605A (en) * 1988-09-13 1994-10-18 Microsoft Corporation Method and system for displaying patterns using a bitmap display
EP0635818A1 (en) * 1993-06-30 1995-01-25 Microsoft Corporation Method and apparatus for efficient transfer of data to memory
WO1995024032A1 (en) * 1994-03-02 1995-09-08 Vlsi Technology, Inc. Method and apparatus for simultaneously minimizing storage and maximizing total memory bandwidth for a repeating pattern

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4988985A (en) * 1987-01-30 1991-01-29 Schlumberger Technology Corporation Method and apparatus for a self-clearing copy mode in a frame-buffer memory
US5357605A (en) * 1988-09-13 1994-10-18 Microsoft Corporation Method and system for displaying patterns using a bitmap display
EP0635818A1 (en) * 1993-06-30 1995-01-25 Microsoft Corporation Method and apparatus for efficient transfer of data to memory
WO1995024032A1 (en) * 1994-03-02 1995-09-08 Vlsi Technology, Inc. Method and apparatus for simultaneously minimizing storage and maximizing total memory bandwidth for a repeating pattern

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