WO1997014214A1 - Compensated delay locked loop timing vernier - Google Patents
Compensated delay locked loop timing vernier Download PDFInfo
- Publication number
- WO1997014214A1 WO1997014214A1 PCT/US1996/015894 US9615894W WO9714214A1 WO 1997014214 A1 WO1997014214 A1 WO 1997014214A1 US 9615894 W US9615894 W US 9615894W WO 9714214 A1 WO9714214 A1 WO 9714214A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- delay
- reference signal
- periodic
- input
- Prior art date
Links
- 230000001934 delay Effects 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 5
- 230000004044 response Effects 0.000 claims description 2
- 230000000737 periodic effect Effects 0.000 claims 30
- 239000003990 capacitor Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 230000007423 decrease Effects 0.000 description 9
- 239000000872 buffer Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31922—Timing generation or clock distribution
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
Definitions
- the present invention relates in general to timing signal generators and in particular to a timing vernier for generating a set of timing signals that are evenly distributed in phase with respect to a reference clock signal.
- a timing vernier produces a set of timing signals of similar frequency and evenly distributed in phase by passing an input reference clock signal through a succession of delay stages, each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage.
- the reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller through separate adjustable first and second delay circuits.
- the phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock.
- the delays of the first and second delay circuits may be adjusted to compensate for controller phase lock error. It is accordingly an object of the invention to provide a timing vernier for producing a set of timing signals that are evenly distributed in phase and which evenly divide the period of a reference clock signal into several intervals.
- FIG. 2 illustrates the phase lock controller of FIG. 1 in more detailed block diagram form
- FIG. 9 illustrates the PBIAS generator circuit of FIG. 7 is schematic diagram form
- the reference clock signal CLK is applied as input to a delay chain 12 consisting of a set of N similar delay stages SI- SN connected in series.
- Stage SI receives as its input the reference clock signal CLK and produces as its output timing signal Tl by delaying the reference clock signal.
- Each subsequent stage S2-SN produces a corresponding output timing signal T2-TN by delaying the timing signal output Tl-T(N-l) of the preceding delay stage.
- Each delay stage Sl-SN delays its input signal by a similar amount of time.
- a phase lock controller 14 adjusts the delay time with a control signal Cl applied to all stages.
- Each stage Sl-SN may, for example, be an inverter or other logic element having a switching speed controlled by the magnitude of Cl which acts as the inverter power supply.
- Phase lock controller 14 receives a delayed version CLK_D of the reference clock signal CLK produced by an adjustable delay circuit 16. Controller 14 also receives a delayed version TN_D of the TN timing signal output of stage SN via another adjustable delay circuit 18. Phase lock controller 14 adjusts the Cl signal so that timing signal TN_D is substantially phase locked to the reference clock signal CLK_D. When CLK leads TN_D, phase lock controller 14 alters Cl so as to decrease the delay in stages Sl-SN. When the TN_D signal leads CLK_D, phase lock controller 14 alters Cl so as to increase the delay in stages Sl-SN. If the delays of delay circuits 16 and 18 are similar, and if TN_D is precisely phase locked to CLK_D, then TN will be phase locked to CLK. In such case timing signals Tl-TN will be evenly distributed in phase and leading edges of signals Tl-TN evenly divide the period of the reference clock signal into N intervals.
- transistors Q13 and Q5 are similar in size and are both controlled by NBIAS. Thus since the drop across transistor Qll is 1/4 VDD, the drop across transistor Ql must also be 1/4 VDD and 0UT_ is at 3/4 VDD. Transistor Q2, also active, pulls OUT near VDD. When IN/IN_ changes state, transistor Q4 turns on and transistor Q3 turns off. OUT falls to 3/4 VDD while 0UT_ rises to near VDD.
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96936179A EP0855102B1 (en) | 1995-10-13 | 1996-10-04 | Compensated delay locked loop timing vernier |
DE69630041T DE69630041T2 (en) | 1995-10-13 | 1996-10-04 | TIMING REGENERATORS USING A COMPENSATED DELAY CONTROL LOOP |
JP51510397A JP3770619B2 (en) | 1995-10-13 | 1996-10-04 | Compensated delay lock loop / timing vernier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/542,518 US5684421A (en) | 1995-10-13 | 1995-10-13 | Compensated delay locked loop timing vernier |
US08/542,518 | 1995-10-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997014214A1 true WO1997014214A1 (en) | 1997-04-17 |
Family
ID=24164167
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/015894 WO1997014214A1 (en) | 1995-10-13 | 1996-10-04 | Compensated delay locked loop timing vernier |
Country Status (6)
Country | Link |
---|---|
US (1) | US5684421A (en) |
EP (1) | EP0855102B1 (en) |
JP (1) | JP3770619B2 (en) |
KR (1) | KR100403694B1 (en) |
DE (1) | DE69630041T2 (en) |
WO (1) | WO1997014214A1 (en) |
Cited By (9)
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KR100403694B1 (en) * | 1995-10-13 | 2004-03-20 | 크레던스 시스템스 코포레이션 | Compensated Delay Locked Loop Timing Vernier |
US7173459B2 (en) | 2004-12-22 | 2007-02-06 | Agere Systems Inc. | Trimming method and apparatus for voltage controlled delay loop with central interpolator |
US7190198B2 (en) | 2004-11-30 | 2007-03-13 | Agere Systems Inc. | Voltage controlled delay loop with central interpolator |
US7212048B2 (en) | 2005-05-26 | 2007-05-01 | Agere Systems Inc. | Multiple phase detection for delay loops |
US7236037B2 (en) | 2005-05-26 | 2007-06-26 | Agere Systems Inc. | Alternating clock signal generation for delay loops |
US7848473B2 (en) | 2004-12-22 | 2010-12-07 | Agere Systems Inc. | Phase interpolator having a phase jump |
US7924074B2 (en) | 2007-12-20 | 2011-04-12 | Renesas Electronics Corporation | Delay control circuit and delay control method |
US8067966B2 (en) | 2004-11-30 | 2011-11-29 | Agere Systems Inc. | Voltage controlled delay loop and method with injection point control |
US8407511B2 (en) * | 2008-08-28 | 2013-03-26 | Agere Systems Llc | Method and apparatus for generating early or late sampling clocks for CDR data recovery |
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US6239627B1 (en) * | 1995-01-03 | 2001-05-29 | Via-Cyrix, Inc. | Clock multiplier using nonoverlapping clock pulses for waveform generation |
TW378289B (en) * | 1995-10-20 | 2000-01-01 | Matsushita Electric Ind Co Ltd | Phase adjusting circuit, system including the same and phase adjusting method |
JP3688392B2 (en) * | 1996-05-31 | 2005-08-24 | 三菱電機株式会社 | Waveform shaping device and clock supply device |
JPH10171774A (en) * | 1996-12-13 | 1998-06-26 | Fujitsu Ltd | Semiconductor integrated circuit |
US6002281A (en) * | 1998-02-20 | 1999-12-14 | Intel Corporation | Delay locked loop |
US6160434A (en) * | 1998-05-14 | 2000-12-12 | Mitsubishi Denki Kabushiki Kaisha | Ninety-degree phase shifter |
US6137334A (en) | 1998-07-06 | 2000-10-24 | Micron Technology, Inc. | Logic circuit delay stage and delay line utilizing same |
DE19830571C2 (en) | 1998-07-08 | 2003-03-27 | Infineon Technologies Ag | Integrated circuit |
KR100272167B1 (en) * | 1998-07-13 | 2000-11-15 | 윤종용 | Reference signal generating circuit & sdram having the same |
KR100301043B1 (en) * | 1998-08-08 | 2001-09-06 | 윤종용 | Phase comparator in DLL & method for delay locking |
DE19845121C1 (en) * | 1998-09-30 | 2000-03-30 | Siemens Ag | Integrated circuit with adjustable delay units for clock signals |
GB2376821B (en) * | 1998-12-30 | 2003-04-09 | Hyundai Electronics Ind | Delayed locked loop clock generator using delay-pulse-delay |
US6777995B1 (en) * | 1999-02-26 | 2004-08-17 | Micron Technology, Inc. | Interlaced delay-locked loops for controlling memory-circuit timing |
US6229364B1 (en) | 1999-03-23 | 2001-05-08 | Infineon Technologies North America Corp. | Frequency range trimming for a delay line |
US6252443B1 (en) * | 1999-04-20 | 2001-06-26 | Infineon Technologies North America, Corp. | Delay element using a delay locked loop |
US6646953B1 (en) | 2000-07-06 | 2003-11-11 | Rambus Inc. | Single-clock, strobeless signaling system |
US6321282B1 (en) | 1999-10-19 | 2001-11-20 | Rambus Inc. | Apparatus and method for topography dependent signaling |
US7051130B1 (en) | 1999-10-19 | 2006-05-23 | Rambus Inc. | Integrated circuit device that stores a value representative of a drive strength setting |
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US7061941B1 (en) * | 2000-11-28 | 2006-06-13 | Winbond Electronics Corporation America | Data input and output circuits for multi-data rate operation |
US7079775B2 (en) | 2001-02-05 | 2006-07-18 | Finisar Corporation | Integrated memory mapped controller circuit for fiber optics transceiver |
US6535038B2 (en) * | 2001-03-09 | 2003-03-18 | Micron Technology, Inc. | Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices |
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US6850107B2 (en) | 2001-08-29 | 2005-02-01 | Micron Technology, Inc. | Variable delay circuit and method, and delay locked loop, memory device and computer system using same |
US6621314B2 (en) * | 2001-09-25 | 2003-09-16 | Intel Corporation | Delay locked loop |
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US7135903B2 (en) * | 2002-09-03 | 2006-11-14 | Rambus Inc. | Phase jumping locked loop circuit |
US6922091B2 (en) | 2002-09-03 | 2005-07-26 | Rambus Inc. | Locked loop circuit with clock hold function |
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US6759881B2 (en) | 2002-03-22 | 2004-07-06 | Rambus Inc. | System with phase jumping locked loop circuit |
US6580304B1 (en) | 2002-03-28 | 2003-06-17 | M/A-Com, Inc. | Apparatus and method for introducing signal delay |
US6853231B2 (en) * | 2003-03-31 | 2005-02-08 | Mosaid Technologies Incorporated | Timing vernier using a delay locked loop |
US6812760B1 (en) * | 2003-07-02 | 2004-11-02 | Micron Technology, Inc. | System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits |
US7149145B2 (en) * | 2004-07-19 | 2006-12-12 | Micron Technology, Inc. | Delay stage-interweaved analog DLL/PLL |
US7078950B2 (en) * | 2004-07-20 | 2006-07-18 | Micron Technology, Inc. | Delay-locked loop with feedback compensation |
US20060095221A1 (en) * | 2004-11-03 | 2006-05-04 | Teradyne, Inc. | Method and apparatus for controlling variable delays in electronic circuitry |
US7561653B2 (en) * | 2005-07-01 | 2009-07-14 | Agere Systems Inc. | Method and apparatus for automatic clock alignment |
US7671647B2 (en) * | 2006-01-26 | 2010-03-02 | Micron Technology, Inc. | Apparatus and method for trimming static delay of a synchronizing circuit |
JP5183269B2 (en) * | 2008-03-28 | 2013-04-17 | 株式会社アドバンテスト | Vernier delay circuit, time digital converter and test apparatus using the same |
KR100963112B1 (en) * | 2008-07-09 | 2010-06-15 | 한양대학교 산학협력단 | Intra-pair skew compensation method for high-speed serial communication and intra-pair skew compensation circuit using the same |
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US8779815B2 (en) | 2012-06-25 | 2014-07-15 | Intel Corporation | Low power oversampling with delay locked loop implementation |
US8797075B2 (en) * | 2012-06-25 | 2014-08-05 | Intel Corporation | Low power oversampling with reduced-architecture delay locked loop |
US10161967B2 (en) | 2016-01-09 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | On-chip oscilloscope |
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US4652778A (en) * | 1982-10-20 | 1987-03-24 | Sanyo Electric Co., Ltd. | I2 L delay circuit with phase comparator and temperature compensator for maintaining a constant delay time |
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US5146121A (en) * | 1991-10-24 | 1992-09-08 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
US5336940A (en) * | 1992-08-07 | 1994-08-09 | Vlsi Technology, Inc. | Delay-compensated output pad for an integrated circuit and method therefor |
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-
1995
- 1995-10-13 US US08/542,518 patent/US5684421A/en not_active Expired - Lifetime
-
1996
- 1996-10-04 KR KR10-1998-0702710A patent/KR100403694B1/en not_active IP Right Cessation
- 1996-10-04 WO PCT/US1996/015894 patent/WO1997014214A1/en active IP Right Grant
- 1996-10-04 JP JP51510397A patent/JP3770619B2/en not_active Expired - Fee Related
- 1996-10-04 DE DE69630041T patent/DE69630041T2/en not_active Expired - Fee Related
- 1996-10-04 EP EP96936179A patent/EP0855102B1/en not_active Expired - Lifetime
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100403694B1 (en) * | 1995-10-13 | 2004-03-20 | 크레던스 시스템스 코포레이션 | Compensated Delay Locked Loop Timing Vernier |
US7190198B2 (en) | 2004-11-30 | 2007-03-13 | Agere Systems Inc. | Voltage controlled delay loop with central interpolator |
US8067966B2 (en) | 2004-11-30 | 2011-11-29 | Agere Systems Inc. | Voltage controlled delay loop and method with injection point control |
US7173459B2 (en) | 2004-12-22 | 2007-02-06 | Agere Systems Inc. | Trimming method and apparatus for voltage controlled delay loop with central interpolator |
US7848473B2 (en) | 2004-12-22 | 2010-12-07 | Agere Systems Inc. | Phase interpolator having a phase jump |
US7212048B2 (en) | 2005-05-26 | 2007-05-01 | Agere Systems Inc. | Multiple phase detection for delay loops |
US7236037B2 (en) | 2005-05-26 | 2007-06-26 | Agere Systems Inc. | Alternating clock signal generation for delay loops |
US7924074B2 (en) | 2007-12-20 | 2011-04-12 | Renesas Electronics Corporation | Delay control circuit and delay control method |
US8407511B2 (en) * | 2008-08-28 | 2013-03-26 | Agere Systems Llc | Method and apparatus for generating early or late sampling clocks for CDR data recovery |
Also Published As
Publication number | Publication date |
---|---|
JPH11513847A (en) | 1999-11-24 |
KR100403694B1 (en) | 2004-03-20 |
DE69630041T2 (en) | 2004-07-08 |
US5684421A (en) | 1997-11-04 |
JP3770619B2 (en) | 2006-04-26 |
EP0855102A4 (en) | 1999-05-12 |
KR19990064224A (en) | 1999-07-26 |
EP0855102B1 (en) | 2003-09-17 |
EP0855102A1 (en) | 1998-07-29 |
DE69630041D1 (en) | 2003-10-23 |
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