WO1997012399A1 - Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions - Google Patents

Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions Download PDF

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Publication number
WO1997012399A1
WO1997012399A1 PCT/US1996/015351 US9615351W WO9712399A1 WO 1997012399 A1 WO1997012399 A1 WO 1997012399A1 US 9615351 W US9615351 W US 9615351W WO 9712399 A1 WO9712399 A1 WO 9712399A1
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WO
WIPO (PCT)
Prior art keywords
layer
titanium
metal stack
approximately
stack
Prior art date
Application number
PCT/US1996/015351
Other languages
French (fr)
Inventor
Rajiv Rastogi
Peng Bai
Sohail Ahmed
William K. Meyer
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to KR1019980702234A priority Critical patent/KR19990063767A/en
Priority to JP9512195A priority patent/JPH11511593A/en
Priority to IL12375196A priority patent/IL123751A0/en
Priority to EP96933891A priority patent/EP0852809A4/en
Priority to AU72453/96A priority patent/AU7245396A/en
Publication of WO1997012399A1 publication Critical patent/WO1997012399A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to metal stacks used for interconnecting structures in integrated circuits.
  • Modem integrated circuits often include millions of active and passive devices such as transistors, capacitors and resistors formed on a semiconductor substrate such as silicon. These devices, when initially fabricated, are isolated from one another on the substrate and are later interconnected to form functional circuits. The quality of these interconnecting structure drastically effects the performance and the reliability of the completed integrated circuit. Interconnections are increasingly determining the limits of performance and densities in modern ultra large scale integrated (ULSI) circuits.
  • ULSI ultra large scale integrated
  • the interconnecting structure is fabricated from a metal stack which may include a base layer, bulk conductor layer and/or capping layer.
  • the stack is formed on a dielectric layer generally by sputtering and then through use of photolithographic techniques is etched to define the interconnecting structure.
  • multiple levels of interconnecting structures are used, for example, four layers of metal stacks may be used, each insulated from one another by a interlayer dielectric (ILD). More often than not, aluminum and aluminum alloys are used as the bulk conductor in metal stacks.
  • ILD interlayer dielectric
  • Electromigration is a significant reliability problem for these thin- film conductors;.
  • Aluminum due to its low melting point, is more susceptible to electromigration than are other metals.
  • atoms are transported and vacancies are generated at grain boundaries which coalesce into a network of voids. Void nucleation often occurs at the intersection of grain boundaries and conductor sidewalls.
  • aluminum-copper alloys selected boundaries remain intact, presumably where they are hardened by copper-rich planar precipitates, resulting in voids with several sharply defined edges. These variously shaped voids continue to enlarge until an open circuit terminates the process.
  • Refractory metals are often used in conjunction with aluminum alloys to provide shunting layers, that is, an electrical path even in the presence of these voids.
  • titanium and titanium nitride layers are sometimes used as shunting layers.
  • Figure 1 shows one prior art metal stack used for an interconnecting structure.
  • the metal stack is formed on an interlayer dielectric (ILD) 10.
  • the bulk conductor 1 1 comprises an aluminum-copper alloy layer 1 1.
  • the thickness of this layer varies depending upon the current that the layer is required to carry; a typical layer may be 350 ⁇ A thick.
  • a layer of titanium nitride (TiN) is formed on the upper surface of the layer 1 1.
  • This layer in the prior art stack described in Figure 1 is approximately 370A thick.
  • a layer 13 of titanium approximately 100 ⁇ A thick is sputtered on to the upper surface of layer 12.
  • an anti-reflective coating (ARC) 14 is formed on the upper surface of layer 13.
  • This coating is 370A thick for the prior art example shown in Figure 1.
  • Figure 2 shows another prior art metal stack used for an interconnecting structure which is formed on an ILD 20.
  • a base layer 21 of titanium approximately 1000A thick is formed on the ILD 20.
  • an aluminum-copper alloy layer 22 is formed on the upper surface of titanium layer 21.
  • the thickness of this layer is, as before, determined by the amount of current that the layer is required to carry (e.g., 6000A to 12000A thick).
  • An ARC 23 is formed on the upper surface of layer 22. Again layer 23 comprises a coating of TiN 370A thick
  • the present invention provides a different stack than those shown in Figures 1 and 2.
  • the newly disclosed metal stack has been found to have superior qualities and, in particular, improved electromigration performance over the metal stacks shown in Figures 1 and 2
  • the stack includes a thin base layer of titanium which, is approximately between 125A and 200A thick
  • a bulk conductor layer is formed on the upper surface of the base layer
  • this layer comprises an aluminum-copper alloy
  • a capping layer of titanium approximately between 125A to 200A thick is formed on the upper surface of the bulk conductor layer
  • An anti-reflective coating of titanium nitride is formed on the upper surface of the capping layer
  • Figure 1 is a cross sectional elevation view of a prior art metal stack used for an interconnecting structure in an integrated circuit
  • Figure 2 is a cross sectional elevation view of another prior art metal stack used for an interconnecting structure in an integrated circuit
  • Figure 3 is a cross sectional elevation view of a metal stack fabricated in accordance with the present invention
  • Figure 4 is a cross sectional elevation view of two metal stacks formed in accordance with the present invention.
  • Figure 5 is a plan view of a sputter system used to fabricate the metal stacks of Figures 2 and 3 showing the sequence of wafer movement.
  • Figure 6 is a process flow diagram illustrating the steps used to fabricate the metal stack of the present invention
  • the present invention describes a novel metal stack for use as an interconnecting structure in an integrated circuit
  • numerous specific details are set forth, such as specific materials, processes and equipment in order to provide a thorough understanding of the present invention It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details
  • well-known manufacturing materials, processes and equipment are not set forth in detail in order not to unnecessarily obscure the present invention
  • the metal stack 35 of the present invention is formed on an ILD layer such as ILD 30
  • ILD 30 an ILD layer
  • well-known photolithographic techniques are used to mask the stack and to etch away portions of the stack so as to form the interconnecting structures as will be discussed
  • Vias are used to provide conductive paths between different levels of metal stacks and between the stacks and substrate regions
  • One via for use with the metal stack of the present invention is described in a co- pending application entitled “A Novel Via Hole Profile and Method of Fabrication", serial no 327,763, filed October 17, 1994 assigned to the Assignee of the present invention
  • the stack 35 illustrated in Figure 3 includes a base layer 31 of titanium which is sputtered in a dedicated chamber onto the ILD layer 30 While titanium is preferred, other refractory metals may be used for this thin layer This shunting layer may be approximately between 125A and 20 ⁇ thick, although 185A is preferred
  • a bulk conductor layer 32 which, in one embodiment ,uses an aluminum-copper alloy having approximately 0 5% copper is in contact with the upper surface of the base layer 31
  • an aluminum alloy layer is preferred because of its low resistivity and its well-known processes, it is to be appreciated that other low resistance materials may act as the bulk conductor.
  • the thickness of the layer 32 is selected as a function of the amount of current that the layer 32 will carry. As will be described in conjunction with Figure 4, the thickness of this layer may be different in one level compared to another in a given integrated circuit. Typical values for the thickness of layer 32 range between approximately 5000A to 20,000A thick.
  • a thin capping layer 33 of titanium is formed in contact with the upper surface of the layer 32.
  • Layer 33 is sputtered titanium, in a dedicated chamber, preferably approximately 185A thick in the preferred embodiment. However, this layer may be approximately between 125A to 200A thick. Again, as in the case of layer 31 other refractory materials may be used for layer 33.
  • ARC anti-reflective coating
  • TiN titanium nitride
  • TiAl3 titanium aluminide
  • 185A of Ti will react with 525A of AICu alloy and result in the formation of approximately 67 ⁇ A of the TiAl3 layer.
  • Performance measurements were compared for the metal stack shown in Figure 3 and the prior art stacks shown in Figures 1 and 2.
  • the metal stacks of Figure 3 perform better in such areas as via resistance, metal undercutting, voiding, and sheet resistance.
  • the stack of Figure 3 proved to be as manufacturable as the prior art stacks.
  • the electromigration performance as measured by defect density for the stack of Figure 3 was found to be unexpectedly high when compared to the prior art stacks of Figures 1 and 2.
  • the stack of Figure 3 is used at a plurality of different levels. This is partially shown in the cross section of Figure 4.
  • a first metal stack 40 is formed on the ILD 43.
  • the stack 40 is separated from a second metal stack 42 by an ILD 41 .
  • Another ILD is formed on the stack 42 and may support an additional metal stack.
  • the stack 40 is patterned into an interconnecting structure using well-known photolithography and etch processes. Any well-known etching techniques such as reactive ion etching (RIE) with a chemistry comprising BCI3 and CI2 can be used to pattern the stack 40 to form the interconnecting structure.
  • RIE reactive ion etching
  • an ILD 41 is formed over the pattern stack 40 using well-known chemical vapor deposition (CVD). For instance, a doped silicon dioxide layer is deposited to a thickness of approximately 10.000A. Also, as is well-known, the layer 41 is planarized using chemical etching or chemical-mechanical polishing to form a planar surface upon which the stack 42 may be formed.
  • CVD chemical vapor deposition
  • the stack 42 is then formed on the ILD 41 in the same manner as used to form the stack 35. Intermediate cleaning, via contact processing steps and other well-known steps have not been described.
  • the stacks 40 and 42 each may be identical to the stack 35 of Figure 3 except that the thickness of the bulk conductor layer may vary.
  • the stack 40 comprises a thin base layer of titanium 44 having a thickness in the preferred embodiment of approximately 185A.
  • a bulk conductive layer 45 may have a thickness of, for example, 540 ⁇ A.
  • the thin capping titanium layer 46 which, in the preferred embodiment, has a thickness of approximately 185A is formed over the layer 45.
  • the ARC coating 47 is then formed on the layer 46.
  • the stack 42 is formed beginning with the base layer 48 of approximately 185A of titanium.
  • the bulk conductor layer 49 of aluminum-copper alloy which may be thicker for the stack 42 (e.g., 740 ⁇ A) is formed on layer 48.
  • the second thin titanium capping layer 50 is formed on layer 49 (approximately 185A thick).
  • another ARC coating 50 is formed on the layer 50 for the patterning of the stack 42.
  • the metal stack of the present invention is formed using a commercially available cluster sputtering apparatus such as an AMAT 5500, Endura Sputter System.
  • cluster sputtering apparatus such as an AMAT 5500, Endura Sputter System.
  • Such systems include, as shown in Figure 5, a central region 60 equipped with a robotic arm allowing wafers to be moved from one chamber to another chamber, such as between chambers 61 , 62, 63 and 64.
  • Each of the chambers are separately controllable to allow different processing to occur in each of the chambers.
  • a wafer is first transported as shown at 66 to a chamber 61.
  • the base layer of titanium is first sputtered onto an ILD.
  • step 71 which follows the processing of the ILD 70.
  • the wafer is next moved to the chamber 63.
  • the bulk conductor such as aluminum-copper alloy is deposited on the base layer of titanium. This is shown in Figure 6 by the processing step 72.
  • the wafer is moved to the chamber 64 where the capping layer of titanium is formed over the bulk conductor layer. Again as currently preferred, this capping layer is approximately 185A thick.
  • the capping layer is shown in Figure 6 by the process step 73.
  • step 74 the ARC (TiN coating) is formed over the capping layer of titanium.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A metal stack (35) for use in an integrated circuit demonstrating improved electromigration properties. A base layer (31) of approximately 185Å of titanium is formed on an ILD followed by the formation of the bulk conductor layer (32) such as an aluminum-copper alloy layer. A capping layer (33) of approximately 185Å of titanium is formed on the bulk conductor layer (32). Finally, an antireflective coating (ARC) (34) of titanium nitride is formed on the capping layer (33).

Description

METAL STACK FOR INTEGRATED CIRCUIT HAVING TWO THIN
LAYERS OF TITANIUM WITH DFDICATED CHAMBER DEPOSITIONS
BACKGROUND OF THE INVENTION
1. Field of the Invention.
The invention relates to metal stacks used for interconnecting structures in integrated circuits.
2. Related Application
This application is related to co-pending application Serial No. 324,763, filed October 17, 1994, entitled "A Novel Via Hole Profile and Method of Fabrication", and assigned to the Assignee of the present application.
DESCRIPTION OF THE PRIOR ART
Modem integrated circuits often include millions of active and passive devices such as transistors, capacitors and resistors formed on a semiconductor substrate such as silicon. These devices, when initially fabricated, are isolated from one another on the substrate and are later interconnected to form functional circuits. The quality of these interconnecting structure drastically effects the performance and the reliability of the completed integrated circuit. Interconnections are increasingly determining the limits of performance and densities in modern ultra large scale integrated (ULSI) circuits.
Often the interconnecting structure is fabricated from a metal stack which may include a base layer, bulk conductor layer and/or capping layer. The stack is formed on a dielectric layer generally by sputtering and then through use of photolithographic techniques is etched to define the interconnecting structure. In current production processes, multiple levels of interconnecting structures are used, for example, four layers of metal stacks may be used, each insulated from one another by a interlayer dielectric (ILD). More often than not, aluminum and aluminum alloys are used as the bulk conductor in metal stacks.
Electromigration is a significant reliability problem for these thin- film conductors;. Aluminum, due to its low melting point, is more susceptible to electromigration than are other metals. As high currents pass through a conductor, atoms are transported and vacancies are generated at grain boundaries which coalesce into a network of voids. Void nucleation often occurs at the intersection of grain boundaries and conductor sidewalls. In aluminum-copper alloys selected boundaries remain intact, presumably where they are hardened by copper-rich planar precipitates, resulting in voids with several sharply defined edges. These variously shaped voids continue to enlarge until an open circuit terminates the process.
Refractory metals are often used in conjunction with aluminum alloys to provide shunting layers, that is, an electrical path even in the presence of these voids. As will be discussed in connection with Figures 1 and 2, titanium and titanium nitride layers are sometimes used as shunting layers.
Figure 1 shows one prior art metal stack used for an interconnecting structure. In Figure 1 the metal stack is formed on an interlayer dielectric (ILD) 10. The bulk conductor 1 1 comprises an aluminum-copper alloy layer 1 1. The thickness of this layer varies depending upon the current that the layer is required to carry; a typical layer may be 350θA thick. A layer of titanium nitride (TiN) is formed on the upper surface of the layer 1 1. This layer in the prior art stack described in Figure 1 is approximately 370A thick. Then a layer 13 of titanium approximately 100θA thick is sputtered on to the upper surface of layer 12. Following this an anti-reflective coating (ARC) 14 is formed on the upper surface of layer 13. This coating is 370A thick for the prior art example shown in Figure 1.
Figure 2 shows another prior art metal stack used for an interconnecting structure which is formed on an ILD 20. First, a base layer 21 of titanium approximately 1000A thick is formed on the ILD 20. Following this the bulk conductor, again an aluminum-copper alloy layer 22 is formed on the upper surface of titanium layer 21. The thickness of this layer is, as before, determined by the amount of current that the layer is required to carry (e.g., 6000A to 12000A thick). An ARC 23 is formed on the upper surface of layer 22. Again layer 23 comprises a coating of TiN 370A thick
As will be seen the present invention provides a different stack than those shown in Figures 1 and 2. The newly disclosed metal stack has been found to have superior qualities and, in particular, improved electromigration performance over the metal stacks shown in Figures 1 and 2
SUMMARY OF THE INVENTION An improved metal stack for use in an interconnecting structure of an integrated circuit is described The stack includes a thin base layer of titanium which, is approximately between 125A and 200A thick A bulk conductor layer is formed on the upper surface of the base layer In one embodiment this layer comprises an aluminum-copper alloy A capping layer of titanium approximately between 125A to 200A thick is formed on the upper surface of the bulk conductor layer An anti-reflective coating of titanium nitride is formed on the upper surface of the capping layer
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a cross sectional elevation view of a prior art metal stack used for an interconnecting structure in an integrated circuit
Figure 2 is a cross sectional elevation view of another prior art metal stack used for an interconnecting structure in an integrated circuit
Figure 3 is a cross sectional elevation view of a metal stack fabricated in accordance with the present invention
Figure 4 is a cross sectional elevation view of two metal stacks formed in accordance with the present invention
Figure 5 is a plan view of a sputter system used to fabricate the metal stacks of Figures 2 and 3 showing the sequence of wafer movement.
Figure 6 is a process flow diagram illustrating the steps used to fabricate the metal stack of the present invention
DETAILED DESCRIPTION OF THE PRESENT INVENTION The present invention describes a novel metal stack for use as an interconnecting structure in an integrated circuit In the following description numerous specific details are set forth, such as specific materials, processes and equipment in order to provide a thorough understanding of the present invention It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details In other instances, well-known manufacturing materials, processes and equipment are not set forth in detail in order not to unnecessarily obscure the present invention
In the cross sectional view of Figure 3 a portion of an interconnecting structure using the novel metal stack 35 of the present invention is illustrated Typically, the metal stack 35 of the present invention is formed on an ILD layer such as ILD 30 After the layers 31 - 34 of stack 35 have been formed on the dielectric, well-known photolithographic techniques are used to mask the stack and to etch away portions of the stack so as to form the interconnecting structures as will be discussed
Vias are used to provide conductive paths between different levels of metal stacks and between the stacks and substrate regions One via for use with the metal stack of the present invention is described in a co- pending application entitled "A Novel Via Hole Profile and Method of Fabrication", serial no 327,763, filed October 17, 1994 assigned to the Assignee of the present invention
The Present Invention as Shown bv the Stack of Figure 3
The stack 35 illustrated in Figure 3 includes a base layer 31 of titanium which is sputtered in a dedicated chamber onto the ILD layer 30 While titanium is preferred, other refractory metals may be used for this thin layer This shunting layer may be approximately between 125A and 20θΛ thick, although 185A is preferred
A bulk conductor layer 32 which, in one embodiment ,uses an aluminum-copper alloy having approximately 0 5% copper is in contact with the upper surface of the base layer 31 Although an aluminum alloy layer is preferred because of its low resistivity and its well-known processes, it is to be appreciated that other low resistance materials may act as the bulk conductor. The thickness of the layer 32 is selected as a function of the amount of current that the layer 32 will carry. As will be described in conjunction with Figure 4, the thickness of this layer may be different in one level compared to another in a given integrated circuit. Typical values for the thickness of layer 32 range between approximately 5000A to 20,000A thick.
A thin capping layer 33 of titanium is formed in contact with the upper surface of the layer 32. Layer 33 is sputtered titanium, in a dedicated chamber, preferably approximately 185A thick in the preferred embodiment. However, this layer may be approximately between 125A to 200A thick. Again, as in the case of layer 31 other refractory materials may be used for layer 33.
Finally, an anti-reflective coating (ARC) 34 is formed on the upper surface of the layer 33. This layer of titanium nitride (TiN) is approximately 15θA thick. As is well-known this layer reduces reflections which would otherwise make masking of the metal stack more difficult.
As may be noted from Figure 3 there are two interfaces in the stack 35 of aluminum alloy and titanium. Once such interface is between layers 31 and 32 and the other between layers 32 and 33. When titanium and aluminum are sufficiently heated, a reaction occurs to form titanium aluminide (TiAl3). In general, a complete reaction occurs between the titanium layers and the bulk conductor forming titanium aluminide layers at these interfaces. This is accomplished through the use of high temperature processing after formation of the metal stacks such as ordinarily occurs during ILD deposition, ILD annealing, high temperature ash cleaning steps and other steps. Although the original thickness of the titanium layers 31 and 33 are each approximately 185A in the currently preferred embodiment, 185A of Ti will react with 525A of AICu alloy and result in the formation of approximately 67θA of the TiAl3 layer.
Performance measurements were compared for the metal stack shown in Figure 3 and the prior art stacks shown in Figures 1 and 2. The metal stacks of Figure 3 perform better in such areas as via resistance, metal undercutting, voiding, and sheet resistance. The stack of Figure 3 proved to be as manufacturable as the prior art stacks. The electromigration performance as measured by defect density for the stack of Figure 3 was found to be unexpectedly high when compared to the prior art stacks of Figures 1 and 2.
Multiple Level of Figure 4
In a typical integrated circuit, the stack of Figure 3 is used at a plurality of different levels. This is partially shown in the cross section of Figure 4. A first metal stack 40 is formed on the ILD 43. The stack 40 is separated from a second metal stack 42 by an ILD 41 . Another ILD is formed on the stack 42 and may support an additional metal stack.
In typical processing, after the stack 40 is formed it is patterned into an interconnecting structure using well-known photolithography and etch processes. Any well-known etching techniques such as reactive ion etching (RIE) with a chemistry comprising BCI3 and CI2 can be used to pattern the stack 40 to form the interconnecting structure.
Following this an ILD 41 is formed over the pattern stack 40 using well-known chemical vapor deposition (CVD). For instance, a doped silicon dioxide layer is deposited to a thickness of approximately 10.000A. Also, as is well-known, the layer 41 is planarized using chemical etching or chemical-mechanical polishing to form a planar surface upon which the stack 42 may be formed.
The stack 42 is then formed on the ILD 41 in the same manner as used to form the stack 35. Intermediate cleaning, via contact processing steps and other well-known steps have not been described.
The stacks 40 and 42 each may be identical to the stack 35 of Figure 3 except that the thickness of the bulk conductor layer may vary. For instance, the stack 40 comprises a thin base layer of titanium 44 having a thickness in the preferred embodiment of approximately 185A. A bulk conductive layer 45 may have a thickness of, for example, 540θA. The thin capping titanium layer 46 which, in the preferred embodiment, has a thickness of approximately 185A is formed over the layer 45. The ARC coating 47 is then formed on the layer 46.
After the patterning of stack 40 and planarization of the ILD 41 , the stack 42 is formed beginning with the base layer 48 of approximately 185A of titanium. Next the bulk conductor layer 49 of aluminum-copper alloy which may be thicker for the stack 42 (e.g., 740θA) is formed on layer 48. Then the second thin titanium capping layer 50 is formed on layer 49 (approximately 185A thick). Finally, another ARC coating 50 is formed on the layer 50 for the patterning of the stack 42. Processing of the Invented Metal Stack
The metal stack of the present invention is formed using a commercially available cluster sputtering apparatus such as an AMAT 5500, Endura Sputter System. Such systems include, as shown in Figure 5, a central region 60 equipped with a robotic arm allowing wafers to be moved from one chamber to another chamber, such as between chambers 61 , 62, 63 and 64. Each of the chambers are separately controllable to allow different processing to occur in each of the chambers.
For the formation of the stack of the present invention, a wafer is first transported as shown at 66 to a chamber 61. In chamber 61 the base layer of titanium is first sputtered onto an ILD. This is shown in Figure 6 as step 71 which follows the processing of the ILD 70. Following the formation of the approximately 185A thick base layer of titanium, the wafer is next moved to the chamber 63. in chamber 63 the bulk conductor such as aluminum-copper alloy is deposited on the base layer of titanium. This is shown in Figure 6 by the processing step 72.
Now the wafer is moved to the chamber 64 where the capping layer of titanium is formed over the bulk conductor layer. Again as currently preferred, this capping layer is approximately 185A thick. The capping layer is shown in Figure 6 by the process step 73.
Finally the wafer is transported to the chamber 62 where the ARC (TiN coating) is formed over the capping layer of titanium. This is shown in Figure 6 by step 74.
Thus, a novel interconnecting structure formed from a metal stack comprising a thin layer of titanium, bulk conductor layer and thin capping layer of titanium has been described along with its method of fabrication.

Claims

1. A metal stack for use as an interconnecting structure in an integrated circuit comprising: a base layer of titanium; a bulk conductor layer in contact with the base layer; and, a capping layer of titanium in contact with the bulk conductor layer.
2. The metal stack defined by claim 1 wherein the base layer is approximately between 125A and 20θA thick.
3. The metal stack defined by claim 1 wherein the capping layer is approximately between 125A and 20θA thick.
4. The metal stack defined by claim 1 wherein the base layer and capping layer are each approximately between 125A and 20θA thick.
5. The metal stack defined by claims 1 , 2, 3 or 4 wherein the bulk conductor layer comprises an aluminum-copper alloy.
6. The metal stack defined by claim 4 wherein an anti¬ reflective coating of titanium nitride is in contact with the upper surface of the capping layer.
7. A metal stack for use as an interconnecting structure in an integrated circuit comprising: a base layer of titanium having a thickness of approximately 185A; a bulk conductor layer in contact with the base layer; and, a capping layer of titanium in contact with the bulk conductive layer having a thickness of approximately 185A.
8. The metal stack defined by claim 7 wherein the bulk conductor layer comprises an aluminum-copper alloy.
9. The metal stack defined by claim 8 including an anti¬ reflective coating in contact with the upper surface of the capping layer.
10. The metal stack defined by claim 9 including an anti¬ reflective coating comprising titanium nitride formed on the capping layer.
1 1. A process for fabricating a metal stack on a dielectric layer comprising the steps of: sputtering a first layer of titanium on the dielectric layer; forming a bulk conductor layer on the first layer of titanium; and, sputtering a second layer of titanium on the bulk conductor layer.
12. The process defined by clam 1 1 wherein the first layer of titanium is approximately between 125A and 20θA thick.
13. The process defined by clam 12 wherein the second layer of titanium is approximately between 125A and 20θA thick.
14. The process defined by claim 13 wherein the forming step comprises the sputtering of an aluminum-copper alloy.
15. The process defined by claim 14 including the additional step of forming a layer of titanium nitride on the second titanium layer.
PCT/US1996/015351 1995-09-29 1996-09-25 Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions WO1997012399A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019980702234A KR19990063767A (en) 1995-09-29 1996-09-25 Metal lamination for integrated circuits with two chamber-deposited thin titanium layers
JP9512195A JPH11511593A (en) 1995-09-29 1996-09-25 Metal stack for integrated circuits with two thin titanium layers in a dedicated chamber
IL12375196A IL123751A0 (en) 1995-09-29 1996-09-25 Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions
EP96933891A EP0852809A4 (en) 1995-09-29 1996-09-25 Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions
AU72453/96A AU7245396A (en) 1995-09-29 1996-09-25 Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53615595A 1995-09-29 1995-09-29
US08/536,155 1995-09-29

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EP (1) EP0852809A4 (en)
JP (1) JPH11511593A (en)
KR (1) KR19990063767A (en)
CN (1) CN1198252A (en)
AU (1) AU7245396A (en)
IL (1) IL123751A0 (en)
WO (1) WO1997012399A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337263B1 (en) 1999-01-27 2002-01-08 Infineon Technologies Ag Method for improving the quality of metal conductor tracks on semiconductor structures
DE10053915A1 (en) * 2000-10-31 2002-05-16 Infineon Technologies Ag Production of integrated circuit comprises applying metallization layers to circuit substrate, and forming hard mask at predetermined temperature which effects phase conversion
US6492281B1 (en) * 2000-09-22 2002-12-10 Advanced Micro Devices, Inc. Method of fabricating conductor structures with metal comb bridging avoidance

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1324675C (en) * 2003-04-02 2007-07-04 旺宏电子股份有限公司 Structure and method for preventing micro image processing aligning mistake
CN1316613C (en) * 2003-06-19 2007-05-16 旺宏电子股份有限公司 Sandwich antireflection structural metal layer of semiconductor and making process thereof
KR100650904B1 (en) * 2005-12-29 2006-11-28 동부일렉트로닉스 주식회사 Method of forming aluminum line
KR102036942B1 (en) 2012-02-24 2019-10-25 스카이워크스 솔루션즈, 인코포레이티드 Improved structures, devices and methods related to copper interconnects for compound semiconductors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673623A (en) * 1985-05-06 1987-06-16 The Board Of Trustees Of The Leland Stanford Junior University Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5231053A (en) * 1990-12-27 1993-07-27 Intel Corporation Process of forming a tri-layer titanium coating for an aluminum layer of a semiconductor device
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5470790A (en) * 1994-10-17 1995-11-28 Intel Corporation Via hole profile and method of fabrication
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
US5747879A (en) * 1995-09-29 1998-05-05 Intel Corporation Interface between titanium and aluminum-alloy in metal stack for integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4673623A (en) * 1985-05-06 1987-06-16 The Board Of Trustees Of The Leland Stanford Junior University Layered and homogeneous films of aluminum and aluminum/silicon with titanium and tungsten for multilevel interconnects

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337263B1 (en) 1999-01-27 2002-01-08 Infineon Technologies Ag Method for improving the quality of metal conductor tracks on semiconductor structures
US6492281B1 (en) * 2000-09-22 2002-12-10 Advanced Micro Devices, Inc. Method of fabricating conductor structures with metal comb bridging avoidance
DE10053915A1 (en) * 2000-10-31 2002-05-16 Infineon Technologies Ag Production of integrated circuit comprises applying metallization layers to circuit substrate, and forming hard mask at predetermined temperature which effects phase conversion
DE10053915C2 (en) * 2000-10-31 2002-11-14 Infineon Technologies Ag Manufacturing process for an integrated circuit

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KR19990063767A (en) 1999-07-26
CN1198252A (en) 1998-11-04
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EP0852809A1 (en) 1998-07-15
EP0852809A4 (en) 1999-09-15
IL123751A0 (en) 1998-10-30

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