WO1996041251A1 - Wake-up system for a pcmcia card - Google Patents
Wake-up system for a pcmcia card Download PDFInfo
- Publication number
- WO1996041251A1 WO1996041251A1 PCT/US1996/005212 US9605212W WO9641251A1 WO 1996041251 A1 WO1996041251 A1 WO 1996041251A1 US 9605212 W US9605212 W US 9605212W WO 9641251 A1 WO9641251 A1 WO 9641251A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- logic
- pcmcia
- cis
- card
- signal
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
Definitions
- the present invention relates generally to portable computers, and more particularly, to a system that causes a PCMCIA card to exit from a power down mode to convey its configuration information to a host.
- PCMCIA Personal Computer Memory Card Industry Association
- the standard not only defines card dimensions and a bus pin- out, but also describes file formats and data structures, a means that allows a card to convey its configuration and capabilities to a host, and a device-independent means of accessing card hardware and software links.
- the PCMCIA bus standard specifies that information on resource requirements for a card should reside in a non-volatile memory on the card.
- Resources that may be required by the card include, for example, interrupt channel numbers, DMA channel numbers, and amount of memory space required from the host computer system.
- the card includes various combinations of the resource requirements. This information is to be read by configuration software that resides in the host computer system at the time of insertion of the card into the host computer, or at the time the computer is turned on.
- configuration software that resides in the host computer system at the time of insertion of the card into the host computer, or at the time the computer is turned on.
- the information residing in the non-volatile memory on the card for purposes of PCMCIA bus configuration is called Card Information Structure (CIS) .
- CIS Card Information Structure
- the PCMCIA bus standard requires the CIS to be permanently available for reading through a PCMCIA bus coupled the host computer to the card, including the time periods when the card is put into a power-down mode.
- This mode defined by the PCMCIA bus standard, is a SLEEP mode intended to reduce the current consumed by the card, in order to preserve precious battery power of a portable computer.
- a status bit is sent from the card to the host computer to indicate whether or not the card is in the SLEEP mode
- a common method for storing the CIS information is to place it within a non-volatile memory device of a PCMCIA adapter card inserted into a host portable computer.
- a flash memory may be used for storing the CIS.
- This flash memory may be accessible by the host computer through the PCMCIA bus, and by a subsystem that resides on the adapter card through a bus local to the adapter card.
- the adapter card sub-system is controlled by a clock. When the adapter card is in the SLEEP mode, it is desired that the clock to the adapter card sub-system be disabled in order to conserve as much power as possible.
- one advantage of the invention is in providing a system that allows host computer access to a CIS memory on a PCMCIA card during a SLEEP mode, without additional non-volatile memory and interface logic.
- Another advantage of the invention is in providing a wake-up system for activating a PCMCIA card during a SLEEP mode that allows power consumption of battery- powered portable computers to be reduced.
- a non-volatile memory accessible to the host computer and the PCMCIA card logic is provided on the PCMCIA card for storing the CIS and other information.
- Arbitration logic is coupled to the memory to control the host computer's and PCMCIA card logic access to the memory.
- Sleep logic supplies a sleep control signal to switch the arbitration logic and the PCMCIA card into the SLEEP mode.
- a CIS read detect logic monitors the PCMCIA bus to supply the sleep logic with a CIS read detect signal when a CIS read operation is detected. The CIS read detect signal activates the arbitration logic to allow the host computer to access the CIS.
- the sleep control signal prevents a fast clock signal from being supplied to the remaining logic on the arbitration logic and to the PCMCIA card logic.
- the sleep logic allows the fast clock signal to be supplied to the arbitration logic.
- the fast clock signal may be allowed to be supplied to the PCMCIA card.
- a slow clock signal at a frequency lower than the fast clock signal is supplied to the sleep logic during the SLEEP mode to activate the PCMCIA card after a preprogrammed time interval.
- the following steps are carried out: storing the CIS and other information used by the logic on the card or in the host computer system in a non-volatile memory accessible to the host computer via a PCMCIA bus and to an adapter card logic via a local bus, controlling by an arbitration means accesses of the PCMCIA bus and the local bus to the non-volatile memory, disabling the arbitration means in response to a sleep control signal that switches the PCMCIA card into the SLEEP mode, monitoring the PCMCIA bus to decode a CIS read operation, and activating the arbitration means in response to the decoded CIS read operation to allow the host processor to access the non-volatile memory.
- FIG. 1 is a block-diagram illustrating a wake-up system for PCMCIA cards in accordance with the present invention.
- FIG. 2 is a diagram illustrating the CIS read detect circuit shown in FIG. 1.
- a host computer 2 is coupled to a PCMCIA adapter card 4 through a PCMCIA bus 6.
- the card 4 comprises a non-volatile memory 42 containing CIS information.
- CIS information For example, a flash memory may be used for storing the CIS information.
- the flash memory 42 is accessible to a subsystem residing on the adapter card. This subsystem is represented by a block 44. The subsystem accesses the memory 42 through a local bus 46.
- SLEEP logic 52 supports the SLEEP mode of the PCMCIA card 4.
- the SLEEP logic 52 may be implemented by a power down state machine activated by a GO TO SLEEP (GTS) signal asserted by the adapter card subsystem 44.
- GTS GO TO SLEEP
- the GTS signal may be provided by the host computer 2.
- the power down machine asserts a select clock (selclk) signal supplied to a multiplexer 55 having two inputs.
- fclk fast clock
- Another input is grounded.
- the selclk signal is deasserted to allow the fclk signal to be supplied from the output of the multiplexer 55 to the arbitration logic 48 and the adapter card subsystem 44.
- the asserted selclk prevents the fclk signal from being supplied to the arbitration logic 48 and the adapter card subsystem 44. Instead, these circuits will be connected to ground. This will cause the arbitration logic 48 and the adapter card subsystem 44 to be switched into a low power state to preserve the computer's battery power. In this state, no logical functions occur in either the arbitration logic 48 or the adapter card subsystem 44. Accordingly, no access from the PCMCIA bus 6 to the memory 42 is provided.
- the SLEEP logic 52 may be preprogrammed to exit the SLEEP mode after a predetermined time interval.
- Slow clock (sclk) signals are supplied, for example at 32 KHz, from a slow clock 56 to the SLEEP logic 52 to define this time interval.
- the exit from the SLEEP mode may be initiated when a counter in the logic 52 that counts when the sclk signals reaches a predetermined count.
- a CIS read detect circuit 57 is incorporated onto the adapter card 4.
- the CIS read detect circuit 57 is active during the SLEEP mode to monitor the PCMCIA bus 6.
- the CIS read detect circuit 57 asserts a CIS detect signal supplied to the SLEEP logic.
- the SLEEP logic deasserts the selclk signal to allow the fclk signal to pass through the multiplexer 54.
- the fclk signal is supplied to the arbitration logic 48 and to the adapter card subsystem 44 to cause the SLEEP mode to be exited.
- the fclk signal may be supplied only to the arbitration logic 48 to allow the adapter card subsystem 44 to stay in the SLEEP mode.
- host computer access to the CIS memory 42 is provided in a short time period that allows the adapter card 4 to comply with PCMCIA bus protocol defined duration of bus cycle.
- the CIS read detect circuit 57 comprises a PCMCIA decoder 60 coupled to the PCMCIA bus 6.
- the decoder 60 receives a register select (Reg) signal, a chip enabling (CE) signal, an output enabling (OE) signal and address (Addr) signals supplied through the PCMCIA bus 6 in accordance with the PCMCIA bus standard to detect a flash select (flashsel) signal indicating that the host computer 2 requests CIS information from the memory 42.
- a D flip-flop 62 the flashsel signal is supplied to an AND gate 64.
- the clock input of the D flip-flop 62 is supplied with the fclk signal.
- the AND gate 64 is also provided with a power down signal from the SLEEP logic asserted during the SLEEP mode. As a result, the AND gate 64 supplies the SLEEP logic 52 with the CIS detect signal, when the flashsel signal is detected during the SLEEP mode. As discussed above, the CIS detect signal causes the SLEEP mode to be exited to allow host computer access to the memory 42 to read the CIS information.
- the adapter card subsystem 44 may again place the adapter card 4 into the SLEEP mode. Alternatively, the switching back to the SLEEP mode may be initiated by the host computer 2.
- a CIS read operation on the PCMCIA bus is detected by the CIS read detect circuit that asserts the CIS detect signal supplied to the SLEEP logic.
- the SLEEP logic allows the fast clock signals to be supplied to the arbitration logic and adapter card subsystem to exit from the SLEEP mode and provide the host computer's access to the memory storing the CIS information.
- the disclosed system allows the entire adapter card, except for the circuits involved in the CIS read detection, to enter the SLEEP mode, thereby minimizing the power consumption of battery-powered portable computers.
- the system allows the additional non-volatile memory and additional PCMCIA interface logic required in some implementations to be removed. The removal of these devices yields cost savings due to reducing the component count required to build a system as well as due to reducing system complexity, thereby increasing reliability and reducing costs at the assembly and test stages of product manufacture.
- the form factor for a standard PCMCIA card is strictly limited, and the removal of components from the card allows valuable card space to be used, for example, for providing additional features.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50047097A JP3726116B2 (en) | 1995-06-07 | 1996-04-15 | Boot system for PCMCIA card |
EP96911770A EP0834105B1 (en) | 1995-06-07 | 1996-04-15 | Wake-up system for a pcmcia card |
DE69601311T DE69601311T2 (en) | 1995-06-07 | 1996-04-15 | ALARM SYSTEM FOR PCMCIA CARD |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/487,316 | 1995-06-07 | ||
US08/487,316 US5845139A (en) | 1995-06-07 | 1995-06-07 | System for providing a host computer with access to a memory on a PCMCIA card in a power down mode |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996041251A1 true WO1996041251A1 (en) | 1996-12-19 |
Family
ID=23935249
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/005212 WO1996041251A1 (en) | 1995-06-07 | 1996-04-15 | Wake-up system for a pcmcia card |
Country Status (6)
Country | Link |
---|---|
US (1) | US5845139A (en) |
EP (1) | EP0834105B1 (en) |
JP (1) | JP3726116B2 (en) |
KR (1) | KR19990022054A (en) |
DE (1) | DE69601311T2 (en) |
WO (1) | WO1996041251A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6389486B1 (en) * | 1999-05-06 | 2002-05-14 | Ericsson Inc. | Systems and methods for transferring PCMCIA card status information to host devices |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3167931B2 (en) * | 1996-07-15 | 2001-05-21 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | PC cards and peripherals |
JPH10301661A (en) * | 1997-04-23 | 1998-11-13 | Matsushita Electric Ind Co Ltd | Clock supplying device |
US6499087B1 (en) * | 1997-11-14 | 2002-12-24 | Agere Systems Guardian Corp. | Synchronous memory sharing based on cycle stealing |
US6175865B1 (en) * | 1998-11-12 | 2001-01-16 | Hewlett-Packard Company | Apparatus for automatically configuring network media connections |
US6194940B1 (en) * | 1999-09-27 | 2001-02-27 | Lucent Technologies Inc. | Automatic clock switching |
CN1188795C (en) * | 1999-11-24 | 2005-02-09 | 皇家菲利浦电子有限公司 | Data processing unit with access to memory of another data processing unit during standby |
KR100415092B1 (en) * | 2002-05-13 | 2004-01-13 | 주식회사 하이닉스반도체 | A semiconductor memory device with a mode register, and method for controlling deep power down mode thereof |
FI20021867A (en) * | 2002-10-18 | 2004-04-19 | Nokia Corp | Method for changing card mode, system, card, and device |
US20040260843A1 (en) * | 2003-06-23 | 2004-12-23 | Sleeman Peter T. | Peripheral device card bridging device |
DE10339887B4 (en) * | 2003-08-29 | 2011-07-07 | Infineon Technologies AG, 81669 | Devices with mutual wake-up function from standby mode |
US20050071534A1 (en) * | 2003-09-30 | 2005-03-31 | Dell Products L.P. | Chassis expansion using newcard |
FI116254B (en) * | 2003-11-14 | 2005-10-14 | Nokia Corp | Signal filtering |
US20050223125A1 (en) * | 2004-03-31 | 2005-10-06 | Intel Corporation | Multi-interfacing in a reconfigurable system |
US7570591B2 (en) * | 2004-08-03 | 2009-08-04 | Hewlett Packard Development Company, L.P. | Method and apparatus for negotiating link speed and configuration |
US7376037B1 (en) * | 2005-09-26 | 2008-05-20 | Lattice Semiconductor Corporation | Programmable logic device with power-saving architecture |
US7818593B2 (en) * | 2005-09-28 | 2010-10-19 | Qualcomm Incorporated | Power conversation for devices on a shared bus using bus busy and free signals |
US7472299B2 (en) * | 2005-09-30 | 2008-12-30 | Intel Corporation | Low power arbiters in interconnection routers |
JP2017136898A (en) | 2016-02-02 | 2017-08-10 | 株式会社Subaru | Vehicular seat control device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1992009028A1 (en) * | 1990-11-09 | 1992-05-29 | Wang Laboratories, Inc. | System clock speed controller |
JPH06282363A (en) * | 1993-03-30 | 1994-10-07 | Matsushita Electric Ind Co Ltd | Control device for input device |
EP0621526A1 (en) * | 1993-04-21 | 1994-10-26 | WaferScale Integration Inc. | Method and apparatus for powering up and powering down peripheral elements |
US5361364A (en) * | 1990-11-22 | 1994-11-01 | Hitachi, Ltd. | Peripheral equipment control device |
JPH0784686A (en) * | 1993-06-30 | 1995-03-31 | Canon Inc | Portable pen input computer device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4385369A (en) * | 1981-08-21 | 1983-05-24 | Mostek Corporation | Semiconductor memory address buffer having power down mode |
JPH06502510A (en) * | 1990-10-12 | 1994-03-17 | インテル・コーポレーション | Slow memory refresh on computers with limited power supplies |
JP3090767B2 (en) * | 1992-04-02 | 2000-09-25 | ダイヤセミコンシステムズ株式会社 | Computer system power saving controller |
US5404543A (en) * | 1992-05-29 | 1995-04-04 | International Business Machines Corporation | Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes |
US5586332A (en) * | 1993-03-24 | 1996-12-17 | Intel Corporation | Power management for low power processors through the use of auto clock-throttling |
JPH06282362A (en) * | 1993-03-26 | 1994-10-07 | Sanyo Electric Co Ltd | Method for controlling drive of device in information processor |
US5584031A (en) * | 1993-11-09 | 1996-12-10 | Motorola Inc. | System and method for executing a low power delay instruction |
US5546590A (en) * | 1994-09-19 | 1996-08-13 | Intel Corporation | Power down state machine for PCMCIA PC card applications |
US5721935A (en) * | 1995-12-20 | 1998-02-24 | Compaq Computer Corporation | Apparatus and method for entering low power mode in a computer system |
US5652895A (en) * | 1995-12-26 | 1997-07-29 | Intel Corporation | Computer system having a power conservation mode and utilizing a bus arbiter device which is operable to control the power conservation mode |
-
1995
- 1995-06-07 US US08/487,316 patent/US5845139A/en not_active Expired - Lifetime
-
1996
- 1996-04-15 JP JP50047097A patent/JP3726116B2/en not_active Expired - Fee Related
- 1996-04-15 WO PCT/US1996/005212 patent/WO1996041251A1/en not_active Application Discontinuation
- 1996-04-15 DE DE69601311T patent/DE69601311T2/en not_active Expired - Lifetime
- 1996-04-15 EP EP96911770A patent/EP0834105B1/en not_active Expired - Lifetime
- 1996-04-15 KR KR1019970708533A patent/KR19990022054A/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1992009028A1 (en) * | 1990-11-09 | 1992-05-29 | Wang Laboratories, Inc. | System clock speed controller |
US5361364A (en) * | 1990-11-22 | 1994-11-01 | Hitachi, Ltd. | Peripheral equipment control device |
JPH06282363A (en) * | 1993-03-30 | 1994-10-07 | Matsushita Electric Ind Co Ltd | Control device for input device |
EP0621526A1 (en) * | 1993-04-21 | 1994-10-26 | WaferScale Integration Inc. | Method and apparatus for powering up and powering down peripheral elements |
JPH0784686A (en) * | 1993-06-30 | 1995-03-31 | Canon Inc | Portable pen input computer device |
Non-Patent Citations (3)
Title |
---|
ANONYMOUS: "Arbitration Circuit for a Personal Computer Memory Card Internaional Association Card", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 38, no. 3, March 1995 (1995-03-01), NEW YORK, US, pages 593 - 596, XP002007951 * |
PATENT ABSTRACTS OF JAPAN vol. 94, no. 010 * |
PATENT ABSTRACTS OF JAPAN vol. 95, no. 003 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6389486B1 (en) * | 1999-05-06 | 2002-05-14 | Ericsson Inc. | Systems and methods for transferring PCMCIA card status information to host devices |
Also Published As
Publication number | Publication date |
---|---|
JP3726116B2 (en) | 2005-12-14 |
DE69601311D1 (en) | 1999-02-18 |
EP0834105B1 (en) | 1999-01-07 |
EP0834105A1 (en) | 1998-04-08 |
DE69601311T2 (en) | 1999-09-02 |
US5845139A (en) | 1998-12-01 |
JPH11506235A (en) | 1999-06-02 |
KR19990022054A (en) | 1999-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5845139A (en) | System for providing a host computer with access to a memory on a PCMCIA card in a power down mode | |
US5623677A (en) | Apparatus and method for reducing power consumption in a computer system | |
US5596756A (en) | Sub-bus activity detection technique for power management within a computer system | |
US6357013B1 (en) | Circuit for setting computer system bus signals to predetermined states in low power mode | |
US5388265A (en) | Method and apparatus for placing an integrated circuit chip in a reduced power consumption state | |
JP3919245B2 (en) | Integrated processor | |
JP3964472B2 (en) | Clock controller | |
US5721935A (en) | Apparatus and method for entering low power mode in a computer system | |
US5590341A (en) | Method and apparatus for reducing power consumption in a computer system using ready delay | |
US5764968A (en) | Clock supply permission/inhibition control system | |
US7146510B1 (en) | Use of a signal line to adjust width and/or frequency of a communication link during system operation | |
US5625807A (en) | System and method for enabling and disabling a clock run function to control a peripheral bus clock signal | |
JP3919246B2 (en) | Multiplexer, integrated processor, and signal multiplexer | |
US6457082B1 (en) | Break event generation during transitions between modes of operation in a computer system | |
CA2160525A1 (en) | Circuit for placing a cache memory into low power mode in response to special bus cycles | |
US4694393A (en) | Peripheral unit for a microprocessor system | |
US5796992A (en) | Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode | |
US6079024A (en) | Bus interface unit having selectively enabled buffers | |
US7219248B2 (en) | Semiconductor integrated circuit operable to control power supply voltage | |
US7237132B2 (en) | Power reduction for unintentional activation of a wireless input device using a flip-flop to detect event termination | |
US6016551A (en) | Method and apparatus for masking and unmasking a clock signal in an integrated circuit | |
JPH10133766A (en) | Adaptive power-down clock control | |
EP0621526A1 (en) | Method and apparatus for powering up and powering down peripheral elements | |
US5974561A (en) | Method and apparatus for generating a reset signal within an integrated circuit | |
JPH07281794A (en) | Card interface device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1996911770 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1019970708533 Country of ref document: KR |
|
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 1997 500470 Kind code of ref document: A Format of ref document f/p: F |
|
WWP | Wipo information: published in national office |
Ref document number: 1996911770 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 1996911770 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1019970708533 Country of ref document: KR |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1019970708533 Country of ref document: KR |