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WO1996036104A1 - A direct conversion receiver - Google Patents

A direct conversion receiver

Info

Publication number
WO1996036104A1
WO1996036104A1 PCT/GB1995/001058 GB9501058W WO1996036104A1 WO 1996036104 A1 WO1996036104 A1 WO 1996036104A1 GB 9501058 W GB9501058 W GB 9501058W WO 1996036104 A1 WO1996036104 A1 WO 1996036104A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
phase
output
circuit
input
signals
Prior art date
Application number
PCT/GB1995/001058
Other languages
French (fr)
Inventor
Christopher Nigel Smith
Original Assignee
Roke Manor Research Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying includes continuous phase systems
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/233Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2332Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/30Circuits for homodyne or synchrodyne receivers
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/007Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals

Abstract

The receiver includes input means comprising an antenna and blocking filter, the output of which is connected to an amplifier. The input signal is split and mixed with an in-phase and quadrature phase signal generated by an oscillator in a mixer circuit, respectively. An output from each mixer circuit is applied to a low pass filter and to an input of a limiting circuit. The output from each low pass filter is applied to an input of a summator circuit respectively, a first of which is arranged to sum the in-phase and quadrature phase signals, and the second of which is arranged to subtract the in-phase and quadrature phase signals to generate a respective output signal having an axis intermediate of the in-phase and quadrature phase signal axes. These signals, together with the in-phase and quadrature phase signals are passed through a limiting circuit respectively, to a decoder circuit for recovering the data. The output of the limiting circuits represents signals quantised to eight possible phase states separated by 45°. When the input signal is GFSK modulated the vector will always cross at least one axis, so the direction of rotation can be established prior to data recovery. In an alternative embodiment a ratiometric combiner may be used instead of the summator circuits, and this is particularly useful for π/4-DQPSK modulation, where the phase excursion per symbol is ± 45° or ± 135° depending upon the bit pair combination, and in this embodiment a minimum of eight axes are generated giving sixteen sectors and 22.5° phase resolution.

Description

A DIRECT CONVERSION RECEIVER

The present invention relates to a direct conversion receiver for use in radio systems.

It is known to use direct conversion in radio receivers which avoid the use of bulky and expensive bandpass IF filters. Also, the use of RF filters is considerably simplified and a complete receiver may be integrated onto a single chip.

In practice, one of the main obstacles to the successful implementation of direct conversion, particularly in the digital communications environment, is a requirement for automatic gain control (AGC). In a direct conversion receiver, AGC must be derived from baseband, which often makes it too slow for use with the bursted signals commonly used in modern digital systems .

Referring to Figures 1 and 2, Figure 1 shows an arrangement which is often used in low data rate paging receivers and includes an antenna 2 connected to an input of a blocking filter 4, the output of which is connected to an input of an amplifier 6. The output of the amplifier is applied to an input of a mixer 8, 10 respectively, which receive at a second input thereof, an output from an oscillator 12. The mixer 8 receives a signal which is at 0° phase from the oscillator 12, and the mixer 10 receives a signal which is at 90° phase from the oscillator 12. The outputs of the mixers 8 and 10 are applied respectively to an input of a low pass filter 14, 16, the output of which is applied to limiters 18, 20 respectively. The output from the limiter 18 is an in-phase signal I, and the output from the limiter 20 is a quadrature phase signal Q. The circuit thus described does not require any AGC.

If the inputs of the receiver is a frequency shift keyed (FSK) signal, it may be represented vectorially as shown in Figure 2. The left hand diagram of Figure 2 shows that the input can have any phase angle, whereas the output, after hard limiting, the I and Q signals are quantised to any four possible phase states, as shown in the right hand diagram of Figure 2.

In order to demodulate the FSK modulation, it is necessary to establish the direction of rotation of the vector. This is straight forward in paging systems where the modulation index is high, since the vector will rotate several cycles for each data bit. The limited I and Q output signals then become a burst of square waves at 90° to each other, either leading or lagging, depending upon the direction of rotation. By comparing the limited I and Q signals in a phase sensitive detector (e.g. a D-Type flip-flop), the polarity of the phase difference, and hence modulation can be recovered.

However, in more spectrally efficient, low modulation index schemes such as Gaussian frequency shift keying (GFSK), the vector can rotate as little as 50° per data bit. This means that the vector can remain entirely within one quadrant, so there is no change at the limiter outputs. In this case the data is not recoverable.

An aim of the present invention is to provide a direct conversion receiver for use with phase modulation signals, which does not require AGC. According to the present invention there is provided a receiver comprising means for receiving an input signal transmitted across a radio medium, means for generating an in- phase and a quadrature phase signal from the received input signal and means for generating in-phase and quadrature phase output signals in the form of a burst of hard-limited signals, characterised in that the receiver includes circuit means arranged to generate additional axes intermediate to the in-phase and quadrature phase signal axes, from which a burst of hard-limited signals are generated, and decoding means arranged to receive the bursts of hard-limited signals and arranged to generate data corresponding to the received radio signal.

The circuit means may include first and second summator circuits, the first of which is arranged to sum the in-phase and quadrature phase signals, the second of which is arranged to subtract the in-phase and quadrature phase signals, thereby generating signals having an axis which is intermediate of the in- phase and quadrature phase signal axes.

The circuit means may include a ratiometric combiner arranged to generate eight axes intermediate of the in-phase and quadrature phase signal axes.

Various embodiments of the present invention will now be described with reference to the accompanying drawings, wherein,

FIGURE 3 shows a direct conversion receiver using four limiters,

FIGURE 4 shows the vector signal representation in a four axis receiver, FIGURE 5 shows a block diagram of an FSK decoder,

FIGURE 6 shows a block diagram of a direct conversion receiver using 'n' limiters, and,

FIGURE 7 shows a block diagram of a π /4-DQPSK (differential quadrature phase shift keyed) decoder.

Referring to Figure 3, there is shown a block diagram of a direct conversion receiver using four limiters. The receiver as shown overcomes the drawback mentioned with respect to the prior art by effectively introducing additional axes, intermediate to the axes of the in-phase I and quadrature phase Q signals. The simplest realisation of this is to add two additional axes at 45° and 135°, by taking the sum and difference of the in-phase I and quadrature phase Q signals, and hard limiting the two new signals designated A and B, as shown in the drawing. The receiver comprises an antenna 22 connected to a blocking filter 24, the output of which is applied to an amplifier 26. The output of the amplifier is applied to a first input of a mixer circuit 28, 30 respectively. The mixer circuit 28 receives an in-phase signal I from an oscillator 32, and the mixer circuit 30 receives a quadrature phase signal Q from an oscillator 32. An output from each mixer circuit 28, 30 is applied to an input of a low pass filter 34, 36 respectively. The output of the filter 34 represents the in- phase signal and is applied to an input of a limiter 42, an input of a summator circuit 38, and to an input of a summator circuit 40. Similarly the output of the filter 36 which represents the quadrature phase signal, is applied to an input of a limiter 48, a further input of summator 40 and to a further input of the summator 38. The summator 38 generates an output signal A which is the summation of the two input signals, and the summator 40 generates an output signal B which is the difference of the two input signals. The output of the summator 38 is applied to a limiter 44, and the output of the summator 40 is applied to an input of a limiter 46. Each of the limiters 42-48 generate an output signal which is applied to a decoder 50 from which an output data signal is generated on an output line 52.

The vector diagram in relation to Figure 3 is shown in Figure 4. With four axes there are now eight sectors, and the hard limited signals effectively represent the signals quantised to eight possible phase states, separated by 45°. When the input signal is a GFSK modulated signal, the vector will now always cross at least one axis, so the direction of rotation can be established and the data recovered.

With reference to Figure 4, the left hand diagram shows that the input signal can have any phase angle, and the right hand diagram shows that after hard limiting the output is quantised to eight possible phase states.

The decoding of the data may be achieved digitally from the binary signals at the outputs of the limiters 42-48 in Figure 4, and the decoding is shown with reference to Figure 5. Figure 5 shows an FSK decoder comprising combinational logic circuit 54 which receives the I, A, B and Q inputs from the limiters 42-48 in Figure 4. The output of the combinational logic circuit is connected to an input of a delay circuit 56 and to the input of a summator circuit 58. The output of the delay circuit 56 is connected to a further input of the summator circuit 58. The output of the summator circuit 58 is connected to an input of an averaging circuit 60, the output of which is applied to a hard limiter 62 from which data is output on an output line 64.

The simple combinational logic may be used to give a binary sector output from 0 to 7 representing the phase sector in which the signal instantaneously resides. By subtracting the previous sector value from the present sector value (modulo-8 arithmetic), a series of pulses is obtained which are either positive of negative, depending upon the direction of rotation. Effectively, a sampled frequency discriminator is formed. To avoid aliassing, the delay element should be less than half a bit period. The pulse train is then averaged in the circuit 60 and limited by the circuit 62 to extract the data.

In modulation schemes where the phase excursion per bit is even less (such as π/4-DQPSK or GFSK with a very low BT factor where B is the bandwidth of the modulation filter and T is the bit period), the technique can be expanded by introducing more axes, hence improving the phase resolution. This concept is shown in Figure 6.

Referring to Figure 6, a further embodiment of the present invention will now be described, and shows a direct conversion receiver using 'n' limiters.

The receiver comprises antenna 66 which feeds an RF filter 68, the output of which is connected to an input of an amplifier 70. The output of the amplifier is applied to the input of a mixer circuit 72 and to an input of a mixer circuit 74. The second inputs of the mixer circuits 72, 74 receive an output from an oscillator 76 in the form of an in-phase signal applied to the mixer circuit 72, and a quadrature phase signal applied to the mixer circuit 74. An output of the mixer circuit 72 is applied to a low pass filter 78, and similarly the output of the mixer circuit 74 is applied a low pass filter 80. The outputs of the filters 78, 80 are each applied to ratiometric combiner 82 respectively, and to an input of a limiter 84 and a limiter 92, respectively. The ratiometric combiner 82 generates a number of output signals, each of which is applied to an input of a limiter 86-90 respectively. An output from each limiter is applied to an input to a decoder circuit 94 which is arranged to generate an output signal on an output line 96.

In π/4-DQPSK modulation, the phase excursion per symbol is ± 45° or ±. 135° depending on the bit pair combination (00, 01, 10 or 11). In the receiver the arrangement as shown in Figure 6, a minimum of eight axes (and eight limiters) would therefore be required giving sixteen sectors and 22.5° phase resolution. The decoding would also change slightly from the FSK version, since three decision thresholds would be needed to detect the magnitude as well as the polarity of the phase shift. The decoder is shown in Figure 7.

Referring to Figure 7, a decoder circuit comprises a logic circuit 98 which receives the input signals from the limiter circuits 84-92 (Figure 6). An output from the logic circuit is applied to the input of a summator circuit 102 and to input of a delay circuit 100. An output from the delay circuit 100 is connected to a further input of the summator circuit 102. An output from the summator circuit 102 is connected to an input of an averaging circuit 104, the output of which is applied to three threshold devices 106, 108, 110, which are arranged to compare the output of the averaging circuit 104 with a threshold signal applied to a second input thereof. The output of each threshold circuit 106-110 is applied to an input of a logic circuit 112, respectively, which is arranged to generate an output data bit on an output line 114, and an output line 116.

It will be appreciated by those skilled in the art that variations and modifications are possible within the scope of the following claims. The receiver is primarily aimed at phase or frequency modulation schemes. However, it will be appreciated that in systems where the envelope variation must be preserved (e.g. for equalisation), the signal envelope could be obtained from the limiter received signal strength indicator ( RSSI) outputs. As this would be a log-compressed envelope, an anti-log function would be needed to restore the linear amplitude variation.

Claims

1. A receiver comprising means for receiving an input signal transmitted across a radio medium, means for generating an in- phase and a quadrature phase signal from the received input signal and means for generating in-phase and quadrature phase output signals in the form of a burst of hard-limited signals, characterised in that the receiver includes circuit means arranged to generate additional axes intermediate to the in-phase and quadrature phase signal axes, from which a burst of hard-limited signals are generated, and decoding means arranged to receive the bursts of hard-limited signals and arranged to generate data corresponding to the received radio signal.
2. A receiver as claimed in Claim 1 , wherein the circuit means comprises first and second summator circuits, the first of which is arranged to sum the in-phase and quadrature phase signals in any ratio, the second of which is arranged to subtract the in-phase and quadrature phase signals in any ratio, thereby generating signals having an axis which is intermediate of the in-phase and quadrature phase signal axes.
3. A receiver as claimed in Claim 2, wherein the output signals from the first and second summators are applied to an input of a limiting device respectively, from which the burst of hard-limited signals are generated, and said in-phase and quadrature phase signals are applied to a limiting device respectively, the output signals from the limiting devices being applied to an input of said decoding circuit respectively.
4. A receiver as claimed in any preceding claim, characterised in that the decoding circuit comprises a combination logic circuit arranged to receive the output signals from the limiting devices, and arranged to give a sector output from zero to seven, when four axes are used, representing a phase sector in which the signal instantaneously resides, and means for subtracting a previous vector from the present vector to generate a series of pulses dependent upon a direction of rotation of the vector.
5. A receiver as claimed in Claim 4, wherein the series of pulses are applied to an averaging circuit and to a limiting circuit arranged to extract the data from said series of pulses.
6. A receiver as claimed in any preceding claim, wherein the decoding means is an FSK decoder.
7. A receiver as claimed in Claim 1, wherein the circuit means comprises a ratiometric combiner arranged to generate eight axes intermediate of the in-phase and quadrature phase signal axes.
8. A receiver as claimed in Claim 7, wherein the output signals from the radiometric combiner circuit, and the in-phase and quadrature phase signals are applied to a limiting circuit respectively, the output signals from which are applied to an input of a decoder circuit respectively.
9. A receiver as claimed in Claim 8, wherein the decoder circuit includes, input logic means arranged to receive the input signals from the limiting devices and arranged to generate a sector output signal in the range of 0 to 15, when eight axes are used, and means for subtracting a previous vector from a present vector in order to generate a series of output signals.
10. A receiver as claimed in Claim 9, wherein the series of output signals are applied to an averaging circuit, the output of which is applied to an input of three decision circuits respectively, and arranged to detect the magnitude and polarity of phase shift, an output of each division circuit being connected to an output logic circuit arranged to generate data output signals on output data lines.
1 1 . A receiver as claimed in Claim 1 or an y of the preceding claims 7-10, wherein the decoding means is a π/4-DQPSK decoder.
12. A receiver substantially as hereinbefore described with reference to Figures 3, 4, 5, 6 and 7 of the accompanying drawings.
PCT/GB1995/001058 1994-02-22 1995-05-10 A direct conversion receiver WO1996036104A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB9403318A GB2286950B (en) 1994-02-22 1994-02-22 A direct conversion receiver
PCT/GB1995/001058 WO1996036104A1 (en) 1994-02-22 1995-05-10 A direct conversion receiver

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
GB9403318A GB2286950B (en) 1994-02-22 1994-02-22 A direct conversion receiver
DE1995615312 DE69515312T2 (en) 1995-05-10 1995-05-10 Direct conversion receiver
US08765686 US5943370A (en) 1995-05-10 1995-05-10 Direct conversion receiver
PCT/GB1995/001058 WO1996036104A1 (en) 1994-02-22 1995-05-10 A direct conversion receiver
JP53384396A JPH10504952A (en) 1995-05-10 1995-05-10 Direct conversion receiver
EP19950918083 EP0772905B1 (en) 1995-05-10 1995-05-10 A direct conversion receiver
CA 2194695 CA2194695C (en) 1995-05-10 1995-05-10 A direct conversion receiver
DE1995615312 DE69515312D1 (en) 1995-05-10 1995-05-10 Direct conversion receiver
DK95918083T DK0772905T3 (en) 1995-05-10 1995-05-10 Direct conversion receiver
FI970028A FI970028A (en) 1995-05-10 1997-01-03 Direct Conversion Receiver

Publications (1)

Publication Number Publication Date
WO1996036104A1 true true WO1996036104A1 (en) 1996-11-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1995/001058 WO1996036104A1 (en) 1994-02-22 1995-05-10 A direct conversion receiver

Country Status (9)

Country Link
US (1) US5943370A (en)
EP (1) EP0772905B1 (en)
JP (1) JPH10504952A (en)
CA (1) CA2194695C (en)
DE (2) DE69515312T2 (en)
DK (1) DK0772905T3 (en)
FI (1) FI970028A (en)
GB (1) GB2286950B (en)
WO (1) WO1996036104A1 (en)

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Also Published As

Publication number Publication date Type
US5943370A (en) 1999-08-24 grant
FI970028A (en) 1997-01-10 application
CA2194695A1 (en) 1996-11-14 application
DE69515312D1 (en) 2000-04-06 grant
EP0772905A1 (en) 1997-05-14 application
GB9403318D0 (en) 1994-04-13 grant
DK0772905T3 (en) 2000-06-05 grant
GB2286950B (en) 1998-06-17 grant
FI970028D0 (en) grant
JPH10504952A (en) 1998-05-12 application
CA2194695C (en) 2001-07-24 grant
DE69515312T2 (en) 2000-06-21 grant
GB2286950A (en) 1995-08-30 application
EP0772905B1 (en) 2000-03-01 grant
FI970028A0 (en) 1997-01-03 application

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