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WO1995022107A1 - Method and apparatus for testing the functionality of a microprocessor - Google Patents

Method and apparatus for testing the functionality of a microprocessor

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Publication number
WO1995022107A1
WO1995022107A1 PCT/US1995/001549 US9501549W WO1995022107A1 WO 1995022107 A1 WO1995022107 A1 WO 1995022107A1 US 9501549 W US9501549 W US 9501549W WO 1995022107 A1 WO1995022107 A1 WO 1995022107A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
micro
address
instruction
microprocessor
test
Prior art date
Application number
PCT/US1995/001549
Other languages
French (fr)
Inventor
Graham B. Whitted, Iii
James A. Kane
Hsiao-Shih Chang
Original Assignee
Meridian Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/273Tester hardware, i.e. output processing circuits
    • G06F11/2736Tester hardware, i.e. output processing circuits using a dedicated service processor for test
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/28Error detection; Error correction; Monitoring by checking the correct order of processing

Abstract

An apparatus and method test the functionality of a microprocessor (100). The microprocessor (100) performs a two-phase self-test. In the first phase, the microprocessor (100) sequentially executes every micro-instruction stored in a micro-instruction ROM (156), without allowing any micro-instruction jumps. Micro-instruction jumps are inhibited by ignoring a next address. A number of the first micro-instructions substantially initialize the microprocessor circuitry to a known state so that outputs (131, 132) generated by the microprocessor are deterministic. During this first phase, a number of output pins are driven so that an optional external test unit can monitor the output pins and compare the output values against expected values. In addition, cyclical redundancy registers (141, 157) monitor other circuits within the microprocessor. After successful completion of the first phase, the results of the first phase are reported and the second phase begins. The second phase comprises comprehensive micro-diagnostic testing. The second phase of the self test ends with the reporting of the results of the micro-diagnostic tests.

Description

METHOD AND APPARATUS FOR TESTING THE FUNCTIONALITY OF A MICROPROCESSOR

Background of the Invention

Field of the Invention

The present invention is in the field of functional testing for microprocessors.

Background Information

Functional tests of microprocessors are generally performed under two circumstances. First, when a microprocessor is initially manufactured, the functionality of the microprocessor is tested to determine whether the manufacturing process was successful with respect to the particular microprocessor. Second, subsequent functionality tests may be executed to determine whether there have been any failures within the microprocessor. The present invention applies to both types of testing, although it is particularly advantageous in the initial testing context.

The general process for manufacturing a microprocessor is well known to a person of skill in the art. Generally, several hundred dies are produced from a single semiconductor wafer, where each die contains the integrated circuitry of a single microprocessor. Before a microprocessor die is enclosed in packaging material to create an integrated circuit component, it is typically thoroughly tested to determine whether it is functional. Due to the complexity of microprocessor circuits, thorough testing of the circuitry is generally very time consuming, and the testing accounts for a significant portion of the cost of manufacturing a microprocessor. Thus, it is advantageous to minimize the time required to perform functional testing of a microprocessor.

Also, the success rate for manufacturing semiconductor dies that are as complex as a general purpose microprocessor is typically between 15 and 25 percent. Consequently, a relatively large number of dies must be both manufactured and tested to obtain a desired number of functional microprocessors. Typically, all of the dies on a wafer are tested sequentially. Although functional microprocessor dies must be completely tested to verify their functionality, the testing of a defective microprocessor die can be terminated as soon as a defect is detected, so that testing of a subsequent die can begin immediately. Thus, it is particularly advantageous to minimize the average time required to detect a defect in each defective die, so as to minimize the time required to test an entire wafer. Summary of the Invention

One aspect of the present invention is a method of rapidly testing the functionality of a microcomputer wherein the microcomputer has an internal micro-coded instruction unit responsive to a micro¬ instruction read only memory (ROM). Normally, a next address to be accessed in the micro-instruction ROM is determined by a micro-address controller having a next address field from a current micro-instruction as an input. The method comprises the steps of resetting the microcomputer to a known initial state such that a first known address is applied to the micro-instruction ROM to access a first micro-instruction stored at the first known address; and executing the micro-instruction stored in said first known address. The method further includes the steps of generating a second address and all subsequent addresses to the micro- instruction ROM by incrementing the first address irrespective of the next address field of the first micro¬ instruction and irrespective of the next address field of all subsequent micro-instructions so that the micro¬ instruction ROM is addressed sequentially through every address; executing the subsequent micro-instructions; monitoring data generated by the microcomputer when executing the first micro-instruction and the subsequent micro-instructions; and comparing the data with expected data to verify that the microprocessor is operating correctly.

Preferably, the method further includes the steps of applying selected data generated by the microprocessor when executing the micro-instructions as inputs to at least one cyclical redundancy checker, and comparing a data output from the cyclical redundancy checker with a predetermined data value after sequencing through the subsequent micro-instructions to verify that the selected data generated by the microprocessor are correct.

Also preferably, the method further includes the step of applying a fast test enable input signal to the micro-address controller to cause the micro-address controller to ignore the next address field of the current micro-instruction and to apply the next sequential address to the micro-instruction ROM.

Another aspect of the present invention is an apparatus for rapidly self-testing a microprocessor having an execution unit, a micro-instruction read-only-memory (ROM) and a micro-address controller that applies addresses to said micro-instruction ROM, wherein the micro-address controller normally generates next addresses to be applied to the micro-instruction ROM in response to a next address field of a micro¬ instruction from the micro-instruction ROM. The apparatus comprises an address incrementer that generates a new address by incrementing the current address by a predetermined value; and an input signal line applied to the micro-address controller. The micro-address controller is responsive to an active signal on the input signal line to apply the new address from the address incrementer to the micro-instruction ROM irrespective of a value in the next address field of the micro-instruction so that the micro-address controller applies addresses to the micro-instruction ROM in sequence to cause the microprocessor to execute every instruction in the micro-instruction ROM irrespective of whether the next address field of any instruction would otherwise cause an instruction brsπch or skip to occur.

A still further aspect of the present invention is a method of initially testing a microprocessor. The method includes the steps of initializing an address applied to a micro-instruction ROM to a predetermined address location; accessing a first micro-instruction stored in the micro-instruction ROM at the predetermined address location; and executing the first micro-instruction from the micro-instruction ROM and subsequent micro-instructions from the micro-instruction ROM while ignoring any instruction branching commands in any of the micro-instructions so that no micro-instruction is skipped and so that no micro-instruction is executed twice, thereby accessing every micro-instruction stored in the micro-instruction ROM. The method includes the further step of comparing data generated by the microprocessor with predetermined data to determine if the microprocessor executes correctly.

Brief Description of the Drawings

Figure 1 is a high level functional block diagram of a microprocessor that can be functionally tested by the method and apparatus of the present invention. Figure 2 is a more detailed functional block diagram of the micro-address unit of Figure 1 , along with other elements of the instruction control unit of Figure 1.

Figures 3A, 3B and 3C form a flow chart illustrating the preferred method of the present invention for performing a functional test of a microprocessor.

Detailed Description of the Preferred Embodiment ■ Fig. 1 is a high-level functional block diagram of a microprocessor 100 that will be used to illustrate the preferred embodiment of the present invention. However, the present invention can also be used with microprocessors having different architectures. In fact, the apparatus and method of the present invention can be used in connection with any microprogrammed processor.

Referring to Figure 1, the microprocessor 100 comprises an execution unit 102, an instruction control unit 1 12, and a memory control unit (MCU) 115. The MCU 115 has a self test detection unit 184 and a counter 186. The instruction control unit 112 comprises an instruction queue 1 14, a macro-instruction decode unit 140, a first cyclical redundancy check (CRC) register 141, a micro-instruction multiplexer 150, a micro-instruction ROM 156, a second CRC register 157, a micro-address unit 161, a micro-instruction register 164, and an instruction queue multiplexer 182. The execution unit 102 is connected to the MCU 115 by an effective address bus 122 and an internal data bus 120. The MCU 115 is connected to external devices (not shown) by an address/control bus 131 and a data bus 132. The MCU 115 is connected to a first data input of the instruction queue multiplexer 182 by a pre-fetch instruction bus 134 and to a control input of the instruction queue multiplexer 182 by a fast fault test line 188. The fast fault test line 188 is also connected to the micro-address unit 161. The execution unit 102 is connected to a second data input of the instruction queue multiplexer 182 by an A result bus 180. An output of the instruction queue multiplexer 182 is connected to an instruction 5 input of the instruction queue 114 by a pre-fetch instruction bus 135. An instruction output of the instruction queue 114 is connected to an instruction input of the decode unit 140 by a next instruction bus 142. An output of the decode unit 140 is connected to a first data input of the micro-instruction multiplexer 150 and to a data input of the CRC register 141 by a micro-instruction bus 152. An output of the micro¬ instruction ROM 156 is connected to a second data input of the micro-instruction multiplexer 150 and to a

10 data input of the CRC register 157 by a micro-instruction bus 158. An output of the micro-instruction multiplexer 150 is connected to a data input of the micro-instruction register 164 by a micro-instruction bus 166. The micro-address unit 161 is connected to the micro-instruction ROM 156 by an address bus 176. The micro-address unit 161 is also connected to a control input of the micro-instruction multiplexer 150 by a selector line 160. A data output of the micro-instruction register 164 is connected to the micro-address

15 unit 161, the execution unit 102, and the MCU 115 by a micro-instruction bus 170.

Figure 2 is a more detailed functional block diagram of the micro-address unit 161 of Figure 1, also including the micro-instruction ROM 156, the micro-instruction multiplexer 150 and the micro-instruction register 164 of Figure 1. The micro-address unit 161 comprises a two-bit LSB counter 200, a test tree multiplexer 202, a micro-address multiplexer 204, a micro-address unit controller 206, an address register

20 208, an incrementer 210, and an address register 212. The micro-instruction register 164 comprises a micro- address command field 240 and a next address field 242, and also includes other fields not described herein. A pair of data outputs of the LSB counter 200 are connected to a two-bit data input of the test tree multiplexer 202 by a pair of LSB counter lines 220. The test tree multiplexer 202 also receives test results from various units of the microprocessor 100 on other data input lines. A pair of outputs of the test

25 tree multiplexer 202 are connected to a pair of address inputs of the micro-instruction ROM 156 by a pair of address lines 222. A set of nine outputs of the micro-address multiplexer 204 is connected to a set of nine address inputs of the micro-instruction ROM 156 by a set of nine address lines 224. The address lines 222 and the address lines 224 form a part of the address bus 176. The nine address lines 224 are also connected to a data input of the address register 208.

30 A data output of the address register 208 is connected to a data input of the incrementer 210 by an address bus 226. A data output of the incrementer 210 is connected to a data input of the address register 212 by an address bus 228. A data output of the address register 212 is connected to a data input of the micro-address multiplexer 204 by an address bus 234. The next address field 242 of the micro¬ instruction register 164 is connected to a data input of the micro-address multiplexer 204 by a set of nine next address lines 236. The micro-address multiplexer 204 may also receive other data inputs from various other micro-address sources. For example, a different micro-address source (not shown) may provide a return address for a micro-code subroutine.

The command field 240 of the micro-instruction register 164 is connected to an input of the micro- address unit controller 206 by a set of micro-address command lines 232. The next address lines 236 and the micro-address lines 232 form a part of the micro-instruction bus 170 (Figure 1). The fast fault test line

188 from the self test detection unit 184 (Figure 1) is also connected to an input of the micro-address unit controller 206.

A first output of the micro-address unit controller 206 is connected to a control input of the micro- address multiplexer 204 by a set of select lines 244. A second output of the micro-address unit controller 206 is connected to a control input of the test tree multiplexer 202 by a set of select lines 246. A third output of the micro-address unit controller 206 is connected to a control input of the address register 208 by a register load line 248. A fourth output of the micro-address unit controller 206 is connected to a control input of the micro-instruction multiplexer 150 by the select line 160. Finally, a fifth output of the micro-address unit controller 206 is connected to a control input of the address register 212 by a register load line 230.

Referring again to Figure 1, during operational mode, the microprocessor 100 generally executes computer programs that are stored in an external memory (not shown) connected to the address/control bus 131 and the data bus 132. The MCU 1 15 fetches macro-instructions from the external memory using the address/control bus 131 and the data bus 132. The MCU 1 15 provides these macro-instructions to the instruction queue multiplexer 182 over the instruction bus 134. During operational mode, the fast fault test line 188 is inactive, which causes the multiplexer 182 to apply the macro-instructions on the instruction bus 134 through to the instruction bus 135 and to the instruction queue 1 14. The instruction queue 114 provides the macro-instructions to the decode unit 140, one at a time, over the instruction bus 142. As the MCU 115 pre-fetches macro-instructions from the external memory, the instructions are stored in the instruction queue 114 until the decode unit 140 is ready for them.

The decode unit 140 generates micro-instructions that are communicated to a first input of the multiplexer 150 over the micro-instruction bus 152. The micro-instruction ROM 156 provides micro¬ instructions to a second input of the multiplexer 150 over the micro-instruction bus 158. The signal on the selector line 160 from the micro-address unit 161 controls the multiplexer 150 to select between the micro¬ instruction buses 152 and 158. The micro-address unit 161 also controls address selection from the micro¬ instruction ROM 156 using the address bus 176 to select specific micro-instructions.

Micro-instructions selected by the multiplexer 150 are communicated to the micro-instruction register 164 over the micro-instruction bus 166. Micro-instructions held by the micro-instruction register 164 are applied to the micro-instruction bus 170. As is well known in the art, a micro-instruction comprises a number of fields that provide instruction data to different units within the microprocessor 100. As shown in Figure 1, different fields of the micro-instruction are provided from the micro-instruction bus 170 to the micro- address unit 161, the MCU 115 and the execution unit 102. In the architecture of Figure 1, for each macro-instruction, the first micro-instruction is generated by the decode unit 140, and subsequent micro-instructions, if any, are provided by the micro-instruction ROM 156. Thus, for the first micro-instruction, the micro-address unit 161 selects the micro-instruction bus 152, allowing the micro-instruction from the decode unit 140 to pass through the multiplexer 150 to the micro¬ instruction register 164. For macro-instructions requiring more than one micro-instruction, the next address field 242 (Figure 2) of the first micro-instruction specifies the address within the ROM 1 6 containing the second micro-instruction. The next address field 242 is provided to the micro-address unit 161 by the next address lines 236 (Figure 2) of the micro-instruction bus 170. For subsequent micro-instructions related to the macro-instruction, the micro-address unit 161 selects address locations within the ROM 156 using the address bus 176. The micro-address unit 161 also controls the multiplexer 150 to select the micro- instruction bus 158 from the ROM 156.

The execution unit 102 provides effective addresses to the MCU 1 15 over the address bus 122. Each effective address specifies a memory location for performing either an instruction fetch or an operand access. The MCU 115 converts the effective addresses into physical addresses. The MCU 1 15 uses the physical address to perform the requested memory access using the address/control bus 131, and the data bus 132. The MCU 115 may optionally include a cache (not shown). If the requested access is an operand read, the requested data is placed on the data bus 120. If the requested access is an instruction fetch, the MCU 1 15 returns the requested code data on the macro-instruction bus 134, and the code data is buffered by the instruction queue 1 14.

Referring to Figure 2, the micro-address unit controller 206 controls address selection for the micro- instruction ROM 156. During normal operation, the micro-address unit controller 206 uses the select lines 244 to select the nine most significant address bits to the micro-instruction ROM 156 from various data inputs to the micro-address multiplexer 204. For example, the micro-address unit controller 206 frequently selects the data input connected to the next address lines 236 so that a subsequent micro-address is obtained from a previous micro-instruction. This address selection allows for sequential execution of micro- instructions, as well as micro-instruction branches and subroutine calls. Other data inputs (not shown) may also be selected to perform other functions, as is well known in the art.

The micro-address unit controller 206 uses the select lines 246 in a similar manner to select the two least significant address bits to the micro-instruction ROM 156 from various data inputs to the test tree multiplexer 202. For example, the micro-address unit controller 206 may cause a micro-instruction branch based on the results of a particular test by selecting the data input of the test tree multiplexer 202 corresponding to the desired test.

The micro-address unit controller 206 controls the address register 208 to load the nine most significant bits of the current micro-address, as required. The incrementer 210 adds one to the value stored 5 in the address register 208 and applies the result to the address bus 228. Adding one to the nine most significant bits stored in the address register 208 effectively adds four to the micro-address represented at the address bus 228. The micro-address unit controller 206 also controls the address register 212 to load the nine most significant bits of the micro-address on the address bus 228. Thus, the micro-address unit controller 206 can cause the most significant address bits in the address register 212 to increment by

10 selecting the data input of the micro-address multiplexer 204 that is connected to the address bus 234, by loading the selected address bits into the address register 208, and by loading the incremented address bits back into the address register 212. In addition, the micro-address unit controller 206 can cause the two least significant address bits to be incremented by selecting the data input of the test tree multiplexer 202 that is connected to the LSB counter line 220. The LSB counter 200 increments every clock cycle. The

15 micro-address unit controller 206 can cause the entire eleven bit micro-address to increment by coordinating the loading of the address registers 208 and 212 so that the incrementing of the address register 212 corresponds with the rolling over of the LSB counter 200 from a value of '1 1' to a value of '00'.

The micro-address unit controller 206 generates signals on the select lines 244, 246 and 160 and on the register load lines 248 and 230 to control the micro-address multiplexer 204, the test tree multiplexer

20 202, the micro-instruction multiplexer 150, the address register 208 and the address register 212, based on the micro-address command lines 232 and the fast fault test line 188. During operational mode, the fast fault test line 188 is inactivate, so that the micro-address unit controller 206 responds to the micro-address command lines 232.

Figures 3A, 3B and 3C form a flow chart illustrating a preferred method of the present invention

25 for performing functional testing on a microprocessor. The method is described in terms of an initial test after wafer manufacture, but before encasing the different dies in packaging material. Typically, an automated test unit is connected to a microprocessor die on a manufactured wafer so that pins of the test unit contact pads of the microprocessor die. The test unit is programmed to activate input signals of the microprocessor die and to monitor output signals of the microprocessor die, as required to perform the

30 method. The method begins at an initial block 300.

The test unit initiates the functional test by resetting the microprocessor 100 and causing the microprocessor 100 to execute a self test. These actions may be executed simultaneously. For example, the test unit may initiate the microprocessor self test by activating a specified input signal of the microprocessor 100 and then activating a reset signal of the microprocessor 100, while the other input signal is still active. At a process block 301, the microprocessor 100 detects the activation of the reset signal and activates an internal reset signal. This microprocessor reset initializes a large portion of the microprocessor circuit to a known state. The first several micro-instructions further initialize the microprocessor 100 so that the outputs generated by the microprocessor 100 are completely deterministic after the first few micro-instructions have been executed. For example, the first several micro-instructions load distinct values into internal registers, such as general purpose registers, segment registers and temporary registers.

At a process block 302, the self test detection unit 184 of the MCU 115 detects the initiation of the self test and asserts the fast fault test line 188 to indicate that a fast fault test is active. The primary purpose of the fast fault test is to test the functionality of a relatively large portion of the microprocessor circuitry in a relatively small amount of time to quickly detect defects in a microprocessor 100.

Upon activation of the fast fault test line 188, the microprocessor 100 begins the fast fault test at a process block 304.

The instruction queue multiplexer 182 and the micro-address unit controller 206 detect the activation of the fast fault test line 188. In response, at a process block 305, the instruction queue multiplexer 182 preferably channels the A result bus 180 through to the instruction queue 114. This results in a more thorough exercise of the logic of the instruction queue 1 14. Typically, the MCU 115 does not fetch any actual instructions for the instruction queue 114 as there is typically no external memory connected to the buses 131 and 132. Consequently, the A result bus 180 provides greater data activity to the instruction queue 114, which increases the likelihood of detecting a fault.

At a process block 306, the microprocessor 100 drives a number of output signals, such as the address/control bus 131 and the data bus 132, to allow external fault detection by the test unit. The microprocessor 100 continues to drive these output signals until the fast fault test is completed. Preferably, the test unit contains a pattern of output data that is generated by fully functional microprocessors during self test mode. During each cycle of the self test, the test unit compares the actual data generated by the microprocessor under test with expected data values. If the test unit detects a mismatch in this comparison, the test unit terminates the testing of the die, indicates that the die is defective (i.e., by marking the die with red ink, or the like), and proceeds to test a subsequent microprocessor die.

At a process block 308, the address register 212 and the LSB counter 200 are cleared to values of zero. The address register 212 and the LSB counter 200 combine to represent a micro-address of zero. As described below, with reference to a process block 314, the micro-address represented by the address register 212 and the LSB counter 200 is preferably incremented by one during each microprocessor clock cycle. The counter 186 in the MCU 1 15 is also cleared to a value of zero, so that the counter 186 is synchronized with the micro-address provided by the address register 212 and the LSB counter 200. As described below, again with reference to the process block 314, the counter 186 is also incremented by one during each microprocessor clock cycle to track the micro-address represented by the address register 212 and the LSB counter 200.

After the process block 308, the method proceeds to a functional loop beginning at a process block 5 310 of Figure 3B. At the process block 310, the micro-address unit controller 206 controls the micro- address multiplexer 204 to select the micro-address bits generated by the address register 212; it controls the test tree multiplexer 202 to select the micro-address bits generated by the LSB counter 200; and it controls the micro-instruction multiplexer 150 to select the micro-instruction generated by the micro-instruction ROM 156. During the first pass through the present loop, the address register 212 and the LSB counter

10 200 combine to select a micro-address of zero. Thus, the micro-instruction multiplexer 150 allows the first micro-instruction in the micro-instruction ROM 156 to be loaded into the micro-instruction register 164. As a result, the microprocessor 100 executes this first micro-instruction. The micro-address unit controller 206 continues to control the micro-address multiplexer 204, the test tree multiplexer 202 and the micro-instruction multiplexer 150 to select the micro-instruction from the micro-instruction ROM 156, as addressed by the

15 address register 212 and the LSB counter 200, until the fast fault test line 188 is deactivated.

At a decision block 312, the self test detection unit 184 determines whether the counter 186 has reached the last address of the micro-instruction ROM 156. If not, the method proceeds to a process block 314. If the last address has been executed, the method proceeds at a process block 316.

At the process block 314, the counter 186 is incremented to point to the next micro-address.

20 Simultaneously, the 2-bit LSB counter 200 is also incremented to point to the next micro-address. Also, the micro-address unit controller 206 controls the address registers 208 and 212 and the incrementer 210 to cause the output of the address register 212 to increment on every fourth pass through the present loop.

As a result, the micro-address represented by both the counter 186 and the combination of the address

. register 212 and the LSB counter 200 sequentially steps through each address in the micro-instruction ROM

25 156, so that each micro-instruction is executed by the microprocessor 100. After the process block 314, the method continues at the process block 310.

During the fast fault test, micro-instructions are generally executed in the same manner as for normal operation. However, all micro-code branches and subroutines are disabled, and execution proceeds sequentially through every micro-instruction from the first one to the last one. As each instruction is

30 executed, the various functional units of the microprocessor perform the functions indicated by the different fields of the micro-instruction. Many instructions require operations to be performed on, for example, internal registers. Under these circumstances, the operations are performed on the values that are stored in the affected registers at the time the instructions are executed. These values are determined by the values that were loaded during initialization and by the sequence of operations that are performed on those values. Duriπg the above-described loop comprising the process blocks 310 and 314 and the decision block 312, a number of CRC registers monitor various internal microprocessor signals. Figure 1 illustrates two CRC registers 141 and 157 that monitor the output of the decode unit 140 and the micro-instruction ROM 156, respectively. These CRC registers 141 and 157 serve as examples of the use of CRC registers to monitor 5 internal signals. The preferred embodiment comprises additional CRC registers (not shown) for monitoring various other internal signals. A person of skill in the art will understand a variety of effective techniques for using a CRC register to monitor a group of signals. The CRC registers combine a series of data values to obtain a result that is dependent on the particular data values provided to the CRC register.

In the preferred embodiment, CRC registers are used to monitor an instruction field of a micro-

10 instruction, an immediate data field of a micro-instruction, a displacement field of a micro-instruction, a hardwired decode of a micro-instruction, a data output of the micro-instruction ROM 156, an ALU result output, an ALU flags output, a set of register file lines, a set of ALU function lines, a set of address limit check result lines and a set of exception status bits.

As indicated above, with reference to the process block 306, a number of output signals are driven

15 by the microprocessor 100 so that the test unit can monitor these output signals for errors. If the test unit detects a single discrepancy between the actual data generated by the die under test and the expected results, the test unit can terminate the testing of the current die and proceed to a subsequent die. Testing of the subsequent die begins at the process block 300.

After the last micro-instruction has been executed and the method proceeds to the process block 20 316, the fast fault test is completed. At this point, the self test detection logic 184 deactivates the fast fault test line 188. As a result, the instruction queue multiplexer 182 selects the pre-fetch instruction bus 134 to supply macro-instructions to the instruction queue 114. In addition, the micro-address unit controller 206 detects the deactivation of the fast fault test line 188 and returns to normal operation. First, the micro- address represented by the address register 212 and the LSB counter 200 is incremented from the last micro- 25 instruction address to an address of zero. Next, the micro-address unit controller 206 controls the multiplexers 204, 202 and 150 to select and execute the first micro-instruction. The micro-address unit controller 206 then responds to the micro-address command field 240 for subsequent micro-addresses.

The first several routines in the micro-instruction ROM 156 implement further aspects of the microprocessor self test. At a process block 318, the micro-code causes the microprocessor 100 to check 30 the CRC registers (eg. 141 and 157) to determine whether they arrived at an expected value after the fast fault test.

At a process block 320, the microprocessor 100 checks a number of internal registers to determine whether they contain expected values after the fast fault test. The registers checked during the process block 320 may include general purpose registers, segment registers and temporary registers. At a process block 322, the microprocessor 100 writes the results of the CRC register check of the process block 318 and the operational register check of the process block 320 to an internal register location so that the results can be checked by a user program. In addition, the microprocessor 100 also attempts to write the results to external memory so that the results can be immediately verified by the test unit. If the test unit detects an error, the self test of the present die is terminated, the die is marked as defective, and functional testing continues with the next microprocessor die.

At a process block 324, the microprocessor 100 performs a comprehensive set of micro-diagnostic tests. For example, one test may cover a translation look-aside buffer, while another test covers an internal cache memory. In combination, the fast fault test and the entire set of micro-diagnostic tests completely test the functionality of the microprocessor die.

At a process block 326, the microprocessor 100 writes the results of the micro-diagnostic tests to a register location so that the results can be checked by a user program. In addition, the microprocessor

100 also attempts to write the results to external memory so that the results can be immediately verified by the test unit. If the test unit detects an error, the self test of the present die is terminated, the die is marked as defective, and functional testing continues with the next microprocessor die.

At a terminal block 328, the self test is completed. The microprocessor 100 now enters a mode of normal operation.

If a microprocessor die completes the fast fault test and the micro-diagnostic tests without any detection of a failure, the microprocessor die is considered fully functional. At this point, testing can continue with the next die.

The apparatus and method of the present invention enables rapid detection of a large number of possible defects in microprocessor dies, without any substantial delay in the completion of a comprehensive functional test of the microprocessor. The above-described fast fault test performs a thorough test of every instruction location in the micro-instruction ROM 156 in a short amount of time because no instruction location is skipped and no instruction location is executed twice. There is no substantial time penalty here because the micro-instruction ROM 156 is tested at a rate of one memory location per clock cycle, and the micro-instruction ROM 156 must be thoroughly tested anyway. In addition, the fast fault test provides a high fault detection coverage of numerous other areas of the microprocessor circuitry without any significant increase in the amount of time required to test the micro-instruction ROM 156 because the fast fault test executes every micro-instruction that will be executed by the microprocessor during normal operation.

The fast fault test is advantageously followed by micro-diagnostic tests that thoroughly test other portions of the microprocessor to detect any faults that may not have been detected by the fast fault test, such as, for example, the branch portions of the instructions that are disabled during the fast fault test. Performing the fast fault test prior to the micro-diagnostic tests substantially reduces the average time required to test microprocessor dies because a relatively large number of defects can be detected in the fast fault test. As soon as a defect is detected, testing of the present die can be terminated and testing of a subsequent die can begin. This substantially reduces the time required to test an entire wafer of microprocessor dies. In addition, using the micro-instructions from the micro-instruction ROM 156 during the fast fault test reduces or eliminates the need for generating test vectors. This substantially reduces the complexity of a test unit that can perform rapid and thorough testing of a microprocessor.

Various embodiments of the present invention have been described above. Although this invention has been described with reference to these specific embodiments, the descriptions are intended to be illustrative of the invention and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A method of rapidly testing the functionality of a microprocessor having an internal micro- coded instruction unit responsive to a micro-instruction read only memory (ROM) in which a next address to be accessed in said micro-instruction ROM is determined by a micro-address controller in response to a next address field from a current micro-instruction, said method comprising the steps of: resetting said microprocessor to a known initial state such that a first known address is applied to said micro-instruction ROM to access a first micro-instruction stored at said first known address; executing said micro-instruction stored in said first known address; generating a second address and all subsequent addresses to said micro-instruction ROM to access respective subsequent micro-instructions stored in said second address and all subsequent addresses by incrementing said first address irrespective of said next address field of said first micro-instruction and irrespective of said next address field of all subsequent micro instructions so that said micro-instruction ROM is addressed sequentially through every address; executing said subsequent micro-instructions to exercise microcode-controlled circuitry of said microprocessor; and monitoring data generated by said microprocessor when executing said first micro-instruction and said subsequent micro-instructions and comparing said data with expected data to verify that said microprocessor is operating correctly.
2. The method as defined in Claim 1, further including the steps of: applying selected data generated by said microprocessor when executing said micro¬ instructions as inputs to at least one cyclical redundancy checker; and comparing a data output from said cyclical redundancy checker with a predetermined data value after sequencing through said subsequent micro-instructions to verify that said selected data generated by said microprocessor are correct.
3. The method as defined in Claim 1, further including the step of applying a fast test enable input signal to said micro-address controller to cause said micro-address controller to ignore said next address field of said current micro-instruction and to apply the next sequential address to said micro-instruction ROM.
4. An apparatus for rapidly self-testing a microprocessor having an execution unit, a micro- instruction read-only-memory (ROM) and a micro-address controller that applies addresses to said micro¬ instruction ROM, said micro-address controller generating next addresses to be applied to said micro- instruction ROM in response to a next address field of a micro-instruction from said micro-instruction ROM, said apparatus comprising: an address incrementer that generates a new address by incrementing the current address by a predetermined value; and an input signal line applied to said micro-address controller, said micro-address controller responsive to an active signal on said input signal line to apply said new address from said address incrementer to said micro-instruction ROM irrespective of a value in said next address field of said micro-instruction so that said micro-address controller applies addresses to said micro-instruction ROM in sequence to cause said microprocessor to execute substantially every micro-instruction in said micro-instruction ROM irrespective of whether the next address field of any micro-instruction would otherwise cause a micro-instruction branch or skip to occur, and to thereby cause substantially all microcode-controlled circuitry of said microprocessor to be exercised.
5. A method of initially testing a microprocessor, comprising the steps of: initializing an address applied to a micro-instruction ROM to a predetermined address location; accessing a first micro-instruction stored in said micro-instruction ROM at said predetermined address location; executing said first micro instruction from said micro-instruction ROM and subsequent micro¬ instructions from said micro-instruction ROM while suppressing micro-instruction branches so that no micro-instruction is skipped and so that no micro-instruction is executed twice, thereby accessing and executing every micro-instruction stored in said micro-instruction ROM; and comparing data generated by said microprocessor from said step of executing with predetermined data to determine if said microprocessor executes correctly.
6. A method of rapidly testing the functionality of a microprocessor that has a micro-instruction ROM, comprising the steps of:
(a) initializing at least one register of said microprocessor with a known data value;
(b) sequentially addressing substantially every micro-instruction stored in said micro¬ instruction ROM;
(c) executing each micro-instruction addressed in step (b) to exercise microcode- controlled circuitry of said microprocessor, said step of executing including the step of performing an operation with respect to said known data value to produce a test data value within said microprocessor; and (d) comparing said test data value with a predetermined data value to determine if said microprocessor functions properly.
7. The method according to claim 6, wherein said step of executing comprises the step of applying a predetermined portion of each micro-instruction addressed in said step (b) to said microcode- controlled circuitry of said microprocessor.
8. The method according to claim 6, wherein said step of executing comprises the step of ignoring a next address portion of each micro-instruction addressed in said step (b) to thereby inhibit branches.
9. The method according to claim 6, wherein said test value is a cyclical redundancy check (CRC) value.
10. The method according to claim 6, further comprising the step of:
(e) when said test data value does not match said predetermined data value, doing each of (i) inhibiting further testing of said microprocessor and (ii) indicating that said microprocessor is defective.
1 1. The method according to Claim 6, wherein said step of executing comprises the step of exercising substantially all of said microcode-controlled circuitry of said microprocessor.
PCT/US1995/001549 1994-02-08 1995-02-08 Method and apparatus for testing the functionality of a microprocessor WO1995022107A1 (en)

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US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
US4920538A (en) * 1985-06-28 1990-04-24 International Business Machines Corporation Method of checking the execution of microcode sequences
US5058007A (en) * 1987-11-05 1991-10-15 Raytheon Company Next microinstruction generator in a microprogram control unit
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation
US5226149A (en) * 1989-06-01 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Self-testing microprocessor with microinstruction substitution

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
US4920538A (en) * 1985-06-28 1990-04-24 International Business Machines Corporation Method of checking the execution of microcode sequences
US5058007A (en) * 1987-11-05 1991-10-15 Raytheon Company Next microinstruction generator in a microprogram control unit
US5226149A (en) * 1989-06-01 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Self-testing microprocessor with microinstruction substitution
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation

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