WO1993003503A1 - High frequency jfet and method for fabricating the same - Google Patents

High frequency jfet and method for fabricating the same Download PDF

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Publication number
WO1993003503A1
WO1993003503A1 PCT/US1992/006182 US9206182W WO9303503A1 WO 1993003503 A1 WO1993003503 A1 WO 1993003503A1 US 9206182 W US9206182 W US 9206182W WO 9303503 A1 WO9303503 A1 WO 9303503A1
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Prior art keywords
pocket
layer
conductivity type
transistor
ion
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PCT/US1992/006182
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French (fr)
Inventor
Adrian I. Cogan
Neill R. Thornton
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Microwave Technology, Inc.
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Publication date
Application filed by Microwave Technology, Inc. filed Critical Microwave Technology, Inc.
Priority to EP19920917188 priority Critical patent/EP0598794A4/en
Publication of WO1993003503A1 publication Critical patent/WO1993003503A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors

Definitions

  • This invention relates generally to junction field effect transistors (JFETs) and in particular to a new process for forming a high power high frequency JFET that has an improved breakdown voltage control, reduced on- resistance, and overdrive capability.
  • JFETs junction field effect transistors
  • JFET 100 The drain of short channel junction field effect transistor (JFET) 100 is a heavily doped region 101 of conductivity type N++. Drain 101 is overlain by a lightly doped epitaxial layer 102 of conductivity type N-. As is known to those skilled in the art, a portion of region 102 functions as the channel of JFET 100. Two pockets 103, 104 of conductivity type P+, with their centers separated by a distance "a" (the device pitch) , extend into epitaxial region 102. Approximately centered between pockets 103, 104 in epitaxial region 102 is a doped source region 105 of conductivity type N+ or N++. An insulating layer 106 (in Fig. 1, a letter is used after reference numeral 106 to identify the different regions of the insulating layer that are visible in the cross-sectional view) overlies surface 102A and has contact openings over pockets 103, 104 and a contact opening over source 105.
  • Metal gate electrodes 110, 112 electrically contact pockets 103 and 104 respectively and overlie insulating layer 106 so that portions of electrodes 110 and 112 which are not in electrical contact with pockets 103 and 104 are electrically insulated from region 102.
  • Source electrode 111 electrically contacts source 105 and also overlies insulating layer 106 so that portions of electrodes 111 which are not in electrical contact with source 105 are electrically insulated from region 102.
  • a passivation layer 113 overlies electrodes 110, 111, 112 and insulating layer 106.
  • Short channel JFET 100 has non-saturated current voltage (I-V) characteristics which are similar to those of a vacuum tube triode.
  • Figure 2 is a graph of the I-V characteristics for short channel JFET 100. The ordinate of the graph is the drain-to-source current in amps (I DS [A]) the abscissa is the drain-to-source voltage in volts (V DS [V]).
  • Curves 201, 202, 203, 204, and 205 are for gate-to-source voltages (V GS [V]) of 0, -2, -4, -6, and -8 volts respectively.
  • the drain current of JFET 100 (Fig. 1) is controlled by the (negative) gate potential, as well as the
  • Short channel JFET 100 is a majority carrier device with high internal electric fields that exhibits a large number of favorable electrical and radio frequency characteristics (TABLE I) . Only majority carriers (electrons) flow in the short channel of JFET 100 (Fig. 1) . Hence, JFET 100 operates at high frequencies because no minority carrier effects are present to slow its operation.
  • Blocking voltage 120 V.
  • short channel JFET 100 provides enhanced performance over equivalent bipolar and MOS transistors
  • short channel JFET 100 is limited by the on- resistance, power overdrive capability, and process limitations that affect breakdown voltage. Techniques for enhancing each of these characteristics are known, but the techniques are generally not applicable to high frequency high power short channel JFET 100. Specifically, the techniques degrade either or both of the power and frequency capability of JFET 100. Therefore, applications of JFET 100 are limited to those applications were the on- resistance, power overdrive and breakdown voltage limitations are not of concern. Unfortunately, in most high power high frequency applications, all of these factors are of concern.
  • the overdrive capability, the breakdown voltage capability and the on-resistance of a unipolar transistor are improved over the prior art unipolar transistors.
  • the on- resistance is decreased by ion-implanting an insulating layer covering a layer that contains the source and gate regions of the unipolar transistor.
  • the ions used are selected so that after implantation the ions maintain their charge both during and after all the subsequent processing steps. This is an important aspect of the invention because if the implanted ions undergo recombination either during or after the subsequent processing, the improvement in on-resistance is lost.
  • the charge of the implanted ions is the same as the charge polarity of the gate regions.
  • the ions are selected from the group of negatively charged ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) .
  • the iodine ion is used.
  • the ions are selected from the group of positively charged ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals. These ions are in family IA of the periodic chart. Preferably, the cesium ion is used.
  • a novel unipolar transistor with the lowered on- resistance includes a support of a first conductivity type.
  • a layer of the first conductivity is disposed on the support.
  • the layer includes a first pocket having a second conductivity type, i.e, a gate region, separated from a second pocket having said first conductivity type, i.e., a source region. Both the first and second pockets extend into said layer from a surface of the layer.
  • An ion-implanted insulating layer is disposed on the surface of the layer in the region separating the first pocket from the second pocket.
  • the transistor is a vertical transistor.
  • the ions in the insulating layer attract charge carriers of the opposite polarity to the interface between the layer and the insulating layer.
  • the charge carriers of the opposite polarity decrease the size of the depletion zone near the interface and create a higher density of charge carriers in the channel region of the unipolar transistor. Both of these effects reduce the on- resistance of the transistor.
  • a region of conductivity opposite to the conductivity of the gate region is formed in the gate region of the transistor. This region of opposite conductivity creates another junction within the gate region.
  • the gate region has two junctions, i.e, the junction between the region of opposite conductivity and the gate region, and the junction between the gate region and the layer containing the gate region.
  • the second junction within the gate region of this invention prevents the gate-to-source junction from becoming forward biased until higher gate voltages are applied and thereby provides increased overdrive capability in comparison to prior art JFETs.
  • the gate of the JFET of this invention has two back-to-back diodes such that one of the diodes is always reverse biased. Consequently, the gate of the JFET has a significantly greater power handling capability.
  • a transistor with improved overdrive capability includes a support of a first conductivity type.
  • a layer of the first conductivity type is disposed on the support so that the layer has a surface opposite to the support.
  • the layer contains a first pocket having a second conductivity type with (i) an upper surface that is a first predetermined distance from the surface of the layer and (ii) a lower surface that is a second predetermined distance from said surface of the layer.
  • the lower surface forms a first junction between the first pocket and the layer.
  • the layer also contains a second pocket having the first conductivity type where the second pocket extends from the surface of the layer into the layer the first predetermined distance and contacts the first pocket so that a second junction is formed between the first and second pocket.
  • the two pockets within the layer are the gate region with the two junctions, i.e., the two back-to- back diodes, described above.
  • a new method is used to form a guard ring surrounding the active area of a JFET, according to the principles of this invention.
  • the JFET formed using this method has a guard ring of a second conductivity type, i.e., a pocket, extending a first distance Dl into a layer having (i) a first conductivity type and (ii) a gate region of the second conductivity type extending a second distance D2 into the layer.
  • the method of this invention allows selection of the first and second distances Dl, D2 to optimize the breakdown voltage and performance of the JFET of this invention.
  • the guard ring and the gate regions are formed in different processing steps.
  • the method for improving the breakdown voltage of a vertical transistor having a drain region and an active area that includes a source region includes the steps of (i) implanting a guard ring region that surrounds an active area of the transistor with ions of a first conductivity type in a first processing step; and (ii) implanting a gate region within the active area of the transistor with ions of the first conductivity type in a processing step different from the first implanting step so that the characteristics of the gate region and the characteristics of the guard ring region are determined different processing steps.
  • a preferred embodiment of the method includes: depositing a masking material over a layer of a first conductivity type; forming openings in the masking material so that the openings surround an area in which the source and gate regions of the transistor are formed in subsequent processing steps; implanting ions of a second conductivity type in the layer through the openings to form a guard ring implant region; forming an insulating layer over the layer; creating openings in the insulating layer to expose surface areas of the layer that will become said gate regions of the transistor; and implanting ions of a second conductivity type in the layer through the openings whereby the gate region is formed with characteristics different from the characteristics of the guard ring region.
  • ions are implanted in the insulating layer so that the implanted ions surround the ends of the gates regions.
  • the ions have a charge polarity opposite to the charge polarity of the gate region.
  • the ions are selected from the group of negatively charged ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) .
  • the iodine ion is used.
  • the ions are selected from the group of positively charged ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals. These ions are in family IA of the periodic chart. Preferably, the cesium ion is used.
  • a transistor having an improved breakdown voltage has a sup ⁇ port of a first conductivity type, e.g., a drain region.
  • a layer of the first conductivity type is disposed on the support so that the layer has a surface opposite to the support.
  • a first pocket having a second conductivity type is included within the layer.
  • the pocket has (i) a lower surface a first predetermined distance from the surface of the and (ii) a first end and a second end, e.g., the pocket is the gate region of the transistor.
  • a second pocket having the first conductivity type is also included in the layer.
  • the second pocket extends from the surface a second predetermined distance into the layer.
  • the second pocket is the source region.
  • An ion-implanted insulating region surrounds the first and second ends of the first pocket and the ions have a charge polarity opposite to the charge polarity of the first pocket thereby improving the breakdown voltage of the transistor, as described above.
  • Each of the transistors of this invention have the same basic features sizes.
  • the different embodiments may be intermixed to obtain a unipolar transistor having specific characteristics.
  • a JFET having a gate region and a guard ring with different depths and an ion-implanted layer where the ions have the same charge polarity as the charge polarity of the gate region may be formed.
  • This JFET has an improved breakdown voltage and a reduced on-resistance in comparison to prior art JFETs.
  • the different depth guard ring and gate region may be combined with the dual junction gate region to obtain a JFET with improved breakdown voltage and improved overdrive capability. If the insulating layer of this JFET is implanted with ions having the same charge polarity as the charge polarity of the gate region, the JFET also has a reduced on-resistance.
  • Figure 1 is a cross sectional view of a prior art short channel JFET.
  • Figure 2 is a graph of the current-voltage characteristics of the short channel JFET of Figure 1.
  • Figures 3A and 3B are a cross sectional view of a short channel JFET with a ion-implanted insulating layer that reduces the on-resistance in comparison to the JFET of Figure 1.
  • Figure 4 includes a cross sectional view of a prior art short channel JFET and the short channel JFET of this invention with the improved on-resistance and a comparison of the channel widths of the two JFETs.
  • Figure 5A is a cross sectional view of a short channel JFET with an additional junction in the gate region that provides enhanced overdrive capability in comparison to the JFET of Figure 1.
  • Figure 5B is an equivalent circuit for the JFET of Figure 5A.
  • Figure 5C is a graph of drain-to-gate current vs. drain-to-gate voltage for JFET 100 of Figure 1 and JFET 500 of this invention.
  • Figure 5D is a graph of capacitance vs. gate voltage for JFET 100 of Figure 1 and JFET 500 of this invention.
  • Figure 6 is a short channel JFET according to the principles of this invention that has improved overdrive capability and a reduced on-resistance in comparison to the JFET of Figure 1.
  • Figure 7 is a cross sectional view of a short channel JFET according to the principles of this invention that has a guard ring and gate regions that are formed in different processing steps so that the characteristics of the guard ring and the gate regions may be tailored for optimum performance.
  • Figures 8A and 8B are a top view and a cross- sectional view respectively of a prior art short channel JFET.
  • Figures 8C and 8D are a top view and a cross sectional view respectively of the prior art JFET of Figures 8A and 8B with a guard ring that is used to increase the breakdown voltage overdrive capability.
  • Figure 9 is a top view of another prior art short channel JFET that illustrates the guard ring source metalization and gate metalization along with the oxide layers that are required to prevent shorting of the metal layers.
  • FIGS 10A-10F illustrate the major processing steps according to the principles of this invention that are used to form the JFET of Figure 7.
  • Figure 11 is a graph of the current-voltage characteristics of the JFET of this invention.
  • Figure 12A is a graph of the input power in watts to the output power in watts at 800 MHZ and case temperature of 25° C for drain-to-source voltages of 40, 50, 60, and 70 volts for the JFET of this invention.
  • Figure 12B is a graph of the output power and power efficiency of the JFET of this invention as a functioning of positive drain supply voltage.
  • Figures 13, 14 and 15 are illustrative examples of bias circuits that may be used with the JFET of this invention in a common gate configuration.
  • Figure 16 is a push-pull bias circuit that may be used with another embodiment of the JFET of this invention.
  • Figures 17A-17G illustrate a method for improving the breakdown voltage of prior art JFETs using a ion-implanted insulating layer at the periphery of the gate regions.
  • Figure 18 is a cross sectional view of one embodiment of a JFET of this invention having a reduced on-resistance and an improved breakdown voltage in comparison to the JFET of Figure 1.
  • Figure 19 is a cross sectional view of another embodiment of the JFET of this invention that has enhanced overdrive capability and breakdown voltage performance in comparison with the JFET of Figure 1.
  • Figure 20 is yet another cross sectional view of a JFET according to the principles of this invention having an improved breakdown voltage, a reduced on-resistance, and an improved overdrive capability in comparison to the JFET of Figure 1.
  • JFET 300 A first embodiment of a novel short channel junction field effect transistor (JFET) 300 with a reduced on- resistance in comparison to JFET 100 is illustrated in Figure 3A.
  • the drain of JFET 300 is a heavily doped region 301 of a first conductivity type, preferably a silicon substrate of conductivity type N++. Drain 301 is overlain by a lightly doped layer 302 of the first conductivity type, preferably an epitaxial layer of conductivity type N-. A portion of region 302 functions as the channel of JFET 300.
  • epitaxial layer 302 has a thickness in the range of about 2 micrometers ( ⁇ m) to about 20 ⁇ m and is preferably about 10 ⁇ m thick.
  • ⁇ m micrometers
  • thickness refers to the distance in a direction perpendicular to the support, e.g., substrate 301, of the JFET.
  • Two pockets 303, 304 of a second conductivity type extend from the surface 302A of region 302 into epitaxial region 302A a first predetermined distance.
  • pockets 303, 304 are conductivity type P+.
  • Surface 302A is the surface opposite surface 302B of epitaxial region 302 that contacts drain 301.
  • the JFET pitch defines a unit cell that may be replicated to obtain JFETs with 5 varying power handling capability.
  • a pocket 305 of the first conductivity type e.g., a doped source region, which in this embodiment is conductivity type N+.
  • Source region 305 extends from surface 302A a second
  • the second predetermined distance is less than the first predetermined distance.
  • the first predetermined depth i.e., the depth of regions 303, 304 in layer 302 is in the
  • the concentration of dopant atoms in pockets 303 and 304 is about 10 15 to 10 20 atoms/cm 3 and preferably about 10 19 atoms/cm 3 .
  • the second predetermined depth i.e., the depth of
  • 20 region 305 in layer 302 is about 0.1 ⁇ m to 1 ⁇ m and preferably about .25 ⁇ m.
  • the concentration of dopant atoms in pocket 305 is in the range of about 10 18 to 10 21 atom/cm 3 and preferably about 10 21 atoms/cm 3 .
  • Layer 302 is the range of 4 ⁇ m to 40 ⁇ m thick, preferably about 8 ⁇ m,
  • 25 has a resistivity in the range of 0.5 ⁇ -cm to 40 ⁇ -cm and preferably about 4 ⁇ -cm.
  • Ion-implanted insulating layer 306 is implanted with an ion having the same charge polarity as pockets 303, 304, i.e., the same charge polarity as the charge polarity of the conductivity type of the gate regions. Insulating
  • 35 layer 306 has a thickness in the range of 0.1 ⁇ m to 2 ⁇ m, preferably about 0.7 ⁇ m, and has an ion-implant charge dose of 10 11 cm “2 to 10 14 cm “2 and preferably about 10 12 cm” 2 .
  • the positively charged ions are cesium ions.
  • the positively charged ions preferably may be any ion selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals.
  • the insulating layer is implanted with negatively charged ions.
  • the negatively charged ions preferably may be any ion selected from the group of ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) .
  • the iodine ion is used.
  • the ions used are selected so that after implantation the ions maintain their charge both during and after all the subsequent processing steps. This is an important aspect of the invention because if the implanted ions undergo recombination either during or after the subsequent processing, the improvement in on-resistance is lost.
  • Gate electrodes 310, 312 electrically contact pockets 303 and 304 respectively and overlie ion-implanted insulating layer 306 so that portions of electrodes 310 and 312 which are not in electrical contact with pockets 303 and 304 are electrically insulated from region 302.
  • gate electrodes 310, 311 are one metal selected from the group of metals consisting of aluminum and PtSi/TiW/Al.
  • Source electrode 311 electrically contacts source region 305 and also overlies ion-implanted insulating layer 306 so that portions of electrodes 311 which are not in electrical contact with source 305 are electrically insulated from region 302.
  • Source electrode 311 is also preferably selected from the group of metals described above.
  • electrodes 310, 311, 312 may be formed from any conductive material and the source and gate electrodes may be formed of different materials.
  • a passivation layer 313 overlies electrodes 310, 311, 312 and ion-implanted insulating layer 306.
  • the width of the opening in layer 306 for the source and drain contacts i.e., distance "a", (Fig.
  • 3B is in the range of 0.5 ⁇ m to 5 ⁇ m and preferably about 0.8 ⁇ m.
  • Cell 300 is symmetrie about center line 350 of the cell as illustrated in Figure 3A. Therefore, in this embodiment device pitch x is in the range of 2.6 ⁇ m to 22 ⁇ m and preferably about 3.6 ⁇ m.
  • the on-resistance of JFET 300 is reduced in comparison to a similar JFET which does not have the ion- implanted insulating layer.
  • JFET 100 has depletion regions 121, 122 (See Figure 4.
  • Figure 4 is an enlarged view of JFET 300 with the depletion region of JFET 100 shown for comparison) .
  • the boundaries of depletion regions 121, 122 for JFET 100 in epitaxial layer 302 are shown by the broken line in Figure 4.
  • the channel of JFET 100 is the region extending from drain 101 to source 105 between depletion regions 121, 122.
  • channel width w of transistor 100 determines the on- resistance of JFET 100.
  • Prior art techniques to modify channel width w and thereby reduce the on-resistance of JFET 100 included field plates and biasing methods. For example, the on- resistance is reduced by forward biasing the gate-source junction below its turn-on point. However, this requires an additional gate voltage and may accidentally turn-on the junction thereby destroying JFET 100 through excess current.
  • Field plates may be used to produce an electric field that attracts charge carriers, i.e., electrons, into the depletion region thereby increasing the channel width which in turn reduces the on-resistance.
  • charge carriers i.e., electrons
  • field plates require additional space which in turn increases the JFET gate-to-source distance.
  • the JFET performance decreases.
  • the frequency response of the JFET is directly related to the size of the JFET.
  • the ion-implanted insulating layer of this invention overcomes the shortcomings of the prior art techniques for reducing the on-resistance of JFET 300.
  • the ion- implanted insulating layer permits construction of smaller feature, high density devices. With smaller features, the frequency response of JFET 300 improves. Thus, ion-implanting the insulating layer improves both the on-resistance and the frequency response of prior art JFET 100.
  • Ion-implanted insulating layer 306 creates an electric field between source region 305 and layer 306.
  • the electric field causes electrons to be transported from source 305 and to accumulate at silicon dioxide-silicon interface 302A. These excess electrons repopulate the edge of the depletion region thereby effectively reducing the size of depletion regions 320, 321 near interface 302A for a given gate-to-source voltage, i.e, the depletion region is reduced by the permanent positive electrical charge at the silicon dioxide-silicon interface.
  • the decrease in the size of the depletion region results in an increase in width "w*" of the channel region which in turn results in an increase in the current path between source 305 and drain 301.
  • channel width w* of JFET 300 is greater than channel width w of JFET 100.
  • the increased current path improves, i.e., lowers, the on- resistance of JFET 300 over JFET 100.
  • JFET 300 of this invention requires a smaller channel width than prior art JFET 100.
  • JFET 300 may be constructed with smaller 5 features which results in the improved density and frequency performance. Further, the lower specific on- resistance (per area) enables better use of the silicon "real estate.”
  • a heavily doped region 501 preferably a silicon substrate of a first conductivity, e.g., conductivity type N++, functions as the drain of
  • Drain 501 is overlain by a lightly doped layer 502 of the first conductivity type and is preferably an epitaxial layer of conductivity type N-. A portion of region 502 functions as the channel of JFET 500.
  • pockets 503, 504 are conductivity type P+.
  • Surface 502A is the surface opposite surface 502B of epitaxial region 502 that contacts drain 501.
  • device pitch xx is the same as device pitch x
  • JFET 300 has a feature sizes and other characteristics of JFET 300. Similarly, the feature sizes and other characteristics of JFET 300 are the same as those of JFET 500.
  • each pocket 503, 504 is a region 515, 517 of the first conductivity type N+ that extends into pocket
  • a doped source region 505 of the first conductivity type which in this embodiment is conductivity type N+.
  • source region 505 extends from surface 502A the second predetermined distance into region 502.
  • the second predetermined distance is less than the first predetermined distance.
  • An insulating layer 506, preferably silicon dioxide, overlies surface 502A and has contact openings over pockets 503, 504 and a contact opening over source 505.
  • Gate electrodes 510, 512 electrically contact pockets 516 and 517 respectively and overlie insulating layer 506 so that portions of electrodes 510 and 512 which are not in electrical contact with pockets 516 and 517 are electrically insulated from region 502.
  • gate electrodes 510, 511 are one metal selected from the group of metals described above for transistor 300.
  • Source electrode 511 electrically contacts source 505 and also overlies insulating layer 506 so that portions of electrodes 511 which are not in electrical contact with source 505 are electrically insulated from region 502.
  • Source electrode 511 is also preferably selected from the group of metals described above.
  • electrodes 510, 511, 512 may be formed from any conductive material and the source and gate electrodes may be formed of different materials.
  • a passivation layer 513 overlies electrodes 510, 511, 512 and insulating layer 506. The dimensions and doping concentrations of JFET 500 are the same as those of JFET 300 which are incorporated herein by referenc .
  • the gate-to- source junction may become forward biased when the source input signal increases above a certain threshold or power level, i.e, JFET 100 is overdriven.
  • the junction injects minority carriers into the drain-to-source channel. Consequently, unipolar JFET 100 becomes a bipolar transistor, i.e, the input signal has exceeded the bipolar turn-on threshold and JFET 100 may be destroyed by excess current.
  • a bipolar transistor has a slower response than a unipolar transistor such as JFET 100. To prevent the bipolar mode, the power level of JFET 100 must be maintained, i.e., limited, so that JFET 100 in not driven over the bipolar turn-on threshold.
  • the second n-p junction 515A, 517A in gate regions 503, 504 of JFET 500 prevents the gate-to-source junction from becoming forward biased until higher gate voltages are applied and thereby provides increased overdrive capability in comparison to JFET 100.
  • an equivalent circuit for unipolar transistor 500 (Fig. 5A) is illustrated in Fig. 5B.
  • the gate of JFET 500 has two back-to-back diodes 524, 525 such that one of the diodes is always reverse biased. Consequently, the gate of JFET 500 has a significantly greater power handling capability.
  • the bipolar turn-on threshold is increased from about the 0.6 volts of JFET 100 to several volts, typically about 2 to 3 volts, i.e., the breakdown-voltage of diode 524, or even higher as illustrated in Figure 5C.
  • the increase in the bipolar turn-on voltage also results in an increase of the capacitance "turn-on" voltage as shown in Figure 5D.
  • the second diode does not affect normal operation of JFET 500 because a JFET has a very high input impedance, typically several megohms.
  • the impedance of the second diode only changes the JFET input impedance by a small amount, e.g., about 10 percent.
  • JFET 600 has both a reduced on-resistance and an enhanced power overdrive capability in comparison to prior art JFET 100.
  • the breakdown voltage of JFET 100 is increased using a novel processing method to form a JFET 700 (Fig. 7) with a guard ring 750, 751 of P conductivity type extending a first distance Dl into epitaxial layer 702 and gate regions 703, 704 of P conductivity type extending a second distance D2 into epitaxial layer 702.
  • First and second distances Dl, D2 are selected to optimize the breakdown voltage and performance of JFET 700.
  • distance D2 is in the range of 0.5 ⁇ m to 10 ⁇ m, and preferably about 2.5 ⁇ m.
  • the distance Dl is in the range of 0.5 ⁇ m to 10 ⁇ m, and preferably about 3 ⁇ m.
  • FIG. 1 A top view and a cross-sectional view of a prior art JFET 800 without a guard ring are presented in Figs. 8A and 8B respectively.
  • Gate regions 803, 804 and source region 805 of JFET 800 are substantially similar to the equivalent regions of JFET 100.
  • JFET 800 is constructed using the basic cell structure of JFET 100. Specifically, JFET 800 has two gate regions 803, 804 of P+ conductivity type and a source region 805 of N+ conductivity type formed in an epitaxial layer 802 of conductivity type N-.
  • JFET 800A with a guard ring 850 are illustrated in Figs. 8C and 8D respectively. Specifically, JFET 800A still has two gate regions 803, 804 of P+ conductivity type and a source regions 805 of N+ conductivity type formed in an epitaxial layer 802 of conductivity type N-. However, gate regions 803, 804 are now directly connected by regions 810, 811 of P+ conductivity type.
  • Guard ring 850 is a diffused region of P+ conductivity type that 5 surrounds source regions 805 and gate regions 803, 804, 810, 811.
  • guard ring 850 (Fig. 8C) is formed in the same process step as gate regions 803, 804 (Figs. 8C and 8D) so that guard ring 850 and gate regions 803, 804
  • guard ring 850 and gate diffusion regions 803, 804 are not possible.
  • the depth of the guard ring in region 802 and distance "d" determine the breakdown voltage
  • Guard ring 850 introduces another problem.
  • JFET 800A are separate gate and source metalization fingers. If both metal contacts electrically contact guard ring 850, the metal contacts will be shorted.
  • JFET 900 (Fig. 9) has four source
  • JFET 900 is constructed using unit cell 100 (Fig. 1). Gate metalization fingers 941, 942, 943, 944, 945 of gate contact 940 electrically contact gate regions
  • Source metalization fingers 931, 932, 933, 934 of source contact 930 electrically contact source regions 906, 907, 908, 909, respectively.
  • a separate masking step is required in the fabrication process to define insulating layers 950, 960 that insulate the overlying metal contact from the underlying guard ring 920.
  • a second insulating layer i.e., a low temperature oxide
  • a masking step is required to pattern the low temperature oxide layer to form regions 950, 960. This masking step increases both production time and production costs of the JFET. Thus, the improvement in breakdown voltage comes at the expense of additional processing steps.
  • the breakdown voltage of prior art JFET 100 is enhanced by using separate masking steps to form the guard ring and the gate regions thereby eliminating the separate mask step required in the prior art to form the insulating layer between the guard ring and the source and gate contacts.
  • the elimination of that mask step reduces the production cost of the JFET and in addition, the novel process of this invention provides for adjusting the guard ring diffusion and the gate diffusions for optimum breakdown voltage and performance.
  • the formation of the JFET starts with an N+ silicon substrate with a resistivity in the range of 0.001 to 0.01 ohm-cm.
  • the substrate is processed to form an N++ substrate using standard industry techniques.
  • Epitaxial layer 702 of conductivity type N- is grown on the substrate using a conventional chemical vapor deposition process.
  • Epitaxial layer 702 has a thickness in the range of 4 ⁇ m to 40 ⁇ m preferably about 8 ⁇ m, and a resistivity in the range of 0.5 ⁇ -cm to 40 ⁇ -cm preferably about 4 ⁇ -cm.
  • a mask layer, preferably silicon nitride (Si 3 N 4 ) is deposited on silicon dioxide layer 1001 and a photoresist layer is then deposited on the mask layer.
  • the photoresist layer is processed in a standard fashion so that only the portions of silicon nitride mask layer 1002, 1003, 1004 that cover the areas of epitaxial layer 702 that will become the source and gate regions are covered.
  • a standard chemical wet etch is then used to remove the portion of the silicon nitride layer that is not protected by the photoresist.
  • a plasma or RIE etch may also be used. After the etch, the photoresist is removed.
  • the result of the first mask step is the structure illustrated in Figure 10A.
  • the distance between the centers of silicon nitride portions 1002, 1004 defines the JFET pitch.
  • a second mask step is used for the guard ring implantation.
  • a photoresist 1005 is deposited on the structure of Figure 10A and openings 1007, 1008 for the guard ring implant are formed in a conventional fashion.
  • the width of the guard ring implant opening is the range of 0.5 ⁇ m to 5 ⁇ m preferably about 1 ⁇ m.
  • Edge 1006A1 of masking opening from the guard ring implant is a distance n d u from edge 1002A of silicon nitride 1002 is in the range of 1 ⁇ m to 15 ⁇ m and preferably about 6 ⁇ m.
  • a boron implantation 1006A, 1006B is used in this embodiment to form P+ pockets that will become the guard ring after drive in.
  • the boron implantation uses a flux in the range of 10 12 cm" 2 to 10 15 cm” 2 preferably 10 13 cm “2 with an energy of 30 Kev to 150 Kev, preferably 60 Kev.
  • photoresist 1005 is removed using standard processes.
  • the implant is driven in using a temperature in the range of 950 °C to 1150 °C for about 0 hours to 3 hours. In one embodiment, a temperature of about 1100 °C for about one hour was used.
  • the process parameters affect only the guard ring implant.
  • the guard ring and gate implants were formed simultaneously so that the characteristics of the guard ring were primarily determined by the implant required to form the gate region.
  • the gate junction depth affects the device gain, transconductance, and maximum frequency.
  • the process of this invention decouples the gate and guard ring processing steps thereby allowing each step to be tailored for optimal performance.
  • a thicker silicon dioxide layer 706 is grown and in the process, the guard ring implant is simultaneously further driven in.
  • This step utilizes conventional processes such as "local oxidation” or “selective oxidation” using the silicon nitride as an oxidation mask. Subsequently, the silicon nitride is removed to form the structure of Fig. 10B.
  • Silicon dioxide layer 706 has a thickness in the range of 0.1 ⁇ m to 2 ⁇ m and preferably about 0.7 ⁇ m.
  • a third mask step is used for the gate implantation.
  • a photoresist is deposited on the structure of Figure 10C and all of the photoresist except portion 1015 covering source opening 1011 is removed in a conventional fashion.
  • a boron implantation 1016A, 1016B is used to form P+ conductivity pockets that form the gate regions.
  • the boron implantation uses a flux in the range of 10 12 cm" 2 to 10 15 cm" 2 , preferably 2xl0 13 cm" 2 with an energy of 30 Kev to 150 Kev, preferably 60 Kev.
  • photoresist 1015 is removed using standard processes, and the implant is driven in at a temperature in the range of 950 °C to 1150 °C, preferably about 1100 °C, for a time in the range of 15 minutes to three hours, preferably about 45 minutes.
  • a fourth mask step is used for the source implantation.
  • a photoresist is deposited on the structure of Figure 10D without layer 1015 and all of the photoresist except portions 1020, 1021 covering gate openings 1010, 1012, respectively, is removed in a conventional fashion.
  • an arsenic implantation 1021 is used to form the N+ conductivity pocket that becomes the source region.
  • the arsenic implantation uses a flux in the range of 10 w cm "2 to 10 16 cm" 2 , preferably about 5xl0 15 cm 2 , with an energy of 15 Kev to 100 Kev preferably about 25 Kev.
  • photoresist 1020, 1022 is removed using standard processes and the implant is annealed at a temperature in the range of 500 °C to 1000 °C for 30 seconds to 100 minutes and preferably about 950 °C for about 45 minutes.
  • metal electrodes 710, 712 to gate region 703, 704 and a metal electrodes 711 to source region 705 are formed using conventional processes.
  • a silicon dioxide passivation layer is deposited over the structure to obtain JFET 700 using conventional techniques.
  • the JFET of this invention with a guard ring formed by the novel process described above has at 1 GHz approximately the following normalized characteristics per gate width (note that the JFET does not include any ion-implanted insulating regions) : Power " 10 watts/cm On-resistance R ⁇ ⁇ 25 ⁇ cm
  • Breakdown voltage V GD 135 volts Transconductance (g m ) " 75 mS/cm Breakdown voltage V GD " 90 volts without guard ring
  • JFET 700 is obtained with a significantly enhanced breakdown voltage performance in comparison to JFET 100.
  • JFET 700 operates as a depletion mode FET and requires biasing conditions similar to a
  • MESFET e.g., negative voltage to the gate and positive voltage to the drain.
  • a negative gate voltage is required to turn off JFET 700.
  • JFETs 300, 500 and 600 also operate in this manner.
  • JFET 700 operates over a wide range of drain voltages, and can operate CW at drain supply voltages as high as 80 volts. As illustrated in the I-V curves of
  • Maximum CW power for single-ended JFETs of this invention is 120 watts(W) or higher at 1000 megahertz(MHz) with a single frequency power gain of 10 decibels(dB) or higher. (Herein, "single-ended” is used to distinguish from “push-pull” operation.)
  • Figure 12A is a graph of input power in watts PI(W) to output power in watts
  • JFET 700 is operated in a common gate configuration to take advantage of the highest frequencies at which JFET 700 still has high power gain.
  • JFET 700 When operated in a common gate configuration, JFET 700 exhibits a single frequency power gain of higher than 10 dB at frequencies as high as 1000 MHz, because JFET 700 has high transconductance of 1 to 2 S coupled with a low common gate feedback capacitance( ⁇ 0.1 pf/W) .
  • Figures 13, 14, 15 Three basic bias circuits for a DC biased common-gate JFET 700 which permit high RF gain operation are illustrated in Figures 13, 14, 15.
  • Figure 13 has gate G of JFET 700 DC and RF grounded.
  • the gate bias voltage develops across the PNP power bipolar transistor(BJT)/Zener diode (DZ) combination.
  • Bias circuit 1300 (Fig. 13) requires only one power supply.
  • the Zener diode DZ is selected to operate JFET 700 in one of Classes A, AB, B or C.
  • Zener diode DZ may be replaced with a resistive voltage divider connected between positive drain power supply voltage V DD and ground. With the resistive voltage divider, the gate voltage may be continuously adjusted for optimal operation.
  • a DC voltage component is applied between the base of PNP transistor BJT and ground. In such applications, the linear power gain of JFET 700 is adjustable over a range of about 18 dB.
  • the bias circuit shown in Figure 14 separates the DC ground from the RF ground by DC floating the drain power supply V DD .
  • a second power supply V SG is required to provide the gate-to-source voltage. This bias circuit eliminates power dissipation in the gate biasing supply, but requires DC floating of the drain power supply.
  • One family of RF packages widely used in the industry has the input(source) and output(drain) leads positioned between four common leads(gate).
  • the bias circuit shown in Figure 15 is used with JFET 700 in such a RF package.
  • gate G is RF grounded while source S is DC grounded.
  • the physical implementation of this circuit requires four low-profile planar capacitors to be mounted under the package common leads. Typical values of these capacitors range from 10 pF through 1000 pF.
  • JFET 700 In another family of RF packages widely used in the industry has a push-pull eight lead version of JFET 700. This package has two input (source) leads SI, S2, two output (drain) leads Dl, D2, and two pairs of common leads (gates) Gl, G2.
  • a bias circuit for this embodiment of JFET 700 is illustrated in Figure 16. This bias circuit provides RF and DC ground separation.
  • a new JFET 700 with a diffused guard ring was used to enhance the breakdown voltage.
  • the breakdown voltage is enhanced without use of a guard ring.
  • ions, having a charge opposite to the conductivity of the gate region are implanted in the insulating layer, preferably silicon dioxide, at the periphery of the gate implant region.
  • the insulating layer preferably silicon dioxide
  • P+ conductivity type pockets 1701, 1703, 1705 are the gate pockets in an epitaxial layer and N+ conductivity type pockets 1702, 1704 are the source pockets in the epitaxial layer.
  • Ends 1701A, 1701B, 1703A, 1703B, 1705A, 1705B of pockets 1701, 1703, 1705 are directly overlain by an insulating layer.
  • this is the insulating layer overlying the surface of the epitaxial layer which has contact openings for the gate and source electrodes.
  • ions having a charge opposite to charge of the gate pockets are implanted in regions 1707, 1708 (Fig. 17B) .
  • the implanted regions extend a predetermined distance nl beyond the ends of the gate pockets and a predetermined distance n2 along the gate pocket so that ion-implanted regions 1707 and 1708 surround the ends of the gate pockets.
  • Both distances nl and n2 are in the range of 2 ⁇ m to 10 ⁇ m and preferably about 5 ⁇ m.
  • the ions are an iodine ion- implantation that uses a flux in the range of 10 10 cm “2 to 10 14 cm” 2 , preferably 10 12 cm “2 , with an energy of 10 Kev to 100 Kev, preferably 20 Kev.
  • the negatively charged ions preferably may be any ion selected from the group of ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) .
  • the implanted ions are positively charged.
  • the positively charged ions preferably may be any ion selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals. These ions are in family IA of the periodic chart.
  • P+ conductivity type pockets 1711, 1713, 1715 are the gate pockets in an epitaxial layer and are joined by P+ conductivity type pockets 1716, 1717.
  • N+ conductivity type pockets 1712, 1714 are the source pockets in the epitaxial layer.
  • the ends of pockets 1711, 1713, 1715 are directly overlain by an insulating layer. Again, this insulating layer is, in one embodiment, the silicon dioxide layer overlying the epitaxial layer.
  • ions having a charge opposite to charge of the gate pockets are implanted in regions 1720, 1721, 1722, 1723 (Fig. 17D) , which are approximately square regions at each corner periphery of the gate region.
  • the size of the region is selected so that the region overlaps the gate regions ends by approximately 2 ⁇ m to 10 ⁇ m, and preferably about 5 ⁇ m.
  • the important aspect of the ion-implant is to place the ions so that the electric field between the source and drain is diminished by the increased depletion area created by the implanted charge. More specifically,
  • Figure 17E is a cross sectional view of the gate implant region of the JFET of this invention.
  • the conventional depletion region near the silicon-silicon dioxide interface i.e., the region when the negative ions are not implanted in the insulating layer, is shown by the broken line 1730, 1740.
  • the horizontal extent of the depletion area is significantly enlarged by the implanted negative ions.
  • the implanted negative ions repel electrons from silicon-silicon dioxide interface 1720 so that there are fewer electrons in the vicinity of the interface to recombine with the minority charge carriers in the gate region. Therefore, electrons are removed from further into the epitaxial layer thereby increasing the size of the depletion region.
  • the larger depletion region reduces the electric field in the channel region which in turn increases the breakdown voltage.
  • the implanted negative ions for improved breakdown voltage are used in combination with the positive ions for greater overdrive capability.
  • the positive ions are implanted in the region bounded by the negative ion-implants at the ends of the gate regions, and the gate and source regions.
  • ion- implanted insulating layer regions 1707, 1708, (Fig. 17E) , 1720, 1721, 1722, 1723 (Fig. 17F) contain negatively charged ions, as indicated by the "-" symbol.
  • the ion- implanted insulating layer regions that contain the positively charged ions are indicated by the "+" symbol.
  • JFET 1800 is formed with improved on-resistance and breakdown voltage using a process similar to that described above for JFET 700. Specifically, the process is identical to that described above with respect to Figures 10A to 10D and that description is incorporated herein by reference.
  • positively charged ions are implanted in silicon dioxide layer 706A, 706B, 706C, 706D to form ion-implanted silicon dioxide layer 1806A, 1806B, 1806C, 1806D (Fig. 18) during the third mask step prior to the removal of photoresist 1015 over source opening 1011.
  • the implanted layer is annealed at a temperature in the range of 300 to 800 °C for 5 to 600 seconds. In one embodiment, the layer was annealed at a temperature of about 600 °C for about 5 minutes.
  • the positively charged ions are cesium ions.
  • the positively charged ions preferably may be any ion selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals.
  • the cesium implantation uses a flux in the range of 10 10 cm “2 to 10 14 cm “2 , preferably 10 12 cm “2 , with an energy of 10 Kev to 100 Kev, preferably 20 Kev. Notice that in this embodiment, the positively charged ion-implantation does not require a separate masking step and that the implant is self-aligned with source mask 1015.
  • JFET 1800 is formed using P type silicon, negatively charges ions are used to implant the silicon dioxide.
  • the negatively charged ions may be any ion from family VIIB of the periodic chart, commonly referred to as the halogens, as defined above.
  • One embodiment of this invention uses iodine ions.
  • JFET 1900 is formed using a process similar to that described above for JFET 700. Specifically, the process is identical to that described with respect to Figures 10A to 10D and the above description is incorporated herein by reference. However, for this embodiment, photoresist 1020, 1021 are not needed and the arsenic implantation forms source region 1905 and N+ regions 1915, 1917 in gate pockets 1903, 1905 of P+ type conductivity. The processing proceeds as described above for Figure 10F and that description is incorporated herein by reference. Of course, if diffused guard ring 1850, 1851 is not desired, the steps associated with Figure 10B are eliminated from the process and JFET 500 (Fig. 5A) is formed.
  • the oxide layer of Figure 10D is ion-implanted, as described above, during the process used to form JFET 1900 and consequently JFET 2000 (Fig. 20) is formed.
  • the feature sizes and doping concentrations are equivalent for equivalent features. Therefore, all of the processes may be intermixed and interchanged.
  • JFETs having any desired combination of the group of features including improved breakdown voltage, improved overdrive capability, and improved on-resistance.
  • various conductivity types may be used in the different regions of the JFET to achieve the same functions and results as described herein.

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Abstract

The junction field effect transistors (JFETs) of this invention have improved breakdown voltage capability, reduced on-resistance and improved overdrive capability. The on-resistance of JFET (2000) is decreased by ion-implanting an insulating layer (2006A, 2006B, 2006C, 2016D) covering a layer (2002) that contains source (2005) and gate (2003, 2004) regions of the unipolar transistor. To improve the overdrive capability of a JFET (2000) a region of conductivity (2015) opposite to the conductivity of gate region (2003) is formed in the gate region of the transistor. The second junction in gate region (2003) of this invention prevents the gate-to-source junction from becoming forward biaised until higher gate voltages are applied and thereby provides increased overdrive capability. A new method is used to form a guard ring (2050, 2051) surrounding the active area of a JFET (2000). JFET (2000) formed using this method has a guard ring (2050, 2051) of a second conductivity type extending a first distance D1 into a layer (2002) having a first conductivity type and a gate region of the second conductivity type extending a second distance D2 into layer (2002).

Description

HIGH FREQUENCY JFET AND METHOD FOR FABRICATING THE SAME
BACKGROUND OF THE INVENTION Field of the Invention
This invention relates generally to junction field effect transistors (JFETs) and in particular to a new process for forming a high power high frequency JFET that has an improved breakdown voltage control, reduced on- resistance, and overdrive capability. Prior Art
One goal common to most microwave semiconductor manufacturers is to continually increase the maximum continuous wave (CW) power available from singularly packaged transistors. Recently, as a response to this demand for high performance power transistors, device designers and application engineers have directed their attention away from bipolar power transistors to field effect transistors (FETs) . As a consequence, while bipolar transistors have experienced incremental performance gains, FETs, both in MOS and junction gate configurations, have made large steps forward in electrical performance, reliability levels, and cost competitiveness.
For very high radio frequency (RF)/microwave power generation and amplification, the use of a high power supply voltage is highly desirable. As higher power supply voltages are used, the current decreases and the transistor's specific impedance level increases, which in turn reduces the matching, combining, and power splitting circuitry loss and complexity. The higher impedance level makes wide operating frequency bandwidth achievable without significant trade offs in gain. The power supply voltage for CW power transistors is limited by the transistor breakdown voltage. One technique used to permit higher power supply voltages to use a short channel JFET. One embodiment of a prior art short channel JFET 100 is illustrated in Figure 1.
The drain of short channel junction field effect transistor (JFET) 100 is a heavily doped region 101 of conductivity type N++. Drain 101 is overlain by a lightly doped epitaxial layer 102 of conductivity type N-. As is known to those skilled in the art, a portion of region 102 functions as the channel of JFET 100. Two pockets 103, 104 of conductivity type P+, with their centers separated by a distance "a" (the device pitch) , extend into epitaxial region 102. Approximately centered between pockets 103, 104 in epitaxial region 102 is a doped source region 105 of conductivity type N+ or N++. An insulating layer 106 (in Fig. 1, a letter is used after reference numeral 106 to identify the different regions of the insulating layer that are visible in the cross-sectional view) overlies surface 102A and has contact openings over pockets 103, 104 and a contact opening over source 105.
Metal gate electrodes 110, 112 electrically contact pockets 103 and 104 respectively and overlie insulating layer 106 so that portions of electrodes 110 and 112 which are not in electrical contact with pockets 103 and 104 are electrically insulated from region 102. Source electrode 111 electrically contacts source 105 and also overlies insulating layer 106 so that portions of electrodes 111 which are not in electrical contact with source 105 are electrically insulated from region 102. A passivation layer 113 overlies electrodes 110, 111, 112 and insulating layer 106.
Short channel JFET 100 has non-saturated current voltage (I-V) characteristics which are similar to those of a vacuum tube triode. Figure 2 is a graph of the I-V characteristics for short channel JFET 100. The ordinate of the graph is the drain-to-source current in amps (IDS[A]) the abscissa is the drain-to-source voltage in volts (VDS[V]). Curves 201, 202, 203, 204, and 205 are for gate-to-source voltages (VGS[V]) of 0, -2, -4, -6, and -8 volts respectively.
The drain current of JFET 100 (Fig. 1) is controlled by the (negative) gate potential, as well as the
(positive) drain potential. The drain current decreases as the magnitude of the (negative) gate voltage increases. Moreover, the drain current increases with a rise in the drain voltage, a "short channel"-like behavior. Conditions under which semiconductor devices exhibit triode-like I-V characteristics are well-known to those skilied-in-the-art. For example see, G.F. Neumark, E.S. Rittner, "Transition from pentode- to triode-like characteristics in FETs", SSE, V10, pp. 299-304, 1967. Other references that define the prior art include: W. Shockley, "Transistorelectronics: imperfections, unipolar and analog transistors", PIRE, V40, pp. 1289-1313, Nov. 1952; R. Zuleeg, "Multi-channel FET theory and experiment", SSE, V10, pp. 559-576, 1967; J.R. Houser, "Characteristics of JFET devices with small channel-to- width ratios", SSE. V10, pp. 577-587, 1967; C. Kim, E. Yang, "Carrier accumulation and space-charge-limited current flow in FETs", SE, V13, pp. 1577-1589, 1970; J. Nishizawa, T. Terasaki, J. Shibata, "FET versus Analog Transistor (Static Induction Transistor)"; A. S. Wang, C.J. Dell'Oca, "A compatible bipolar and JFET Process" IEDM Proc.. pp. 45-47, Dec. 1976; J. Nishizawa, "Semiconductor technology in Japan", North Holland. Publisher, NY, 1982; M.G. Kane, R. Frey, "The PSIFET emerges as a new contender", MSN, pp. 46-58, Sept. 1984; A. Cogan, R. Blanchard, "Progress toward the ultimate semiconductor switch", Powertechniques Magazine, pp. 35- 39, Sept. 1986; J. Browne, "Solid State Triodes boost high voltages at broad bandwidths". Microwaves & RRF. pp. 211- 224, May, 1989; B.J. Baliga, "Bipolar operation of power JFETs.", El.Letters. V10, No. 2, Feb. 1980.
Short channel JFET 100 is a majority carrier device with high internal electric fields that exhibits a large number of favorable electrical and radio frequency characteristics (TABLE I) . Only majority carriers (electrons) flow in the short channel of JFET 100 (Fig. 1) . Hence, JFET 100 operates at high frequencies because no minority carrier effects are present to slow its operation.
Table I
Characteristics of Prior Art Short Channel JFET 100. Blocking voltage ) 120 V.
Voltage Gain > 25 §VDS = 40 V, IDS = l A.
Transconductance > 400 mS at VDS = 50 V, IDS = 1 A.
CGD < 0.3 pF/W § VGD = 50 volts.
CQS < 0.4 pF/W § VDS = 15 volts. Cus < 0.1 pF/W 8 VDS = 50 volts.
Saturated CW power > 150 W § 250 MHz.
F^ > 4GHz.
Power gain > lOdb @ 250 MHz.
Power (drain) Efficiency > 65% § 500 MHz
While prior art short channel JFET 100 provides enhanced performance over equivalent bipolar and MOS transistors, short channel JFET 100 is limited by the on- resistance, power overdrive capability, and process limitations that affect breakdown voltage. Techniques for enhancing each of these characteristics are known, but the techniques are generally not applicable to high frequency high power short channel JFET 100. Specifically, the techniques degrade either or both of the power and frequency capability of JFET 100. Therefore, applications of JFET 100 are limited to those applications were the on- resistance, power overdrive and breakdown voltage limitations are not of concern. Unfortunately, in most high power high frequency applications, all of these factors are of concern. SUMMARY OF THE INVENTION
According to the principles of this invention, the overdrive capability, the breakdown voltage capability and the on-resistance of a unipolar transistor, e.g., a junction field effect transistor, are improved over the prior art unipolar transistors. In one embodiment the on- resistance is decreased by ion-implanting an insulating layer covering a layer that contains the source and gate regions of the unipolar transistor. The ions used are selected so that after implantation the ions maintain their charge both during and after all the subsequent processing steps. This is an important aspect of the invention because if the implanted ions undergo recombination either during or after the subsequent processing, the improvement in on-resistance is lost.
The charge of the implanted ions is the same as the charge polarity of the gate regions. Thus, if the gate region is of conductivity type N, the ions are selected from the group of negatively charged ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) . Preferably, the iodine ion is used. Alternatively, if the gate region is of conductivity type P, the ions are selected from the group of positively charged ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals. These ions are in family IA of the periodic chart. Preferably, the cesium ion is used.
A novel unipolar transistor with the lowered on- resistance includes a support of a first conductivity type. A layer of the first conductivity is disposed on the support. The layer includes a first pocket having a second conductivity type, i.e, a gate region, separated from a second pocket having said first conductivity type, i.e., a source region. Both the first and second pockets extend into said layer from a surface of the layer. An ion-implanted insulating layer is disposed on the surface of the layer in the region separating the first pocket from the second pocket. Preferably, the transistor is a vertical transistor.
The ions in the insulating layer attract charge carriers of the opposite polarity to the interface between the layer and the insulating layer. The charge carriers of the opposite polarity decrease the size of the depletion zone near the interface and create a higher density of charge carriers in the channel region of the unipolar transistor. Both of these effects reduce the on- resistance of the transistor.
To improve the overdrive capability of a unipolar transistor, a region of conductivity opposite to the conductivity of the gate region is formed in the gate region of the transistor. This region of opposite conductivity creates another junction within the gate region. Thus, the gate region has two junctions, i.e, the junction between the region of opposite conductivity and the gate region, and the junction between the gate region and the layer containing the gate region.
The second junction within the gate region of this invention prevents the gate-to-source junction from becoming forward biased until higher gate voltages are applied and thereby provides increased overdrive capability in comparison to prior art JFETs. Specifically, the gate of the JFET of this invention has two back-to-back diodes such that one of the diodes is always reverse biased. Consequently, the gate of the JFET has a significantly greater power handling capability.
A transistor with improved overdrive capability includes a support of a first conductivity type. A layer of the first conductivity type is disposed on the support so that the layer has a surface opposite to the support. The layer contains a first pocket having a second conductivity type with (i) an upper surface that is a first predetermined distance from the surface of the layer and (ii) a lower surface that is a second predetermined distance from said surface of the layer. The lower surface forms a first junction between the first pocket and the layer.
The layer also contains a second pocket having the first conductivity type where the second pocket extends from the surface of the layer into the layer the first predetermined distance and contacts the first pocket so that a second junction is formed between the first and second pocket. The two pockets within the layer are the gate region with the two junctions, i.e., the two back-to- back diodes, described above.
A new method is used to form a guard ring surrounding the active area of a JFET, according to the principles of this invention. The JFET formed using this method has a guard ring of a second conductivity type, i.e., a pocket, extending a first distance Dl into a layer having (i) a first conductivity type and (ii) a gate region of the second conductivity type extending a second distance D2 into the layer. The method of this invention allows selection of the first and second distances Dl, D2 to optimize the breakdown voltage and performance of the JFET of this invention. To obtain first and second distances that are different, the guard ring and the gate regions are formed in different processing steps. Thus, the method for improving the breakdown voltage of a vertical transistor having a drain region and an active area that includes a source region includes the steps of (i) implanting a guard ring region that surrounds an active area of the transistor with ions of a first conductivity type in a first processing step; and (ii) implanting a gate region within the active area of the transistor with ions of the first conductivity type in a processing step different from the first implanting step so that the characteristics of the gate region and the characteristics of the guard ring region are determined different processing steps.
Specifically, a preferred embodiment of the method includes: depositing a masking material over a layer of a first conductivity type; forming openings in the masking material so that the openings surround an area in which the source and gate regions of the transistor are formed in subsequent processing steps; implanting ions of a second conductivity type in the layer through the openings to form a guard ring implant region; forming an insulating layer over the layer; creating openings in the insulating layer to expose surface areas of the layer that will become said gate regions of the transistor; and implanting ions of a second conductivity type in the layer through the openings whereby the gate region is formed with characteristics different from the characteristics of the guard ring region.
In another method to improve the breakdown voltage of the JFET, ions are implanted in the insulating layer so that the implanted ions surround the ends of the gates regions. The ions have a charge polarity opposite to the charge polarity of the gate region. Thus, if the gate region is of conductivity type P, the ions are selected from the group of negatively charged ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) . Preferably, the iodine ion is used. Alternatively, if the gate region is of conductivity type N, the ions are selected from the group of positively charged ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals. These ions are in family IA of the periodic chart. Preferably, the cesium ion is used.
The implanted ions repeal charge carriers having the same charge polarity as the ions from the layer-insulating layer interface at the ends of the gate regions. Therefore, the depletion zone is increased in this region and the number of charge carriers in the source-drain channel is decreased. Both of these effects reduce the source-to-drain current for a given voltage which increases the break down voltage. Thus, according to the principles of this invention a transistor having an improved breakdown voltage has a sup¬ port of a first conductivity type, e.g., a drain region. A layer of the first conductivity type is disposed on the support so that the layer has a surface opposite to the support. A first pocket having a second conductivity type is included within the layer. The pocket has (i) a lower surface a first predetermined distance from the surface of the and (ii) a first end and a second end, e.g., the pocket is the gate region of the transistor. A second pocket having the first conductivity type is also included in the layer. The second pocket extends from the surface a second predetermined distance into the layer. The second pocket is the source region. An ion-implanted insulating region surrounds the first and second ends of the first pocket and the ions have a charge polarity opposite to the charge polarity of the first pocket thereby improving the breakdown voltage of the transistor, as described above.
Each of the transistors of this invention have the same basic features sizes. Thus, the different embodiments may be intermixed to obtain a unipolar transistor having specific characteristics. For example, a JFET having a gate region and a guard ring with different depths and an ion-implanted layer where the ions have the same charge polarity as the charge polarity of the gate region may be formed. This JFET has an improved breakdown voltage and a reduced on-resistance in comparison to prior art JFETs.
Alternatively, the different depth guard ring and gate region may be combined with the dual junction gate region to obtain a JFET with improved breakdown voltage and improved overdrive capability. If the insulating layer of this JFET is implanted with ions having the same charge polarity as the charge polarity of the gate region, the JFET also has a reduced on-resistance.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross sectional view of a prior art short channel JFET.
Figure 2 is a graph of the current-voltage characteristics of the short channel JFET of Figure 1. Figures 3A and 3B are a cross sectional view of a short channel JFET with a ion-implanted insulating layer that reduces the on-resistance in comparison to the JFET of Figure 1.
Figure 4 includes a cross sectional view of a prior art short channel JFET and the short channel JFET of this invention with the improved on-resistance and a comparison of the channel widths of the two JFETs.
Figure 5A is a cross sectional view of a short channel JFET with an additional junction in the gate region that provides enhanced overdrive capability in comparison to the JFET of Figure 1.
Figure 5B is an equivalent circuit for the JFET of Figure 5A.
Figure 5C is a graph of drain-to-gate current vs. drain-to-gate voltage for JFET 100 of Figure 1 and JFET 500 of this invention.
Figure 5D is a graph of capacitance vs. gate voltage for JFET 100 of Figure 1 and JFET 500 of this invention.
Figure 6 is a short channel JFET according to the principles of this invention that has improved overdrive capability and a reduced on-resistance in comparison to the JFET of Figure 1. Figure 7 is a cross sectional view of a short channel JFET according to the principles of this invention that has a guard ring and gate regions that are formed in different processing steps so that the characteristics of the guard ring and the gate regions may be tailored for optimum performance.
Figures 8A and 8B are a top view and a cross- sectional view respectively of a prior art short channel JFET. Figures 8C and 8D are a top view and a cross sectional view respectively of the prior art JFET of Figures 8A and 8B with a guard ring that is used to increase the breakdown voltage overdrive capability.
Figure 9 is a top view of another prior art short channel JFET that illustrates the guard ring source metalization and gate metalization along with the oxide layers that are required to prevent shorting of the metal layers.
Figures 10A-10F illustrate the major processing steps according to the principles of this invention that are used to form the JFET of Figure 7.
Figure 11 is a graph of the current-voltage characteristics of the JFET of this invention.
Figure 12A is a graph of the input power in watts to the output power in watts at 800 MHZ and case temperature of 25° C for drain-to-source voltages of 40, 50, 60, and 70 volts for the JFET of this invention.
Figure 12B is a graph of the output power and power efficiency of the JFET of this invention as a functioning of positive drain supply voltage.
Figures 13, 14 and 15 are illustrative examples of bias circuits that may be used with the JFET of this invention in a common gate configuration.
Figure 16 is a push-pull bias circuit that may be used with another embodiment of the JFET of this invention.
Figures 17A-17G illustrate a method for improving the breakdown voltage of prior art JFETs using a ion-implanted insulating layer at the periphery of the gate regions.
Figure 18 is a cross sectional view of one embodiment of a JFET of this invention having a reduced on-resistance and an improved breakdown voltage in comparison to the JFET of Figure 1.
Figure 19 is a cross sectional view of another embodiment of the JFET of this invention that has enhanced overdrive capability and breakdown voltage performance in comparison with the JFET of Figure 1.
Figure 20 is yet another cross sectional view of a JFET according to the principles of this invention having an improved breakdown voltage, a reduced on-resistance, and an improved overdrive capability in comparison to the JFET of Figure 1.
DETAILED DESCRIPTION
A first embodiment of a novel short channel junction field effect transistor (JFET) 300 with a reduced on- resistance in comparison to JFET 100 is illustrated in Figure 3A. The drain of JFET 300 is a heavily doped region 301 of a first conductivity type, preferably a silicon substrate of conductivity type N++. Drain 301 is overlain by a lightly doped layer 302 of the first conductivity type, preferably an epitaxial layer of conductivity type N-. A portion of region 302 functions as the channel of JFET 300. In one embodiment, epitaxial layer 302 has a thickness in the range of about 2 micrometers (μm) to about 20 μm and is preferably about 10 μm thick. Herein, "thickness" refers to the distance in a direction perpendicular to the support, e.g., substrate 301, of the JFET.
Two pockets 303, 304 of a second conductivity type, with their centers separated by a distance x (the device pitch) , extend from the surface 302A of region 302 into epitaxial region 302A a first predetermined distance. In this embodiment, pockets 303, 304 are conductivity type P+. Surface 302A is the surface opposite surface 302B of epitaxial region 302 that contacts drain 301. As is well known to those skilled in the art, the JFET pitch defines a unit cell that may be replicated to obtain JFETs with 5 varying power handling capability.
Centered between pockets 303, 304 is a pocket 305 of the first conductivity type, e.g., a doped source region, which in this embodiment is conductivity type N+. Source region 305 extends from surface 302A a second
10 predetermined distance into region 302. Preferably, the second predetermined distance is less than the first predetermined distance.
In one embodiment, the first predetermined depth, i.e., the depth of regions 303, 304 in layer 302 is in the
15 range of 0.5 μm to 10 μm and preferably about 2.5 μm. The concentration of dopant atoms in pockets 303 and 304 is about 1015 to 1020 atoms/cm3 and preferably about 1019 atoms/cm3.
The second predetermined depth, i.e., the depth of
20 region 305 in layer 302, is about 0.1 μm to 1 μm and preferably about .25 μm. The concentration of dopant atoms in pocket 305 is in the range of about 1018 to 1021 atom/cm3 and preferably about 1021 atoms/cm3. Layer 302 is the range of 4 μm to 40 μm thick, preferably about 8 μm,
25 and has a resistivity in the range of 0.5 Ω-cm to 40 Ω-cm and preferably about 4 Ω-cm.
An ion-implanted insulating layer 306, preferably silicon dioxide implanted with cesium ions, overlies surface 302A and has contact openings over gate pockets
30 303, 304 and another contact opening over source pocket 305. Ion-implanted insulating layer 306 is implanted with an ion having the same charge polarity as pockets 303, 304, i.e., the same charge polarity as the charge polarity of the conductivity type of the gate regions. Insulating
35 layer 306 has a thickness in the range of 0.1 μm to 2 μm, preferably about 0.7 μm, and has an ion-implant charge dose of 1011 cm"2 to 1014 cm"2 and preferably about 1012 cm"2. In this embodiment, the positively charged ions are cesium ions. However, the positively charged ions preferably may be any ion selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals.
Alternatively, if the gate regions are of conductivity type P, the insulating layer is implanted with negatively charged ions. The negatively charged ions preferably may be any ion selected from the group of ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) . Preferably, the iodine ion is used.
The ions used are selected so that after implantation the ions maintain their charge both during and after all the subsequent processing steps. This is an important aspect of the invention because if the implanted ions undergo recombination either during or after the subsequent processing, the improvement in on-resistance is lost.
Gate electrodes 310, 312 electrically contact pockets 303 and 304 respectively and overlie ion-implanted insulating layer 306 so that portions of electrodes 310 and 312 which are not in electrical contact with pockets 303 and 304 are electrically insulated from region 302. Preferably, gate electrodes 310, 311 are one metal selected from the group of metals consisting of aluminum and PtSi/TiW/Al.
Source electrode 311 electrically contacts source region 305 and also overlies ion-implanted insulating layer 306 so that portions of electrodes 311 which are not in electrical contact with source 305 are electrically insulated from region 302. Source electrode 311 is also preferably selected from the group of metals described above. Of course, electrodes 310, 311, 312 may be formed from any conductive material and the source and gate electrodes may be formed of different materials. A passivation layer 313 overlies electrodes 310, 311, 312 and ion-implanted insulating layer 306. In one embodiment, the width of the opening in layer 306 for the source and drain contacts, i.e., distance "a", (Fig. 3B) is in the range of 0.5 μm to 5 μm and preferably about 0.8 μm. The width of layer 306 between pocket 305 and pockets 303, i.e., distance "b", is about 0.8 μm to 6 μm and preferably about 1 μm. Cell 300 is symmetrie about center line 350 of the cell as illustrated in Figure 3A. Therefore, in this embodiment device pitch x is in the range of 2.6 μm to 22 μm and preferably about 3.6 μm. The on-resistance of JFET 300 is reduced in comparison to a similar JFET which does not have the ion- implanted insulating layer. Consider prior art transistor 100 (Fig. 1) which has the smallest on-resistance with a gate-to-source bias voltage of 0 volts. With this bias voltage, JFET 100 has depletion regions 121, 122 (See Figure 4. Figure 4 is an enlarged view of JFET 300 with the depletion region of JFET 100 shown for comparison) . The boundaries of depletion regions 121, 122 for JFET 100 in epitaxial layer 302 are shown by the broken line in Figure 4. The channel of JFET 100 is the region extending from drain 101 to source 105 between depletion regions 121, 122. As is well-known to those skilled in the art, channel width w of transistor 100 determines the on- resistance of JFET 100.
Prior art techniques to modify channel width w and thereby reduce the on-resistance of JFET 100 included field plates and biasing methods. For example, the on- resistance is reduced by forward biasing the gate-source junction below its turn-on point. However, this requires an additional gate voltage and may accidentally turn-on the junction thereby destroying JFET 100 through excess current.
Field plates may be used to produce an electric field that attracts charge carriers, i.e., electrons, into the depletion region thereby increasing the channel width which in turn reduces the on-resistance. However, such field plates require additional space which in turn increases the JFET gate-to-source distance. As is known to those skilled-in-the-art, as the gate-to-source distance increases, the JFET performance decreases. In particular, the frequency response of the JFET is directly related to the size of the JFET. The ion-implanted insulating layer of this invention overcomes the shortcomings of the prior art techniques for reducing the on-resistance of JFET 300. Further, the ion- implanted insulating layer, as described more completely below, permits construction of smaller feature, high density devices. With smaller features, the frequency response of JFET 300 improves. Thus, ion-implanting the insulating layer improves both the on-resistance and the frequency response of prior art JFET 100.
Ion-implanted insulating layer 306 (Fig. 4) creates an electric field between source region 305 and layer 306. The electric field causes electrons to be transported from source 305 and to accumulate at silicon dioxide-silicon interface 302A. These excess electrons repopulate the edge of the depletion region thereby effectively reducing the size of depletion regions 320, 321 near interface 302A for a given gate-to-source voltage, i.e, the depletion region is reduced by the permanent positive electrical charge at the silicon dioxide-silicon interface. The decrease in the size of the depletion region results in an increase in width "w*" of the channel region which in turn results in an increase in the current path between source 305 and drain 301. Moreover, the increase in the number of electrons near the channel surface further increases the conductivity of the source-to-drain channel. As illustrated in Figure 4, channel width w* of JFET 300 is greater than channel width w of JFET 100. The increased current path improves, i.e., lowers, the on- resistance of JFET 300 over JFET 100. This means that for a given acceptable on-resistance, JFET 300 of this invention requires a smaller channel width than prior art JFET 100. Thus, JFET 300 may be constructed with smaller 5 features which results in the improved density and frequency performance. Further, the lower specific on- resistance (per area) enables better use of the silicon "real estate."
A second embodiment of a novel short channel junction
10 field effect transistor 500 with an increased overdrive capability relative to prior art JFET 100 (Fig. 1) is illustrated in Figure 5A. A heavily doped region 501, preferably a silicon substrate of a first conductivity, e.g., conductivity type N++, functions as the drain of
15 JFET 500. Drain 501 is overlain by a lightly doped layer 502 of the first conductivity type and is preferably an epitaxial layer of conductivity type N-. A portion of region 502 functions as the channel of JFET 500.
Two pockets 503, 504 of a second conductivity type,
20 with their centers separated by a distance xx (the device pitch) , extend into epitaxial region 502A a first predetermined distance from the surface 502A of region 502. Surfaces 503A, 504A of pockets 503, 504 at the first predetermined distance form a diode junction with
25 epitaxial region 502. In this embodiment, pockets 503, 504 are conductivity type P+. Surface 502A is the surface opposite surface 502B of epitaxial region 502 that contacts drain 501.
Herein, device pitch xx is the same as device pitch x
30 of JFET 300. Similarly, the feature sizes and other characteristics of JFET 300 are the same as those of JFET 500.
Within each pocket 503, 504 is a region 515, 517 of the first conductivity type N+ that extends into pocket
35 503, 504 a second predetermined distance from the surface 502A of region 502. Surfaces 515A, 517A of pockets 515, 517 at the second predetermined distance form a diode junction with pockets 503, 504 respectively. Thus, the gate regions of JFET 500 contain back-to-back diodes.
Centered between pockets 503, 504 is a doped source region 505 of the first conductivity type, which in this embodiment is conductivity type N+. In this embodiment, source region 505 extends from surface 502A the second predetermined distance into region 502. Preferably, the second predetermined distance is less than the first predetermined distance. An insulating layer 506, preferably silicon dioxide, overlies surface 502A and has contact openings over pockets 503, 504 and a contact opening over source 505.
Gate electrodes 510, 512 electrically contact pockets 516 and 517 respectively and overlie insulating layer 506 so that portions of electrodes 510 and 512 which are not in electrical contact with pockets 516 and 517 are electrically insulated from region 502. Preferably, gate electrodes 510, 511 are one metal selected from the group of metals described above for transistor 300. Source electrode 511 electrically contacts source 505 and also overlies insulating layer 506 so that portions of electrodes 511 which are not in electrical contact with source 505 are electrically insulated from region 502. Source electrode 511 is also preferably selected from the group of metals described above. Of course, electrodes 510, 511, 512 may be formed from any conductive material and the source and gate electrodes may be formed of different materials. A passivation layer 513 overlies electrodes 510, 511, 512 and insulating layer 506. The dimensions and doping concentrations of JFET 500 are the same as those of JFET 300 which are incorporated herein by referenc .
When prior art JFET 100 (Fig. 1) , described above, is used in a high frequency amplifier circuit, the gate-to- source junction may become forward biased when the source input signal increases above a certain threshold or power level, i.e, JFET 100 is overdriven. When the gate-to- source junction becomes forward biased, the junction injects minority carriers into the drain-to-source channel. Consequently, unipolar JFET 100 becomes a bipolar transistor, i.e, the input signal has exceeded the bipolar turn-on threshold and JFET 100 may be destroyed by excess current. Also, a bipolar transistor has a slower response than a unipolar transistor such as JFET 100. To prevent the bipolar mode, the power level of JFET 100 must be maintained, i.e., limited, so that JFET 100 in not driven over the bipolar turn-on threshold.
The second n-p junction 515A, 517A in gate regions 503, 504 of JFET 500 (Fig. 5A) of this invention prevents the gate-to-source junction from becoming forward biased until higher gate voltages are applied and thereby provides increased overdrive capability in comparison to JFET 100. Specifically, an equivalent circuit for unipolar transistor 500 (Fig. 5A) is illustrated in Fig. 5B. The gate of JFET 500 has two back-to-back diodes 524, 525 such that one of the diodes is always reverse biased. Consequently, the gate of JFET 500 has a significantly greater power handling capability.
The bipolar turn-on threshold is increased from about the 0.6 volts of JFET 100 to several volts, typically about 2 to 3 volts, i.e., the breakdown-voltage of diode 524, or even higher as illustrated in Figure 5C. The increase in the bipolar turn-on voltage also results in an increase of the capacitance "turn-on" voltage as shown in Figure 5D.
Since the bipolar turn-on voltage of JFET 500 is increased, the maximum acceptable high frequency input power level is also increased. Moreover, the second diode does not affect normal operation of JFET 500 because a JFET has a very high input impedance, typically several megohms. The impedance of the second diode only changes the JFET input impedance by a small amount, e.g., about 10 percent.
In another embodiment, ion-implanted insulating layer 306 of JFET 300 and the additional n-p junctions of JFET 500 are included in a single JFET 600 (Figure 6) . The other features of JFET 600 are similar to those described above for JFETs 300 and 500 and that description is incorporated herein by reference. Thus, JFET 600 has both a reduced on-resistance and an enhanced power overdrive capability in comparison to prior art JFET 100.
In yet a third embodiment of this invention, the breakdown voltage of JFET 100 (Fig. 1) is increased using a novel processing method to form a JFET 700 (Fig. 7) with a guard ring 750, 751 of P conductivity type extending a first distance Dl into epitaxial layer 702 and gate regions 703, 704 of P conductivity type extending a second distance D2 into epitaxial layer 702. First and second distances Dl, D2 are selected to optimize the breakdown voltage and performance of JFET 700. As described above, distance D2 is in the range of 0.5 μm to 10 μm, and preferably about 2.5 μm. The distance Dl is in the range of 0.5 μm to 10 μm, and preferably about 3 μm. To understand the advantages of this new processing method and resulting JFET 700, it is informative to first consider the prior art methods for forming a diffused guard ring around the active area of JFET 100 (Fig. 1) . A top view and a cross-sectional view of a prior art JFET 800 without a guard ring are presented in Figs. 8A and 8B respectively. Gate regions 803, 804 and source region 805 of JFET 800 are substantially similar to the equivalent regions of JFET 100. JFET 800 is constructed using the basic cell structure of JFET 100. Specifically, JFET 800 has two gate regions 803, 804 of P+ conductivity type and a source region 805 of N+ conductivity type formed in an epitaxial layer 802 of conductivity type N-.
A top view and a cross-sectional view of prior art
JFET 800A with a guard ring 850 are illustrated in Figs. 8C and 8D respectively. Specifically, JFET 800A still has two gate regions 803, 804 of P+ conductivity type and a source regions 805 of N+ conductivity type formed in an epitaxial layer 802 of conductivity type N-. However, gate regions 803, 804 are now directly connected by regions 810, 811 of P+ conductivity type. Guard ring 850 is a diffused region of P+ conductivity type that 5 surrounds source regions 805 and gate regions 803, 804, 810, 811.
Typically, guard ring 850 (Fig. 8C) is formed in the same process step as gate regions 803, 804 (Figs. 8C and 8D) so that guard ring 850 and gate regions 803, 804
10 extend the same distance into epitaxial region 802.
Consequently, separate adjustments to the depth of guard ring 850 and gate diffusion regions 803, 804 are not possible. The depth of the guard ring in region 802 and distance "d" determine the breakdown voltage
15 characteristics of the JFET so that the breakdown voltage is limited by the depth of the diffusion required for the gate regions.
Guard ring 850 introduces another problem. The metal contacts to the source regions 805 and gate regions 803,
20 804, 810, 811 of JFET 800A are separate gate and source metalization fingers. If both metal contacts electrically contact guard ring 850, the metal contacts will be shorted.
For example, JFET 900 (Fig. 9) has four source
25 regions 906, 907, 908, 909 and five gate regions 901, 902, 903, 904, 905 with interconnecting regions 910, 911. Again, JFET 900 is constructed using unit cell 100 (Fig. 1). Gate metalization fingers 941, 942, 943, 944, 945 of gate contact 940 electrically contact gate regions
30 901, 902, 903, 904, 905, respectively. Source metalization fingers 931, 932, 933, 934 of source contact 930 electrically contact source regions 906, 907, 908, 909, respectively.
To prevent electrical shorting of gate contact 940
35 and source contact 930 by guard ring 920, a separate masking step is required in the fabrication process to define insulating layers 950, 960 that insulate the overlying metal contact from the underlying guard ring 920. Typically, a second insulating layer, i.e., a low temperature oxide, is deposited on the structure and patterned prior to the first metalization process step. A masking step is required to pattern the low temperature oxide layer to form regions 950, 960. This masking step increases both production time and production costs of the JFET. Thus, the improvement in breakdown voltage comes at the expense of additional processing steps. According to the principles of this invention, the breakdown voltage of prior art JFET 100 is enhanced by using separate masking steps to form the guard ring and the gate regions thereby eliminating the separate mask step required in the prior art to form the insulating layer between the guard ring and the source and gate contacts. The elimination of that mask step reduces the production cost of the JFET and in addition, the novel process of this invention provides for adjusting the guard ring diffusion and the gate diffusions for optimum breakdown voltage and performance.
In one embodiment of this invention, the formation of the JFET starts with an N+ silicon substrate with a resistivity in the range of 0.001 to 0.01 ohm-cm. In another embodiment, the substrate is processed to form an N++ substrate using standard industry techniques.
After processing of the substrate to form the N++ conductivity region 701, an epitaxial layer 702 of conductivity type N- is grown on the substrate using a conventional chemical vapor deposition process. Epitaxial layer 702 has a thickness in the range of 4 μm to 40 μm preferably about 8 μm, and a resistivity in the range of 0.5 Ω-cm to 40 Ω-cm preferably about 4 Ω-cm.
Subsequent to growing epitaxial layer 702, a silicon dioxide layer 1001 with a thickness of about 0.01 μm to about 0.1 μm, preferably about 0.05 μm, is formed on epitaxial layer 702 using conventional processes known to those skilled in the art. A mask layer, preferably silicon nitride (Si3N4) , is deposited on silicon dioxide layer 1001 and a photoresist layer is then deposited on the mask layer. The photoresist layer is processed in a standard fashion so that only the portions of silicon nitride mask layer 1002, 1003, 1004 that cover the areas of epitaxial layer 702 that will become the source and gate regions are covered. A standard chemical wet etch is then used to remove the portion of the silicon nitride layer that is not protected by the photoresist. Alternatively, a plasma or RIE etch may also be used. After the etch, the photoresist is removed. Thus, the result of the first mask step is the structure illustrated in Figure 10A. The distance between the centers of silicon nitride portions 1002, 1004 defines the JFET pitch.
A second mask step is used for the guard ring implantation. A photoresist 1005 is deposited on the structure of Figure 10A and openings 1007, 1008 for the guard ring implant are formed in a conventional fashion. The width of the guard ring implant opening is the range of 0.5 μm to 5 μm preferably about 1 μm. Edge 1006A1 of masking opening from the guard ring implant is a distance nd u from edge 1002A of silicon nitride 1002 is in the range of 1 μm to 15 μm and preferably about 6 μm. In one embodiment, a boron implantation 1006A, 1006B is used in this embodiment to form P+ pockets that will become the guard ring after drive in. The boron implantation uses a flux in the range of 1012 cm"2 to 1015 cm"2 preferably 1013 cm"2 with an energy of 30 Kev to 150 Kev, preferably 60 Kev. After the implantation, photoresist 1005 is removed using standard processes. The implant is driven in using a temperature in the range of 950 °C to 1150 °C for about 0 hours to 3 hours. In one embodiment, a temperature of about 1100 °C for about one hour was used.
In this step, the process parameters affect only the guard ring implant. Recall that in the prior art device, the guard ring and gate implants were formed simultaneously so that the characteristics of the guard ring were primarily determined by the implant required to form the gate region. The gate junction depth affects the device gain, transconductance, and maximum frequency. The process of this invention decouples the gate and guard ring processing steps thereby allowing each step to be tailored for optimal performance.
In the next processing step, a thicker silicon dioxide layer 706 is grown and in the process, the guard ring implant is simultaneously further driven in. This step utilizes conventional processes such as "local oxidation" or "selective oxidation" using the silicon nitride as an oxidation mask. Subsequently, the silicon nitride is removed to form the structure of Fig. 10B.
Silicon dioxide layer 706 has a thickness in the range of 0.1 μm to 2 μm and preferably about 0.7 μm.
A third mask step is used for the gate implantation. A photoresist is deposited on the structure of Figure 10C and all of the photoresist except portion 1015 covering source opening 1011 is removed in a conventional fashion. In one embodiment, a boron implantation 1016A, 1016B is used to form P+ conductivity pockets that form the gate regions. The boron implantation uses a flux in the range of 1012 cm"2 to 1015 cm"2, preferably 2xl013 cm"2 with an energy of 30 Kev to 150 Kev, preferably 60 Kev. After the implantation, photoresist 1015 is removed using standard processes, and the implant is driven in at a temperature in the range of 950 °C to 1150 °C, preferably about 1100 °C, for a time in the range of 15 minutes to three hours, preferably about 45 minutes.
A fourth mask step is used for the source implantation. A photoresist is deposited on the structure of Figure 10D without layer 1015 and all of the photoresist except portions 1020, 1021 covering gate openings 1010, 1012, respectively, is removed in a conventional fashion. In one embodiment, an arsenic implantation 1021 is used to form the N+ conductivity pocket that becomes the source region. The arsenic implantation uses a flux in the range of 10w cm"2 to 1016 cm"2, preferably about 5xl015 cm2, with an energy of 15 Kev to 100 Kev preferably about 25 Kev. After the implantation, photoresist 1020, 1022 is removed using standard processes and the implant is annealed at a temperature in the range of 500 °C to 1000 °C for 30 seconds to 100 minutes and preferably about 950 °C for about 45 minutes.
In the fifth mask step, metal electrodes 710, 712 to gate region 703, 704 and a metal electrodes 711 to source region 705 are formed using conventional processes. After formation of metal electrodes 710, 711, 712, a silicon dioxide passivation layer is deposited over the structure to obtain JFET 700 using conventional techniques.
In this embodiment and each of the other embodiments of the JFETs of this invention, only a single source region and two gate regions, i.e., a unit cell are included. However, this description is only illustrative of the principles of the invention and is not intended to limit the invention to the particular embodiment described. In view of this disclosure, those skilled in the art can use the novel process to form a JFET with an improved breakdown voltage having multiple source regions and multiple gate regions. Similarly, JFETs with improved on-resistance and overdrive capability can be formed with multiple source regions and multiple gate regions.
Specifically, the JFET of this invention with a guard ring formed by the novel process described above has at 1 GHz approximately the following normalized characteristics per gate width (note that the JFET does not include any ion-implanted insulating regions) : Power " 10 watts/cm On-resistance R^ ~ 25 Ωcm
Power gain ~ 10 dB
Breakdown voltage VGD " 135 volts Transconductance (gm) " 75 mS/cm Breakdown voltage VGD " 90 volts without guard ring
These parameters can be used to define the size of a JFET with a specific power handling capability. Using the above process, where the diffused guard ring is formed in the second mask step and the gate is formed in the third mask step, a JFET 700 is obtained with a significantly enhanced breakdown voltage performance in comparison to JFET 100. JFET 700 operates as a depletion mode FET and requires biasing conditions similar to a
MESFET, e.g., negative voltage to the gate and positive voltage to the drain. When the source is DC grounded and the drain positively biased, a negative gate voltage is required to turn off JFET 700. JFETs 300, 500 and 600 also operate in this manner.
JFET 700 operates over a wide range of drain voltages, and can operate CW at drain supply voltages as high as 80 volts. As illustrated in the I-V curves of
Figure 11, higher gate-to-source voltage and a higher drain-to-source current are achieved with this process than for the I-V curves of Fig 2. In Figure 11, the ordinate of the graph is the drain-to-source current in amps (IDS[A]) and the abscissa is the drain-to-source voltage in volts (VDS[V]). Curves 1101, 1102, 1103, 1104, and 1105 are for gate-to-source voltages (VGS[V]) of 0, -3,
-6, -9, and -12 volts respectively.
Maximum CW power for single-ended JFETs of this invention is 120 watts(W) or higher at 1000 megahertz(MHz) with a single frequency power gain of 10 decibels(dB) or higher. (Herein, "single-ended" is used to distinguish from "push-pull" operation.) Figure 12A is a graph of input power in watts PI(W) to output power in watts
POUT(W) at 800 MHz and a case temperature of 25 °C for drain-to-source voltages of 40, 50, 60 and 70 volts, respectively of JFET 700.
The maximum available output power and the power gain of JFET 700 increase when the positive drain supply voltage VDD is increased. Output power and power efficiency as a function of change in positive drain supply voltage VDD are illustrated in Figure 12B.
In one embodiment, JFET 700 is operated in a common gate configuration to take advantage of the highest frequencies at which JFET 700 still has high power gain. When operated in a common gate configuration, JFET 700 exhibits a single frequency power gain of higher than 10 dB at frequencies as high as 1000 MHz, because JFET 700 has high transconductance of 1 to 2 S coupled with a low common gate feedback capacitance(< 0.1 pf/W) .
Three basic bias circuits for a DC biased common-gate JFET 700 which permit high RF gain operation are illustrated in Figures 13, 14, 15. Figure 13 has gate G of JFET 700 DC and RF grounded. The gate bias voltage develops across the PNP power bipolar transistor(BJT)/Zener diode (DZ) combination. Bias circuit 1300 (Fig. 13) requires only one power supply. The Zener diode DZ is selected to operate JFET 700 in one of Classes A, AB, B or C. Alternatively, Zener diode DZ may be replaced with a resistive voltage divider connected between positive drain power supply voltage VDD and ground. With the resistive voltage divider, the gate voltage may be continuously adjusted for optimal operation. For automatic gain control applications, a DC voltage component is applied between the base of PNP transistor BJT and ground. In such applications, the linear power gain of JFET 700 is adjustable over a range of about 18 dB.
The bias circuit shown in Figure 14 separates the DC ground from the RF ground by DC floating the drain power supply VDD. A second power supply VSG is required to provide the gate-to-source voltage. This bias circuit eliminates power dissipation in the gate biasing supply, but requires DC floating of the drain power supply.
One family of RF packages widely used in the industry has the input(source) and output(drain) leads positioned between four common leads(gate). The bias circuit shown in Figure 15 is used with JFET 700 in such a RF package. In this circuit, gate G is RF grounded while source S is DC grounded. The physical implementation of this circuit requires four low-profile planar capacitors to be mounted under the package common leads. Typical values of these capacitors range from 10 pF through 1000 pF.
In another family of RF packages widely used in the industry has a push-pull eight lead version of JFET 700. This package has two input (source) leads SI, S2, two output (drain) leads Dl, D2, and two pairs of common leads (gates) Gl, G2. A bias circuit for this embodiment of JFET 700 is illustrated in Figure 16. This bias circuit provides RF and DC ground separation.
In the previous embodiment, a new JFET 700 with a diffused guard ring was used to enhance the breakdown voltage. In another embodiment, the breakdown voltage is enhanced without use of a guard ring. Specifically, ions, having a charge opposite to the conductivity of the gate region, are implanted in the insulating layer, preferably silicon dioxide, at the periphery of the gate implant region. For example, in the structure of Figure 17A, P+ conductivity type pockets 1701, 1703, 1705 are the gate pockets in an epitaxial layer and N+ conductivity type pockets 1702, 1704 are the source pockets in the epitaxial layer. Ends 1701A, 1701B, 1703A, 1703B, 1705A, 1705B of pockets 1701, 1703, 1705 are directly overlain by an insulating layer. In one embodiment this is the insulating layer overlying the surface of the epitaxial layer which has contact openings for the gate and source electrodes.
According to the principles of this invention, ions having a charge opposite to charge of the gate pockets, are implanted in regions 1707, 1708 (Fig. 17B) . The implanted regions extend a predetermined distance nl beyond the ends of the gate pockets and a predetermined distance n2 along the gate pocket so that ion-implanted regions 1707 and 1708 surround the ends of the gate pockets.
Both distances nl and n2 are in the range of 2 μm to 10 μm and preferably about 5 μm. When the gate pocket is of a P+ conductivity type, negatively charged ion are implanted. In one embodiment, the ions are an iodine ion- implantation that uses a flux in the range of 1010 cm"2 to 1014 cm"2, preferably 1012 cm"2, with an energy of 10 Kev to 100 Kev, preferably 20 Kev. While iodine ions are used in this embodiment, the negatively charged ions preferably may be any ion selected from the group of ions consisting of fluorine, chlorine, bromine, iodine, and astatine, which are commonly referred to as the halogens, i.e, family VIIB of the periodic chart. (Herein, hydrogen is not considered a member of family VIIB) . If a N+ conductivity type is used for the gate pockets, the implanted ions are positively charged. The positively charged ions preferably may be any ion selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals. These ions are in family IA of the periodic chart.
In the structure of Figure 17C, P+ conductivity type pockets 1711, 1713, 1715 are the gate pockets in an epitaxial layer and are joined by P+ conductivity type pockets 1716, 1717. N+ conductivity type pockets 1712, 1714 are the source pockets in the epitaxial layer. The ends of pockets 1711, 1713, 1715 are directly overlain by an insulating layer. Again, this insulating layer is, in one embodiment, the silicon dioxide layer overlying the epitaxial layer.
According to the principles of this invention, ions having a charge opposite to charge of the gate pockets, are implanted in regions 1720, 1721, 1722, 1723 (Fig. 17D) , which are approximately square regions at each corner periphery of the gate region. The size of the region is selected so that the region overlaps the gate regions ends by approximately 2 μm to 10 μm, and preferably about 5 μm.
The important aspect of the ion-implant is to place the ions so that the electric field between the source and drain is diminished by the increased depletion area created by the implanted charge. More specifically,
Figure 17E is a cross sectional view of the gate implant region of the JFET of this invention. The conventional depletion region near the silicon-silicon dioxide interface, i.e., the region when the negative ions are not implanted in the insulating layer, is shown by the broken line 1730, 1740. The horizontal extent of the depletion area is significantly enlarged by the implanted negative ions.
The implanted negative ions repel electrons from silicon-silicon dioxide interface 1720 so that there are fewer electrons in the vicinity of the interface to recombine with the minority charge carriers in the gate region. Therefore, electrons are removed from further into the epitaxial layer thereby increasing the size of the depletion region. The larger depletion region reduces the electric field in the channel region which in turn increases the breakdown voltage.
In one embodiment, the implanted negative ions for improved breakdown voltage are used in combination with the positive ions for greater overdrive capability. As described above, the positive ions are implanted in the region bounded by the negative ion-implants at the ends of the gate regions, and the gate and source regions. Specifically, as illustrated in Figs. 17E and 17F, ion- implanted insulating layer regions 1707, 1708, (Fig. 17E) , 1720, 1721, 1722, 1723 (Fig. 17F) contain negatively charged ions, as indicated by the "-" symbol. The ion- implanted insulating layer regions that contain the positively charged ions are indicated by the "+" symbol.
In another embodiment, JFET 1800 is formed with improved on-resistance and breakdown voltage using a process similar to that described above for JFET 700. Specifically, the process is identical to that described above with respect to Figures 10A to 10D and that description is incorporated herein by reference. However, with the structure illustrated in Figure 10D, positively charged ions are implanted in silicon dioxide layer 706A, 706B, 706C, 706D to form ion-implanted silicon dioxide layer 1806A, 1806B, 1806C, 1806D (Fig. 18) during the third mask step prior to the removal of photoresist 1015 over source opening 1011. After the implant, the implanted layer is annealed at a temperature in the range of 300 to 800 °C for 5 to 600 seconds. In one embodiment, the layer was annealed at a temperature of about 600 °C for about 5 minutes.
In one embodiment, the positively charged ions are cesium ions. However, the positively charged ions preferably may be any ion selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium, which are commonly referred to as the alkali metals. The cesium implantation uses a flux in the range of 1010 cm"2 to 1014 cm"2, preferably 1012 cm"2, with an energy of 10 Kev to 100 Kev, preferably 20 Kev. Notice that in this embodiment, the positively charged ion-implantation does not require a separate masking step and that the implant is self-aligned with source mask 1015. After the cesium implantation, the processing proceeds as described above for Figures 10E and 10F and that description is incorporated herein by reference. Of course, if diffused guard ring 1850, 1851 is not desired, the steps associated with Figure 10B are eliminated from the process and JFET 300 (Fig. 3) is formed.
After implantation, the cesium ions maintain their charge both during and after all the subsequent processing steps. This is an important aspect of the invention because if the implanted ions undergo recombination either during or after the subsequent processing, the improvement in on-resistance provided by the ions will be lost. If JFET 1800 is formed using P type silicon, negatively charges ions are used to implant the silicon dioxide. The negatively charged ions may be any ion from family VIIB of the periodic chart, commonly referred to as the halogens, as defined above. One embodiment of this invention uses iodine ions.
In another embodiment, JFET 1900, with improved overdrive capability and breakdown voltage, is formed using a process similar to that described above for JFET 700. Specifically, the process is identical to that described with respect to Figures 10A to 10D and the above description is incorporated herein by reference. However, for this embodiment, photoresist 1020, 1021 are not needed and the arsenic implantation forms source region 1905 and N+ regions 1915, 1917 in gate pockets 1903, 1905 of P+ type conductivity. The processing proceeds as described above for Figure 10F and that description is incorporated herein by reference. Of course, if diffused guard ring 1850, 1851 is not desired, the steps associated with Figure 10B are eliminated from the process and JFET 500 (Fig. 5A) is formed. Similarly, if the improved on- resistance is desired in addition to the improved breakdown voltage and overdrive capability, the oxide layer of Figure 10D is ion-implanted, as described above, during the process used to form JFET 1900 and consequently JFET 2000 (Fig. 20) is formed. In each of the JFETs of this invention the feature sizes and doping concentrations are equivalent for equivalent features. Therefore, all of the processes may be intermixed and interchanged. Several embodiments of JFETs formed using the principles of this invention have been described above. These embodiments are illustrative only of the principles of the invention and are not intended to limit the invention to the particular embodiments described. In view of this disclosure, those skilled in the art can form a variety of JFETs having any desired combination of the group of features including improved breakdown voltage, improved overdrive capability, and improved on-resistance. In addition, as is well known to those skilled in the art, various conductivity types may be used in the different regions of the JFET to achieve the same functions and results as described herein.

Claims

CLAIMS :
We claim: 1. A vertical transistor comprising: a support of a first conductivity type; a layer of said first conductivity disposed on said support wherein said layer includes a first pocket having a second conductivity type separated from a second pocket having said first conductivity type and further wherein said first and second pockets extend into said layer from a surface of said layer; and an ion-implanted insulating layer disposed on the surface of said layer in the region separating said first pocket from said second pocket wherein said ions have the same charge polarity as the charge polarity of said second conductivity type.
2. The vertical transistor of Claim 1 wherein said ion-implanted insulating layer comprises a silicon dioxide layer.
3. The vertical transistor of Claim 1 wherein said layer further includes a third pocket having said second conductivity type and extending from said surface into said layer wherein said second pocket is centered between said first and third pockets.
4. The vertical transistor of Claim 3 wherein said ion-implanted insulating layer is disposed on the surface of said layer in the region separating said second pocket from said third pocket.
5. The vertical transistor of Claim 1 further comprising a first electrode wherein said first electrode electrically contacts said second pocket and is electrically insulated from said layer by said ion- implanted insulating layer. 6. The vertical transistor of Claim 5 further comprising a second electrode wherein said second electrode electrically contacts said first pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
7. A vertical transistor comprising: a highly doped semiconductor layer of a first conductivity type; an epitaxial layer of said first conductivity type overlying said highly doped semiconductor layer and having a surface opposite said highly doped semiconductor layer; a first pocket having a second conductivity type within said epitaxial layer wherein said first pocket extends from said surface into said epitaxial layer; a second pocket having said first conductivity type within said epitaxial layer wherein said second pocket extends from said surface into said epitaxial layer and is separated from said first pocket; an ion-implanted insulating layer overlying said surface of said epitaxial layer wherein said ions in said insulating layer have a charge polarity opposite to the charge polarity of said first conductivity type; a first electrode wherein said first electrode electrically contacts said first pocket and is electrically insulated from said epitaxial layer by said ion-implanted insulating layer; and a second electrode wherein said second electrode electrically contacts said second pocket and is electrically insulated from said epitaxial layer by said ion-implanted insulating layer whereby said ion- implanted insulating layer decreases the on- resistance of said transistor.
8. The vertical transistor of Claim 7 wherein said ion-implanted insulating layer comprises a silicon dioxide layer.
9. The vertical transistor of Claim 7 wherein said epitaxial layer further includes a third pocket having said second conductivity type and extending from said surface into said layer wherein said second pocket is centered between said first and third pockets.
10. A method for improving the on-resistance of a vertical transistor including the steps of: forming an insulating layer over a surface; and ion-implanting said insulating layer with ions having a charge polarity the same as the charge polarity of a gate region of said vertical transistor.
11. The method of Claim 10 wherein said insulating layer comprises a silicon dioxide layer.
12. The method of Claim 11 wherein said silicon dioxide layer has a thickness in the range of 0.1 μm to 2 μm.
13. The method of Claim 12 wherein said silicon dioxide layer has a thickness of about 0.7 μm.
14. The method of Claim 10 ion-implanting step uses an ion-implant charge dose in the range of 10u cm"2 to 1014 cm"2.
15. The method of Claim 14 wherein said ion-implant charge dose is about 1012 cm"2
16. The method of Claim 10 wherein the implanted ion is selected from the group of ions consisting of fluorine, chlorine, bromine, iodine, and astatine. 17. The method of Claim 16 wherein the implanted ion is iodine
18. The method of Claim 10 wherein the implanted ion is selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium.
19. The method of Claim 18 wherein the implanted ion is cesium.
20. A unipolar transistor comprising: a support of a first conductivity type; a layer of said first conductivity disposed on said support wherein said layer includes; a first pocket having a second conductivity type within said layer wherein an upper surface of said first pocket is a first predetermined distance from said surface of said layer and a lower surface of said pocket is a second predetermined distance from said surface of said layer wherein said first pocket comprises a gate region of said unipolar transistor; and a second pocket having said first conductivity type within said layer wherein said second pocket extends from said surface of said layer into said layer said first predetermined distance and contacts said first pocket so that a junction is formed which increases the overdrive capability of said unipolar transistor.
21. The unipolar transistor of Claim 20 further comprising a third pocket having said first conductivity type within said layer wherein said third pocket extends into said layer from said surface of said layer and is separated from said first and second pockets. .22. The unipolar transistor of Claim 21 further comprising an insulating layer disposed on said layer in the region separating said second and third pockets.
23. The unipolar transistor of Claim 22 wherein said layer further includes a fourth pocket having said second conductivity type and further wherein (i) an upper surface of said fourth pocket is said first predetermined distance from said surface of said layer and a lower surface of said pocket is said second predetermined distance from said surface of said layer and (ii) is separated from said other pockets.
24. The unipolar transistor of Claim 23, further comprising a fifth pocket having said first conductivity type within said layer wherein said fifth pocket (i) extends from said surface of said layer into said layer said first predetermined distance and contacts said fourth pocket so that a junction is formed and (ii) is separated from said third pocket.
25. The unipolar transistor of Claim 24 wherein said insulating layer is disposed on the surface of said layer in the region separating said third pocket from said fifth pocket.
26. The unipolar transistor of Claim 25 wherein said insulating layer comprises silicon dioxide.
27. The unipolar transistor of Claim 25 wherein said third pocket is centered between said second and fifth pockets.
28. The unipolar transistor of Claim 27 further comprising a first electrode wherein said first electrode electrically contacts said second pocket and is electrically insulated from said layer by said insulating layer .
29. The unipolar transistor of Claim 28 further comprising a second electrode wherein said second electrode electrically contacts said third pocket and is electrically insulated from said layer by said insulating layer.
30. The unipolar transistor of Claim 29 further comprising a third electrode wherein said third electrode electrically contacts said fifth pocket and is electrically insulated from said layer by said insulating layer.
31. A vertical transistor comprising: a highly doped semiconductor layer of a first conductivity type; an epitaxial layer of said first conductivity type overlying said highly doped semiconductor layer and having a surface opposite said highly doped semiconductor layer; a first pocket having a second conductivity type within said epitaxial layer wherein an upper surface of said first pocket is a first predetermined distance from said surface of said epitaxial layer and a lower surface of said pocket is a second predetermined distance from said surface of said epitaxial layer; a second pocket having said first conductivity type within said epitaxial layer wherein said second pocket extends from said surface of said epitaxial layer into said epitaxial layer said first predetermined distance and contacts said first pocket so that a junction is formed which increases the overdrive capability of said transistor; a third pocket having said first conductivity type within said epitaxial layer wherein said third pocket extends into said epitaxial layer from said surface of said layer and is separated from said first and second pockets; a fourth pocket having said second conductivity type within said epitaxial layer wherein (i) an upper surface of said fourth pocket is said first predetermined distance from said surface of said epitaxial layer and a lower surface of said pocket is said second predetermined distance from said surface of said epitaxial layer and (ii) is separated from said other pockets; a fifth pocket having said first conductivity type within said epitaxial layer wherein said fifth pocket (i) extends from said surface of said epitaxial layer into said epitaxial layer said first predetermined distance and contacts said fourth •pocket so that a junction is formed and (ii) is separated from said third pocket. an insulating layer disposed on the surface of said layer in the region separating said second and third pockets and in the region separating said third and fifth pockets; a first electrode wherein said first electrode electrically contacts said second pocket and is electrically insulated from said layer by said insulating layer; a second electrode wherein said second electrode electrically contacts said third pocket and is electrically insulated from said layer by said insulating layer; and a third electrode wherein said third electrode electrically contacts said fifth pocket and is electrically insulated from said layer by said insulating layer.
32. The vertical transistor of Claim 31 wherein said third pocket is centered between said second and fifth pockets .
33. The vertical transistor of Claim 31 wherein said insulating comprises silicon dioxide.
34. A method of improving the overdrive capability of a unipolar transistor having a gate region of a first conductivity type extending a predetermined distance into a layer from a surface of the layer comprising: forming a region of a second conductivity in said gate region so that said second conductivity region extends a second predetermined distance into said gate region from said surface wherein said second predetermined distance is less that said first predetermined distance so that a junction is formed between the portion of said gate region remaining in said layer and said second conductivity region.
35. The method of Claim 34 wherein said region of second conductivity is formed in the same processing step as a source of said unipolar transistor.
36. A unipolar transistor comprising: a support of a first conductivity type; a layer of said first conductivity disposed on said support wherein said layer includes: a first pocket having a second conductivity type within said layer wherein an upper surface of said first pocket is a first predetermined distance from said surface of said layer and a lower surface of said pocket is a second predetermined distance from said surface of said layer; a second pocket having said first conductivity type in said layer wherein said second pocket extends from said surface of said layer into said layer said first predetermined distance and contacts said first pocket so that a junction is formed which increases the overdrive capability of said unipolar transistor; and a third pocket having said first conductivity type wherein said third pocket extends into said layer from said surface of said layer and is separated from said second pocket; and an ion-implanted insulating layer disposed on the surface of said layer in the region separating said second and third pockets wherein said ions in said insulating layer have a charge polarity opposite to the charge polarity of said first conductivity type.
37. The unipolar transistor of Claim 36 wherein said layer further includes a fourth pocket having said second conductivity type and further wherein (i) an upper surface of said fourth pocket is said first predetermined distance from said surface of said layer and a lower surface of said pocket is said second predetermined distance from said surface of said layer and (ii) is separated from said other pockets.
38. The unipolar transistor of Claim 37, further comprising a fifth pocket having said first conductivity type within said layer and further wherein said fifth pocket (i) extends from said surface of said epitaxial layer into said epitaxial layer said first predetermined distance and contacts said fourth pocket so that a junction is formed, and (ii) is separated from said third pocket.
39. The unipolar transistor of Claim 38 wherein said ion-implanted insulating layer is disposed on the surface of said layer in the region separating said third pocket from said fifth pocket.
40. The unipolar transistor of Claim 39 wherein said third pocket is centered between said second and fifth pockets.
41. The unipolar transistor of Claim 39 further comprising a first electrode wherein said first electrode electrically contacts said second pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
42. The unipolar transistor of Claim 41 further comprising a second electrode wherein said second electrode electrically contacts said third pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
43. The unipolar transistor of Claim 42 further comprising a third electrode wherein said third electrode electrically contacts said fifth pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
44. The unipolar transistor of Claim 36 wherein said ion-implanted insulating layer comprises a silicon dioxide layer.
45. A vertical transistor comprising: a highly doped semiconductor layer of a first conductivity type; an epitaxial layer of said first conductivity type overlying said highly doped semiconductor layer and having a surface opposite said highly doped semiconductor layer; a first pocket having a second conductivity type within said epitaxial layer wherein an upper surface .of said irst pocket is a first predetermined distance from said surface of said epitaxial layer and a lower surface of said pocket is a second predetermined distance from said surface of said epitaxial layer; a second pocket having said first conductivity type within said epitaxial layer wherein said second pocket extends from said surface of said epitaxial layer into said epitaxial layer said first predetermined distance and contacts said first pocket so that a junction is formed which increases the overdrive capability of said transistor; a third pocket having said first conductivity type within said epitaxial layer wherein said third pocket extends into said epitaxial layer from said surface of said layer and is separated from said first and second pockets; a fourth pocket having second conductivity type within said epitaxial layer wherein (i) an upper surface of said fourth pocket is said first predetermined distance from said surface of said epitaxial layer and a lower surface of said pocket is said second predetermined distance from said surface of said epitaxial layer and (ii) is separated from said other pockets; a fifth pocket having said first conductivity type within said epitaxial layer wherein said fifth pocket (i) extends from said surface of said epitaxial layer into said epitaxial layer said first predetermined distance and contacts said fourth pocket so that a junction is formed and (ii) is separated from said third pocket. an ion-implanted insulating layer disposed on the surface of said layer in the region separating said second and third pockets and in the region separating said third and fifth pockets wherein said ions have a charge polarity opposite to the charge polarity of said first conductivity type; a first electrode wherein said first electrode electrically contacts said second pocket and is electrically insulated from said layer by said ion- implanted insulating layer; a second electrode wherein said second electrode electrically contacts said third pocket and is electrically insulated from said layer by said ion- implanted insulating layer; and a third electrode wherein said third electrode electrically contacts said fifth pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
46. The vertical transistor of Claim 45 wherein said third pocket is centered between said second and fifth pockets.
47. The vertical transistor of Claim 45 wherein said ion-implanted insulating layer comprises a silicon dioxide layer.
48. A vertical transistor comprising: a highly doped semiconductor layer of a first conductivity type; an epitaxial layer of said first conductivity type overlying said highly doped semiconductor layer and having a surface opposite said highly doped semiconductor layer; a first pocket having a second conductivity type within said epitaxial layer wherein said second conductivity pocket extends from said surface into said epitaxial layer a first predetermined distance; a second pocket having said first conductivity type within said epitaxial layer wherein said first conductivity pocket extends from said surface into said epitaxial layer and is separated from said second pocket wherein said pockets are included in an active area of said vertical transistor; and a third pocket having said second conductivity type wherein said third pocket (i) is separated from and surrounds said active area and (ii) extends from said surface into said epitaxial layer a second predetermined distance wherein said first predetermined distance is less than said second predetermined distance.
49. The vertical transistor of Claim 48 wherein said active area further comprises a fourth pocket having said second conductivity type within said epitaxial layer and further wherein said fourth conductivity pocket (i) extends from said surface into said epitaxial layer said first predetermined distance and (ii) is separated from said second pocket.
50. The vertical transistor of Claim 49 further comprising an insulating layer disposed on said the surface of said layer wherein said insulating layer is disposed on the surface of said layer in the region separating said third pocket from said fifth pocket and in the region separating said second pocket from said third pocket.
51. The vertical transistor Claim 50 wherein said insulating layer comprises silicon dioxide.
52. The vertical transistor of Claim 50 wherein said third pocket is centered between said second and fifth pockets.
53. The vertical transistor of Claim 50 further comprising a first electrode wherein said first electrode electrically contacts said first pocket and is electrically insulated from said layer by said insulating layer..
54. The vertical transistor of Claim 53 further comprising a second electrode wherein said second electrode electrically contacts said second pocket and is electrically insulated from said layer by said insulating layer.
55. The vertical transistor of Claim 54 further comprising a third electrode wherein said third electrode electrically contacts said fourth pocket and is electrically insulated from said layer by said insulating layer.
56. The vertical transistor of Claim 48 wherein said first predetermined distance is in the range of 0.5 μm to 10 μm.
57. The vertical transistor of Claim 56 wherein said first predetermined distance is about 2.5 μm.
58. The vertical transistor of Claim 48 wherein said second predetermined distance is in the range of 0.5 μm to 10 μm.
59. The vertical transistor of Claim 58 wherein said second predetermined distance is about 3 μm.
60. A method for improving the breakdown voltage of a vertical transistor having a drain region and an active area that includes a source region comprising the steps of: implanting a guard ring region about said active area with ions of a first conductivity type in a first processing step; and implanting a gate region of said transistor with ions of said first conductivity type in a processing step different from said first implanting step so that the characteristics of said gate region and the characteristics of said guard ring region are determined in different processing steps.
61. A method for forming a vertical transistor with improved breakdown voltage capability comprising the steps of: depositing a masking material over a layer of a first conductivity type; forming openings in said masking material wherein said openings surround an area in which source and gate regions of said transistor are formed in subsequent processing steps; implanting ions of a second conductivity type in said layer through said openings to form a guard ring implant region; forming an insulating layer over said layer; creating openings in said insulating layer to expose surface areas of said layer that will become said gate regions of said transistor; and implanting ions of a second conductivity type in said layer through said openings whereby said gate region is formed with characteristics different from the characteristics of said guard ring region.
62. A vertical transistor comprising: a highly doped semiconductor layer of a first conductivity type; an epitaxial layer of said first conductivity type overlying said highly doped semiconductor layer and having a surface opposite said highly doped semiconductor layer; a first pocket having a second conductivity type in said epitaxial layer wherein said second conductivity pocket extends from said surface into said epitaxial layer a first predetermined distance; a second pocket having said first conductivity type in said epitaxial layer wherein said first conductivity pocket extends from said surface into said epitaxial layer and is separated from said second pocket wherein said pockets are included in an active area of said transistor; a third pocket having said second conductivity type wherein said third pocket (i) is separated from and surrounds said active area and (ii) extends from said surface into said epitaxial layer a second predetermined distance wherein said first predetermined distance is less than said second predetermined distance; and an ion-implanted insulating layer disposed on said surface of said layer wherein said ion-implanted insulating layer is disposed on the surface of said layer in the region separating said first pocket from said second pocket and the ions implanted in said insulating layer have a charge polarity opposite to the charge polarity of the first conductivity type.
63. The vertical transistor of Claim 62 wherein said active area further comprises a fourth pocket having said second conductivity type in said epitaxial layer and further wherein said fourth conductivity pocket (i) extends from said surface into said epitaxial layer said first predetermined distance and (ii) is separated from said second pocket.
64. The vertical transistor of Claim 63 wherein said ion-implanted insulating layer is disposed on said the surface of said layer in the region separating said second pocket from said fourth pocket.
65. The vertical transistor Claim 64 wherein said ion-implanted insulating layer comprises silicon dioxide. 66. The vertical transistor of Claim 59 wherein said second pocket is centered between said first and fourth pockets.
67. The vertical transistor of Claim 63 further comprising a first electrode wherein said first electrode electrically contacts said first pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
68. The vertical transistor of Claim 67 further comprising a second electrode wherein said second electrode electrically contacts said second pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
69. The vertical transistor of Claim 67 further comprising a third electrode wherein said third electrode electrically contacts said fourth pocket and is electrically insulated from said layer by said ion- implanted insulating layer.
70. A vertical transistor comprising: a highly doped semiconductor layer of a first conductivity type; an epitaxial layer of said first conductivity type overlying said highly doped semiconductor layer and having a surface opposite said highly doped semiconductor layer; a first pocket having a second conductivity type within said epitaxial layer wherein an upper surface of said first pocket is a first predetermined distance from said surface of said epitaxial layer and a lower surface of said pocket is a second predetermined distance from said surface of said epitaxial layer; a second pocket having said first conductivity type within said epitaxial layer wherein said second pocket extends from said surface of said epitaxial layer into said epitaxial layer said first predetermined distance and contacts said first pocket so that a junction is formed; a third pocket having said first conductivity type in said epitaxial layer wherein said third pocket extends from said surface and is separated from said second pocket and further wherein said pockets are included in an active area of said transistor; an ion-implanted insulating layer disposed on the surface of said epitaxial layer in the region separating said second and third pockets wherein the ions in said insulating layer have the same charge polarity as the charge of said second conductivity type; and a fourth pocket having said second conductivity type wherein said fourth pocket (i) is separated from and surrounds said active area and (ii) extends from said surface into said epitaxial layer a third predetermined distance wherein said second predetermined distance is less than said third predetermined distance.
71. The vertical transistor of Claim 70 wherein said active area further comprises a fifth pocket having said second conductivity type within said epitaxial layer and further wherein (i) an upper surface of said fifth pocket is said first predetermined distance from said surface of said epitaxial layer and a lower surface of said pocket is said second predetermined distance from said surface of said epitaxial layer and (ii) is separated from said other pockets.
72. The vertical transistor of Claim 71 wherein said active area further comprises a sixth pocket having said first conductivity type within said epitaxial layer and further wherein said sixth pocket (i) extends from said surface of said epitaxial layer into said epitaxial layer said first predetermined distance and contacts said fifth pocket so that a junction is formed and (ii) is separated from said third pocket.
73. The vertical transistor of Claim 72 wherein said ion-implanted insulating layer is disposed on said the surface of said epitaxial layer in the region separating said third pocket from said sixth pocket.
74. The vertical transistor Claim 73 wherein said ion-implanted insulating layer comprises silicon dioxide.
75. The vertical transistor of Claim 69 wherein said third pocket is centered between said second and sixth pockets.
76. The vertical transistor of Claim 73 further comprising a first electrode wherein said first electrode electrically contacts said second pocket and is electrically insulated from said epitaxial layer by said ion-implanted insulating layer.
77. The vertical transistor of Claim 76 further comprising a second electrode wherein said second electrode electrically contacts said third pocket and is electrically insulated from said epitaxial layer by said ion-implanted insulating layer.
78. The vertical transistor of Claim 77 further comprising a third electrode wherein said third electrode electrically contacts said sixth pocket and is electrically insulated from said epitaxial layer by said ion-implanted insulating layer. 79. The vertical transistor of Claim 70 wherein said second predetermined distance is in the range of 0.5 μm to 10 μm.
80. The vertical transistor of Claim 79 wherein said second predetermined distance is about 2.5 μm.
81. The vertical transistor of Claim 70 wherein said third predetermined distance is in the range of 0.5 μm to 10 μm.
82. The vertical transistor of Claim 82 wherein said third predetermined distance is about 3 μm.
83. A vertical transistor comprising: a support of a first conductivity type; a layer of said first conductivity type overlying said support and having a surface opposite said support; a first pocket having a second conductivity type within said layer wherein said pocket has (i) a surface a first predetermined distance from said surface of said layer and (ii) a first end and a second end; a second pocket having said first conductivity type within said layer wherein said second pocket extends from said surface of said layer into said layer a second predetermined distance; and ion-implanted insulating layer regions overlying said layer wherein a first region surrounds said first end of said first pocket and a second region surrounds second end of said first pocket wherein said ions in said ion-implanted insulating layer regions have a charge polarity opposite to the charge polarity of said second conductivity type thereby improving the breakdown voltage of said transistor. 84. The vertical transistor of Claim 83 further comprising a third pocket having said second conductivity type within said layer wherein said pocket has (i) a lower surface said first predetermined distance from said surface of said epitaxial layer and (ii) a first end and a second end, and is separated from said pockets.
85. The vertical transistor of Claim 83 wherein said first ion-implanted insulated layer region surrounds said first end of said third pocket and said second ion- implanted insulated layer region surrounds said second end of said third pocket.
86. The vertical transistor of Claim 84 or 83 wherein said ion-implanted regions overlap the ends of said pockets in the range of 2 μm to 10 μm.
87. The vertical transistor of Claim 86 wherein said ion-implanted regions overlap the ends of said pockets about 5 μm.
88. The vertical transistor Claim 83 wherein said ion-implanted insulating layer comprises silicon dioxide.
89. The transistor in any one of Claims 1, 20, 36 or 83 wherein said support comprises a highly doped semiconductor layer of said first conductivity type.
90. The transistor in any one of Claims 1, 20, 36 or 83 wherein said layer comprises an epitaxial layer.
91. The transistor of Claim 90 wherein said epitaxial layer has a thickness in the range of 2 micrometers (μm) to 20 μm.
92. The transistor of Claim 91 wherein said epitaxial layer has a thickness of about 10 μm. •93. The transistor in any one of Claims 7, 31, 45, 48, or 70 wherein said epitaxial layer has a thickness in the range of 2 micrometers (μm) to 20 μm.
94. The transistor of Claim 93 wherein said epitaxial layer has a thickness of about 10 μm.
95. The transistor in any one of Claims 2, 8, 26, 33, 44, 47, 51, 65, 74, or 88 wherein said silicon dioxide layer has a thickness in the range of 0.1 μm to 2 μm.
96. The transistor of Claim 95 wherein said silicon dioxide layer has a thickness of about 0.7 μm.
97. The transistor in any one of Claims 1, 7, 20, 30, 36, 45, 48, 62, 70 or 83 wherein said first conductivity type is N type conductivity.
98. The transistor of Claim 97 wherein said second conductivity type is P type conductivity.
99. The transistor in any one of Claims 1, 7, 20, 30, 36, 45, 48, 62, 70 or 83 having a pitch in the range of 2.6 μm to 22 μm.
100. The transistor of Claims 99 having a pitch of about 3.6 μm.
101. The transistor in any one of Claims 1, 7, 36, 45, 62 or 70 wherein said ion-implanted insulating layer is formed a processing step including implanting the insulating layer with an ion-implant charge dose in the range of lθn cm"2 to 1014 cm"2.
102. The transistor of Claim 101 wherein said ion- implant charge dose is about 1012 cm"2 103. The transistor in any one of Claims 1, 7, 36, 45, 62 or 70 wherein the ion-implanted in said ion- implanted insulating layer is selected from the group of ions consisting of fluorine, chlorine, bromine, iodine, and astatine.
104. The transistor of Claim 103 wherein the ion- implanted in said insulating layer is iodine
105. The transistor in any one of Claims 1, 7, 36, 45, 62 or 70 wherein the ion-implanted in said ion- implanted insulating layer is selected from the group of ions consisting of lithium, sodium, potassium, rubidium, cesium and francium.
106. The transistor of Claim 105 wherein the ion- implanted in said insulating layer is cesium.
PCT/US1992/006182 1991-07-30 1992-07-29 High frequency jfet and method for fabricating the same WO1993003503A1 (en)

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EP0598794A1 (en) 1994-06-01
US5321283A (en) 1994-06-14
AU2415892A (en) 1993-03-02

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