WO1992020205A1 - Tapered semiconductor device package - Google Patents
Tapered semiconductor device package Download PDFInfo
- Publication number
- WO1992020205A1 WO1992020205A1 PCT/US1992/003005 US9203005W WO9220205A1 WO 1992020205 A1 WO1992020205 A1 WO 1992020205A1 US 9203005 W US9203005 W US 9203005W WO 9220205 A1 WO9220205 A1 WO 9220205A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- tapered
- substrate
- peripheral portion
- package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Definitions
- This invention relates generally to electronic packages and more specifically to molded semiconductor device packages.
- Molded chip carrier packages have become a popular form of integrated circuit packaging, as they provide for a large number of interconnections in a small package.
- An array of pins having a standard spacing (for example, 0.100 inches center to center) is located on a substrate so that the pins extends outward from one face of the substrate to join with sockets on a main printed circuit board.
- An integrated circuit or semiconductor device is mounted on the top side of the substrate and wire bonds are made between the bonding pads of the integrated circuit and the traces on the substrate.
- the integrated circuit, the leads, and the wire bonds are then covered with an encapsulant by transfer molding a thermoset plastic composition over the device and the substrate.
- the assembly to be encapsulated is located inside a metal mold which has recesses defining the shape of the cover to be produced.
- Solid plastic is heated and forced under pressure through gates into the mold. The heat and pressure causes the plastic to liquify and flow into the mold cavities surrounding the integrated circuit.
- the mold is heated to cure the plastic and the molded assembly is then removed from the mold.
- Molded pad grid array packages are formed in a similar manner. These types of packages have traditionally been made in a rectangular form with substantially parallel sides, with the molded portion being reminiscent of a 'domino' shape.
- the basic characteristics of transfer molding are taught in U.S. Patent No. 4,460,537.
- a transfer molded package inherently retains stress after molding and develops stress during thermal excursions and mechanical bending due to differences in mechanical properties, Young's modulus, coefficients of thermal expansion of the system components, and variations in physical sizes. Mechanical bending imposed upon the package, after it is soldered to the main circuit board, also creates undesired stresses.
- stress is placed on the molding compound by heating or cooling the molded package, the area of highest stress in the molding compound occurs directly over the integrated circuit and at the interface between the molding compound and the substrate. This is the weakest link in the package, and can lead to premature failure of the package by cracking or breaking the molding compound, allowing ingress of environmental contaminants and resulting corrosion and failure of the integrated circuit.
- the susceptibility of the molding compound to fracture increases dramatically, thereby limiting the use of transfer molded chip carriers to relatively small integrated circuits.
- a semiconductor device package A semiconductor device is attached to a first side of a carrier substrate, and an encapsulant material is molded about the semiconductor device.
- the encapsulant material covers the semiconductor device and most of the first side of the carrier substrate.
- the center portion of the molded material over the semiconductor device is of uniform thickness and substantially parallel to the semiconductor device.
- a peripheral portion of the molded material is tapered away from the center of the device, such that the cross-sectional thickness of the tapered area diminishes as the edge of the carrier substrate is approached.
- FIG. 1 is a cut-away plan view of a semiconductor package in accordance with the present invention.
- FIG. 2 is a cross-sectional view of a semiconductor package through section A-A of FIG. 1.
- FIG. 3 is an elevational view of a semiconductor package in accordance with the present invention.
- a leadless, transfer-molded, chip carrier 10 is made by attaching an integrated circuit chip or semiconductor device 12 to a circuit carrying substrate 14.
- Chips may also be attached to the same substrate, as in a multi-chip module. While the preferred embodiment as described herein consists of a chip carrier, the invention may also be utilized to advantage in applications where the substrate is larger than a chip carrier, i.e. an entire circuit board. In these applications, the semiconductor device in but one of a number of components on the substrate. Mounting the component on the substrate in this manner is known as chip-on-board, or COB.
- the circuit carrying substrate is a resinous, glass reinforced printed circuit board such as epoxy-glass or polyimide-glass, but may also consist of other materials such as flexible circuitry made from polyimide, polyester, or polyetherimide film, or a TAB bonded substrate with metal fingers, or even a stamped or etched metal substrate as employed in flat packs and DIPs.
- the circuit-carrying substrate 14 has a metallization pattern 16 on the upper surface, where the integrated circuit 12 is attached and wire-bonded, TAB bonded or flip chip attached.
- the assembly is transfer-molded using a thermoplastic or thermoset molding compound, preferably a thermoset epoxy, to produce a cover.
- the cover 18 is molded about the chip in order to encapsulate and cover the chip 12 and all the associated interconnections 19, and covers nearly all the top surface of the circuit carrying substrate 14. It can be seen that the upper surface of the circuit carrying substrate 14 is not totally covered by the molding compound, but a small portion 20 around the peripheral edge of the substrate is left exposed in order to facilitate fixturing the assembly in the mold. In the preferred embodiment, an exposed portion of at least 0.010 inches is provided.
- the molding compound 18 may extend to the edges of the substrate 14 but will preferably terminate a short distance from the edges of the substrate 14 in order to aid in handling during subsequent assembly operations.
- the molded cover 18 contains a central area 24 that lies over the semiconductor device, that is planar and essentially parallel to the plane of the semiconductor device.
- the molded cover 18 also contains a tapered portion 22 at the periphery of the central area 24 that is an area of gradually reduced thickness of molding compound beyond the area where the semiconductor device 12 is mounted.
- the tapered area 22 is typically located beyond an area defined by the perimeter of the upper portion of the wire bonds.
- the corners 26 of the molded cover 18 can also be chamfered to enhance the reliability of the package as shown in FIG. 1.
- the stress imparted to the molding compound during thermal and mechanical shock is significantly reduced.
- this stress is reduced by about 8 percent as compared to prior art package designs utilizing non-tapered or substantially perpendicular sidewalls.
- the reliability of a tapered package is thereby improved.
- reduced thickness of the molding compound is desired, the package could not be fabricated by simply reducing the thickness of the entire molded package, since a certain minimum thickness of compound is required in the area above the wire bonds in order to protect them.
- By creating an area of tapered thickness the total mass of the package is reduced, thereby reducing the stress near the edges of the package, where stress levels are highest.
- the tapered area should be as large as possible, but practicality dictates that it must not interfere with the wire bonds. In any case, the tapered area should not encroach upon the perimeter of the integrated circuit die.
- the shape of the tapered area normally approximates the shape of the integrated circuit, typically a square or rectangular configuration. However, if desired, other shapes such as circular, ellipsoid, oval, or irregular shapes may be employed in order to achieve a similar result.
- the amount of taper should be between about 2 degrees and about 75 degrees from horizontal as shown in FIG. 3, with about 15 degrees being a typical value for a preferred embodiment transfer molded chip carrier.
- taper 22 Another way of describing the tapered shape is is to envision the taper 22 as being referenced to the horizontal plane of the central area 24 of the molded cover 18, originating there and extending downward toward the substrate 14. Tapers greater than 75 degrees have little practical value in reducing stresses, while those less than 2 degrees create a package too large to be of practical value. In practice, tapers should be at least 10 degrees. A minimum thickness of molding compound should be maintained near the cover perimeter, typically about 0.010 inches. Since the purpose of creating an taper is to relieve stress, one should seek to maximize the tapered area in order to realize the greatest stress reduction. In practice, a trade-off between the ability to mold a quality package and the need to minimize stress is always present, and the those skilled in the art will recognize the limitations and optimum design for each particular package.
- Finite element computer models of a prior art chip carrier with substantially perpendicular sidewalls and a chip carrier made in accordance with the invention show that a high level of stress is experienced in the molding compound above the die when the package is heated.
- This stress measurement is made by modeling the physical dimensions of the package in a computer program that utilizes the fundamental material properties of the individual components of the package in conjunction with the mechanical forces acting on the package, to calculate resultant stress levels.
- the most important feature of the computer model is the ability to create comparisons between two similar configurations.
- the calculated stress levels computed at the die surface for the various package types are as follows:
- PSD Level PSH Prior Art Non-tapered Cover 8400 9300
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A semiconductor device (12) is attached to a first side of a carrier substrate (14), and an encapsulant material (18) is molded about the semiconductor device (12) to form a cover. The encapsulant material covers the semiconductor device and most of the first side of the carrier substrate (14). A central portion of the molded material over the semiconductor device is of uniform thickness and substantially parallel to the semiconductor device. The remaining peripheral portion (22) of the cover is tapered away from the center of the device (12), such that the cross-sectional thickness of the tapered area (22) diminishes as it approaches the edge of the carrier substrate.
Description
PATENT APPLICATION
TAPERED SEMICONDUCTOR DEVICE PACKAGE
Technical Field
This invention relates generally to electronic packages and more specifically to molded semiconductor device packages.
Background
Molded chip carrier packages have become a popular form of integrated circuit packaging, as they provide for a large number of interconnections in a small package. An array of pins having a standard spacing (for example, 0.100 inches center to center) is located on a substrate so that the pins extends outward from one face of the substrate to join with sockets on a main printed circuit board. An integrated circuit or semiconductor device is mounted on the top side of the substrate and wire bonds are made between the bonding pads of the integrated circuit and the traces on the substrate. The integrated circuit, the leads, and the wire bonds are then covered with an encapsulant by transfer molding a thermoset plastic composition over the device and the substrate. In transfer molding, the assembly to be encapsulated is located inside a metal mold which has recesses defining the shape of the cover to be produced. Solid plastic is heated and forced under pressure through gates into the mold. The heat and pressure causes the plastic to liquify and flow into the mold cavities surrounding the integrated circuit. The mold is heated to cure the plastic and the molded assembly is then removed from
the mold. Molded pad grid array packages are formed in a similar manner. These types of packages have traditionally been made in a rectangular form with substantially parallel sides, with the molded portion being reminiscent of a 'domino' shape. The basic characteristics of transfer molding are taught in U.S. Patent No. 4,460,537.
A transfer molded package inherently retains stress after molding and develops stress during thermal excursions and mechanical bending due to differences in mechanical properties, Young's modulus, coefficients of thermal expansion of the system components, and variations in physical sizes. Mechanical bending imposed upon the package, after it is soldered to the main circuit board, also creates undesired stresses. When stress is placed on the molding compound by heating or cooling the molded package, the area of highest stress in the molding compound occurs directly over the integrated circuit and at the interface between the molding compound and the substrate. This is the weakest link in the package, and can lead to premature failure of the package by cracking or breaking the molding compound, allowing ingress of environmental contaminants and resulting corrosion and failure of the integrated circuit. As the physical size of the integrated circuit increases, the susceptibility of the molding compound to fracture increases dramatically, thereby limiting the use of transfer molded chip carriers to relatively small integrated circuits.
Clearly, a need exists for a low-cost, high density plastic package that would overcome the inherent problems of fragility and reliability found in conventional packages. Such a package would result in improved short and long term field reliability.
Summary of the Invention
Briefly, according to the invention, there is provided a semiconductor device package. A semiconductor device is attached to a first side of a carrier substrate, and an encapsulant material is molded about the semiconductor device. The encapsulant material covers the semiconductor device and most
of the first side of the carrier substrate. The center portion of the molded material over the semiconductor device is of uniform thickness and substantially parallel to the semiconductor device. A peripheral portion of the molded material is tapered away from the center of the device, such that the cross-sectional thickness of the tapered area diminishes as the edge of the carrier substrate is approached.
Brief Description of the Drawings FIG. 1 is a cut-away plan view of a semiconductor package in accordance with the present invention.
FIG. 2 is a cross-sectional view of a semiconductor package through section A-A of FIG. 1.
FIG. 3 is an elevational view of a semiconductor package in accordance with the present invention.
Detailed Description of the Preferred Embodiment
Referring to FIG. 1 and FIG. 2, a leadless, transfer-molded, chip carrier 10 is made by attaching an integrated circuit chip or semiconductor device 12 to a circuit carrying substrate 14.
Multiple chips may also be attached to the same substrate, as in a multi-chip module. While the preferred embodiment as described herein consists of a chip carrier, the invention may also be utilized to advantage in applications where the substrate is larger than a chip carrier, i.e. an entire circuit board. In these applications, the semiconductor device in but one of a number of components on the substrate. Mounting the component on the substrate in this manner is known as chip-on-board, or COB. The circuit carrying substrate is a resinous, glass reinforced printed circuit board such as epoxy-glass or polyimide-glass, but may also consist of other materials such as flexible circuitry made from polyimide, polyester, or polyetherimide film, or a TAB bonded substrate with metal fingers, or even a stamped or etched metal substrate as employed in flat packs and DIPs. The circuit-carrying substrate 14 has a metallization pattern 16 on the upper surface, where the integrated circuit 12 is attached and wire-bonded, TAB bonded or
flip chip attached. The assembly is transfer-molded using a thermoplastic or thermoset molding compound, preferably a thermoset epoxy, to produce a cover. The cover 18 is molded about the chip in order to encapsulate and cover the chip 12 and all the associated interconnections 19, and covers nearly all the top surface of the circuit carrying substrate 14. It can be seen that the upper surface of the circuit carrying substrate 14 is not totally covered by the molding compound, but a small portion 20 around the peripheral edge of the substrate is left exposed in order to facilitate fixturing the assembly in the mold. In the preferred embodiment, an exposed portion of at least 0.010 inches is provided. The molding compound 18 may extend to the edges of the substrate 14 but will preferably terminate a short distance from the edges of the substrate 14 in order to aid in handling during subsequent assembly operations.
The molded cover 18 contains a central area 24 that lies over the semiconductor device, that is planar and essentially parallel to the plane of the semiconductor device. The molded cover 18 also contains a tapered portion 22 at the periphery of the central area 24 that is an area of gradually reduced thickness of molding compound beyond the area where the semiconductor device 12 is mounted. The tapered area 22 is typically located beyond an area defined by the perimeter of the upper portion of the wire bonds. In an alternate embodiment of the invention, the corners 26 of the molded cover 18 can also be chamfered to enhance the reliability of the package as shown in FIG. 1.
By gradually reducing the section thickness of the area beyond the edges of the integrated circuit, the stress imparted to the molding compound during thermal and mechanical shock is significantly reduced. By tapering the thickness of the molding compound around the periphery of the semiconductor device, this stress is reduced by about 8 percent as compared to prior art package designs utilizing non-tapered or substantially perpendicular sidewalls. The reliability of a tapered package is thereby improved.
Although reduced thickness of the molding compound is desired, the package could not be fabricated by simply reducing the thickness of the entire molded package, since a certain minimum thickness of compound is required in the area above the wire bonds in order to protect them. By creating an area of tapered thickness, the total mass of the package is reduced, thereby reducing the stress near the edges of the package, where stress levels are highest. The tapered area, to be most effective, should be as large as possible, but practicality dictates that it must not interfere with the wire bonds. In any case, the tapered area should not encroach upon the perimeter of the integrated circuit die. The shape of the tapered area normally approximates the shape of the integrated circuit, typically a square or rectangular configuration. However, if desired, other shapes such as circular, ellipsoid, oval, or irregular shapes may be employed in order to achieve a similar result. The amount of taper should be between about 2 degrees and about 75 degrees from horizontal as shown in FIG. 3, with about 15 degrees being a typical value for a preferred embodiment transfer molded chip carrier. Another way of describing the tapered shape is is to envision the taper 22 as being referenced to the horizontal plane of the central area 24 of the molded cover 18, originating there and extending downward toward the substrate 14. Tapers greater than 75 degrees have little practical value in reducing stresses, while those less than 2 degrees create a package too large to be of practical value. In practice, tapers should be at least 10 degrees. A minimum thickness of molding compound should be maintained near the cover perimeter, typically about 0.010 inches. Since the purpose of creating an taper is to relieve stress, one should seek to maximize the tapered area in order to realize the greatest stress reduction. In practice, a trade-off between the ability to mold a quality package and the need to minimize stress is always present, and the those skilled in the art will recognize the limitations and optimum design for each particular package. Finite element computer models of a prior art chip carrier with substantially perpendicular sidewalls and a chip carrier
made in accordance with the invention show that a high level of stress is experienced in the molding compound above the die when the package is heated. This stress measurement is made by modeling the physical dimensions of the package in a computer program that utilizes the fundamental material properties of the individual components of the package in conjunction with the mechanical forces acting on the package, to calculate resultant stress levels. The most important feature of the computer model is the ability to create comparisons between two similar configurations. The calculated stress levels computed at the die surface for the various package types are as follows:
Package Type Thermal Stress Mechanical Stress
Level (PSD Level (PSH Prior Art Non-tapered Cover 8400 9300
Tapered Cover 8000 8600
Note that there is about an 8% reduction in the maximum stress level in the model of the invention as compared to the model of the prior art. The use of the invention creates a lower cost, higher reliability package. The tapered sides, with the smaller cross-sectional area, impart a lower stress to the molding compound-substrate interface near the substrate edge during environmental excursions. By lowering stress levels, adhesion failures at this interface are reduced. Stress concentrations arising from mechanical bending, once the IC package is interconnected to the circuit, are also minimized. Vibration and shock are commonplace in portable communication equipment, and are known to cause mechanical bending of the package. The positive effect of the tapered molding compound in bending arises from the reduced cross-sectional area, allowing the mold compound to bend more freely with the substrate instead of resisting.
Various changes and modifications in the tapered semiconductor device package herein disclosed may occur to those skilled in the art; and to the extent that such changes and
modifications are embraced by the appended claims, it is to be understood that they constitute part of the present invention. The examples shown in the accompanying drawings, while illustrative, are not meant to be considered limiting and other configurations of the package are envisioned to fall within the scope of the invention.
What is claimed is:
Claims
1. A semiconductor device assembly, comprising: a carrier substrate having first and second sides; a semiconductor device attached to the first side of the carrier substrate; and an encapsulant material molded over the semiconductor device and the carrier substrate first side, the encapsulant material having a center portion over and about the semiconductor device and a tapered peripheral portion about the center portion.
2. The semiconductor assembly as described in claim 1 , wherein the peripheral portion is tapered between about 2 degrees and about 75 degrees.
3. The semiconductor assembly as described in claim 1 , wherein the encapsulant material is transfer molded.
4. A chip carrier package, comprising: a circuit carrying substrate having a plurality of contacts; a semiconductor device mounted directly on the circuit carrying substrate and electrically interconnected to at least two of said contacts; and a protective cover having an upper surface comprising a substantially planar central portion above the semiconductor device and a peripheral portion tapered toward the central portion, the cover encapsulating the semiconductor device and portions of the circuit carrying substrate.
5. The chip carrier package as described in claim 4, wherein the peripheral portion is tapered between about 2 degrees and about 75 degrees.
6. The chip carrier package as described in claim 4, wherein the tapered peripheral portion increases to its final thickness prior to reaching the perimeter of the semiconductor device.
7. The chip carrier package as described in claim 4, wherein the encapsulant material is transfer molded.
8. A leadless chip carrier package, comprising: a resinous printed circuit board having a plurality of contact pads on a bottom surface and having a semiconductor device mounted directly on an opposing upper surface, the semiconductor device being electrically interconnected to at least two of said contact pads; and a transfer molded protective cover having an upper surface comprising a substantially planar central portion above the semiconductor device and a peripheral portion, said peripheral portion being tapered in diminishing section away from the central portion, said taper comprising between about 2 degrees and about 75 degrees, the cover encapsulating the semiconductor device and portions of the upper surface of the printed circuit board.
9. The chip carrier package as described in claim 8, wherein the peripheral portion is thinnest at the substrate perimeter and increases to its final thickness prior to reaching the perimeter of the semiconductor device.
10. The chip carrier assembly as described in claim 8, wherein the cover encapsulates the semiconductor device and substantially all of the upper surface of the printed circuit board.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69189191A | 1991-04-26 | 1991-04-26 | |
US691,891 | 1991-04-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1992020205A1 true WO1992020205A1 (en) | 1992-11-12 |
Family
ID=24778391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1992/003005 WO1992020205A1 (en) | 1991-04-26 | 1992-04-13 | Tapered semiconductor device package |
Country Status (1)
Country | Link |
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WO (1) | WO1992020205A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19833039A1 (en) * | 1998-07-22 | 2000-01-27 | Elcos Gmbh Electronic Componen | Opto-electronic components encapsulated in transparent plastic to make e.g. displays, are rear-injected individually through holes in substrate to prevent undesirable segment cross-illumination |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55165654A (en) * | 1979-06-12 | 1980-12-24 | Nec Corp | Semiconductor device sealed up with thin resin |
US4688152A (en) * | 1986-08-11 | 1987-08-18 | National Semiconductor Corporation | Molded pin grid array package GPT |
-
1992
- 1992-04-13 WO PCT/US1992/003005 patent/WO1992020205A1/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55165654A (en) * | 1979-06-12 | 1980-12-24 | Nec Corp | Semiconductor device sealed up with thin resin |
US4688152A (en) * | 1986-08-11 | 1987-08-18 | National Semiconductor Corporation | Molded pin grid array package GPT |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19833039A1 (en) * | 1998-07-22 | 2000-01-27 | Elcos Gmbh Electronic Componen | Opto-electronic components encapsulated in transparent plastic to make e.g. displays, are rear-injected individually through holes in substrate to prevent undesirable segment cross-illumination |
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