WO1992001344A1 - Phase locking circuit for jitter reduction in a digital multiplex system - Google Patents

Phase locking circuit for jitter reduction in a digital multiplex system Download PDF

Info

Publication number
WO1992001344A1
WO1992001344A1 PCT/SE1991/000487 SE9100487W WO9201344A1 WO 1992001344 A1 WO1992001344 A1 WO 1992001344A1 SE 9100487 W SE9100487 W SE 9100487W WO 9201344 A1 WO9201344 A1 WO 9201344A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
amplifier
input
multiplex system
phase locking
Prior art date
Application number
PCT/SE1991/000487
Other languages
French (fr)
Inventor
Mats Bladh
Original Assignee
Telefonaktiebolaget Lm Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson filed Critical Telefonaktiebolaget Lm Ericsson
Priority to EP91913634A priority Critical patent/EP0549591B1/en
Priority to DE69128632T priority patent/DE69128632T2/en
Priority to DK91913634T priority patent/DK0549591T3/en
Priority to AU82343/91A priority patent/AU660933B2/en
Publication of WO1992001344A1 publication Critical patent/WO1992001344A1/en
Priority to NO93931566A priority patent/NO931566L/en
Priority to GR980400204T priority patent/GR3026036T3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Definitions

  • the present invention relates to a phase locking circuit for jitter reduction in a multiplex system, including a feed ⁇ back operational amplifier.
  • a phase locked circuit or loop shall lock on to frequency differences, which requires “large” gain and “large” bandwidth.
  • the output signal shall have low inherent jitter, in accordance with standards for acceptable jitter level, which requires “low” gain due to digitally generated jitter in the multiplex system.
  • the object of the present invention is to provide a new solution to the problem of inherent jitter contra phase lock ⁇ ing in a digital multiplexer of the DCC type in a simple, cheap, voluminously economic and current saving way.
  • an RC circuit is arranged before the diodes on the amplifier input to pass through frequency and phase differences, for the purpose of filtering, but to attenuate the input frequencies and input signals to the phase compara ⁇ tor.
  • a series resistance is provided on the amplifier input for dimensioning purposes.
  • This resistance is intended to limit the magnitude of the gain for an unlocked circuit, and in principle it could be included in the resistance of the above-mentioned RC circuit.
  • this gain regulation resistance separa ⁇ tely the adjustment of the gain is facilitated.
  • the amplifier is of the FET or CMOS type with a high-ohm amplifier input, so that the load from the amplifier will be low.
  • the reference voltage for the amplifier is selected such that the operation will take place substantially in the central part of the buffer store.
  • Figure 1 illustrates the location of the circuit in a practical app ⁇ lication
  • Figure 2 is a circuit diagram of the circuit.
  • the circuit 2 in accordance with the invention is connec ⁇ ted between a phase comparator 4 and a voltage controlled oscillator VCO with associated buffer store 6, as illustrated in Figure 1.
  • D in and Cl in respectively denote data and clock inputs
  • D out and Cl out respectively denote outputs for data and clock signals.
  • the circuit in accordance with the invention includes an operational amplifier OP, which is fed back by the loop R 2 , C 2 r as will be seen from Figure 2.
  • R 2 is a high-ohm resistan ⁇ ce, and the capacitor C 2 is dimensioned to give a long time constant (DC separation) .
  • One input on the amplifier OP is connected to the phase comparator via an RC circuit, which is adapted to pass fre- quency diferences and block fundamental frequencies to the phase comparator. There is thus obtained at the point A substantially the phase and frequency difference from the phase comparator and only a low superposed AC level.
  • Two anti-parallel coupled diodes O- and D 2 are connected in series with a resistance R_ between the point A and the input of the amplifier OP. Desired automatic gain control is thus realised in a very simple way.
  • the gain F will be substantially
  • R l + R D12 where R D ⁇ denotes a mean value of the resistance through the diodes.
  • the circuit according to the invention includes two anti ⁇ parallel coupled diodes D_ and D 2 to be able to operate in both directions.
  • the diodes are suitably ordinary silicon diodes.
  • the resistance R_ is selected so that the gain F will be of a suitable magnitude in the case when the diodes D 2 and D 2 are low-ohmic, i.e. when R D12 ⁇ s approximately equal to zero.
  • R_ could be included in the resistance R, but the adjustment of the gain F is facilitated by the arrange ⁇ ment of a separate resistance R_ for this purpose.
  • the ope- rational amplifier OP is suitably of the FET or CMOS type, with a high-ohm amplifier input, such that it conducts as small a current as possible through the diodes, thus making them high-ohmic.
  • the circuit may suitably operate at signal levels of 5 V, it then being suitable to choose the reference voltage Ref to the operational ampli ⁇ bomb OP equal to 2.5 V, which will mean that operation will be substantially in the middle of the buffer store 6, cf Figure 1.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Amplifiers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Networks Using Active Elements (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

A phase locking circuit for jitter reduction in a digital multiplex system includes a feed-back operational amplifier (OP). Two antiparallel coupled diodes (D1, D2) are arranged on one input of the amplifier for achieving automatic gain control, the other input of the amplifier being connected to a reference voltage (Ref).

Description

Phase Locking Circuit for Jitter Reduction in a Digital
Multiplex System
The present invention relates to a phase locking circuit for jitter reduction in a multiplex system, including a feed¬ back operational amplifier.
In a digital multiplexer of the digital cross connect (DCC) type, a phase locked circuit or loop (PLL) shall lock on to frequency differences, which requires "large" gain and "large" bandwidth. When the system has been phase locked, the output signal shall have low inherent jitter, in accordance with standards for acceptable jitter level, which requires "low" gain due to digitally generated jitter in the multiplex system.
Solutions up to now have comprised the manipulation of gain and bandwidth, with accompanying problems, either with jitter or locking. The object of the present invention is to provide a new solution to the problem of inherent jitter contra phase lock¬ ing in a digital multiplexer of the DCC type in a simple, cheap, voluminously economic and current saving way.
This object is achieved with a circuit of the kind de- scribed in the introduction, and with the characterising features stated in claim 1.
With the circuit according to the invention low gain in a locked circuit is thus obtained in a very simple way, re¬ sulting in low inherent jitter, and at the same time high gain for a circuit that has not been locked, or has a high input jitter.
According to the one embodiment of the circuit according to the invention, an RC circuit is arranged before the diodes on the amplifier input to pass through frequency and phase differences, for the purpose of filtering, but to attenuate the input frequencies and input signals to the phase compara¬ tor.
According to another advantageous embodiment of the circuit according to the invention, a series resistance is provided on the amplifier input for dimensioning purposes. This resistance is intended to limit the magnitude of the gain for an unlocked circuit, and in principle it could be included in the resistance of the above-mentioned RC circuit. However, in arranging this gain regulation resistance separa¬ tely the adjustment of the gain is facilitated.
According to another advantageous embodiment of the cir¬ cuit according to the invention, the amplifier is of the FET or CMOS type with a high-ohm amplifier input, so that the load from the amplifier will be low.
According to a further advantageous embodiment of the circuit according to the invention, the reference voltage for the amplifier is selected such that the operation will take place substantially in the central part of the buffer store.
An embodiment of the circuit according to the invention, selected as an example, will now be described more in detail with reference to the accompanying drawing on which Figure 1 illustrates the location of the circuit in a practical app¬ lication, and Figure 2 is a circuit diagram of the circuit.
The circuit 2 in accordance with the invention is connec¬ ted between a phase comparator 4 and a voltage controlled oscillator VCO with associated buffer store 6, as illustrated in Figure 1. Din and Clin respectively denote data and clock inputs, and Dout and Clout respectively denote outputs for data and clock signals.
The circuit in accordance with the invention includes an operational amplifier OP, which is fed back by the loop R2, C2 r as will be seen from Figure 2. R2 is a high-ohm resistan¬ ce, and the capacitor C2 is dimensioned to give a long time constant (DC separation) .
One input on the amplifier OP is connected to the phase comparator via an RC circuit, which is adapted to pass fre- quency diferences and block fundamental frequencies to the phase comparator. There is thus obtained at the point A substantially the phase and frequency difference from the phase comparator and only a low superposed AC level.
Two anti-parallel coupled diodes O- and D2 are connected in series with a resistance R_ between the point A and the input of the amplifier OP. Desired automatic gain control is thus realised in a very simple way.
The gain F will be substantially
F = S2
Rl + RD12 where RDι denotes a mean value of the resistance through the diodes.
For a locked PLL circuit Uuτ is constant, and a small current flows through the diodes O_ and D , which then will be high-ohmic, the gain F decreasing and the jitter being attenuated. For an unlocked PLL circuit, a larger current passes through the diodes Dx and D2, which then become low- ohmic, and the gain increases, so that the phase and fre- quency differences can be captured. There is thus obtained in a simple way the desired automtaic gain control with a smooth transition between the two states, and which thus switches to low-ohm state between high- and low-ohm states in response to variations in the input voltage UIN. The circuit according to the invention includes two anti¬ parallel coupled diodes D_ and D2 to be able to operate in both directions. The diodes are suitably ordinary silicon diodes.
The resistance R_ is selected so that the gain F will be of a suitable magnitude in the case when the diodes D2 and D2 are low-ohmic, i.e. when RD12 ^s approximately equal to zero. In principle, R_ could be included in the resistance R, but the adjustment of the gain F is facilitated by the arrange¬ ment of a separate resistance R_ for this purpose. The ope- rational amplifier OP is suitably of the FET or CMOS type, with a high-ohm amplifier input, such that it conducts as small a current as possible through the diodes, thus making them high-ohmic.
As illustrated in the figure, the circuit may suitably operate at signal levels of 5 V, it then being suitable to choose the reference voltage Ref to the operational ampli¬ fier OP equal to 2.5 V, which will mean that operation will be substantially in the middle of the buffer store 6, cf Figure 1. •

Claims

1. Phase locking circuit for jitter reduction in a di- gital multiplex system, including a feed-back operational amplifier, characterised in that two anti-parallel coupled diodes (Dlf D2) are arranged at one input to the amplifier (OP) for achieving automatic gain control, the other input to the amplifier being connected to a reference voltage.
2. Circuit as claimed in claim 1, characterised in that an RC-circuit is arranged before the diodes on the amplifier input for only letting through phase and frequency differen¬ ces for filtering purposes.
3. Circuit as claimed in claim 1 or 2, characterised in that a further series resistance (R_ ) is provided on the amp¬ lifier input for dimensioning purposes.
4. Circuit as claimed in any one of claims 1-3, charac¬ terised in that the amplifier is of the FET or CMOS type, with high-ohmic amplifier input.
5. Circuit as claimed in any one of claims 1-4, charac¬ terised in that the reference voltage for the amplifier is selected such that operation will be substantially in the middle of a buffer store (6) .
PCT/SE1991/000487 1990-07-10 1991-07-09 Phase locking circuit for jitter reduction in a digital multiplex system WO1992001344A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP91913634A EP0549591B1 (en) 1990-07-10 1991-07-09 Phase locking circuit for jitter reduction in a digital multiplex system
DE69128632T DE69128632T2 (en) 1990-07-10 1991-07-09 PHASE LOCKING ARRANGEMENT FOR JITTER REDUCTION IN A DIGITAL MULTIPLEX SYSTEM
DK91913634T DK0549591T3 (en) 1990-07-10 1991-07-09 Phase-locked circuit for reducing jitter in a digital multiplex system
AU82343/91A AU660933B2 (en) 1990-07-10 1991-07-09 Phase locking circuit for jitter reduction in a digital multiplex system
NO93931566A NO931566L (en) 1990-07-10 1993-04-29 PHASELAS CIRCUIT FOR REDUCING DIRING IN A DIGITAL MULTIPLEX SYSTEM
GR980400204T GR3026036T3 (en) 1990-07-10 1998-01-30 Phase locking circuit for jitter reduction in a digital multiplex system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9002408-4 1990-07-10
SE9002408A SE466474B (en) 1990-07-10 1990-07-10 CLEARING CIRCUIT FOR JITTER REDUCTION IN DIGITAL MULTIPLEX SYSTEM

Publications (1)

Publication Number Publication Date
WO1992001344A1 true WO1992001344A1 (en) 1992-01-23

Family

ID=20379985

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1991/000487 WO1992001344A1 (en) 1990-07-10 1991-07-09 Phase locking circuit for jitter reduction in a digital multiplex system

Country Status (13)

Country Link
EP (1) EP0549591B1 (en)
AU (1) AU660933B2 (en)
CA (1) CA2095350C (en)
DE (1) DE69128632T2 (en)
DK (1) DK0549591T3 (en)
ES (1) ES2110994T3 (en)
FI (1) FI932330A0 (en)
GR (1) GR3026036T3 (en)
IE (1) IE80859B1 (en)
MX (1) MX9100088A (en)
NO (1) NO931566L (en)
SE (1) SE466474B (en)
WO (1) WO1992001344A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598445A (en) * 1994-03-28 1997-01-28 Alcatel N.V. Jitter reduction system in digital demultiplexers
WO1999063670A1 (en) * 1998-06-04 1999-12-09 Adc Telecommunications, Inc. Phase-locked loop with a loop filter

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3420956A (en) * 1966-01-04 1969-01-07 Bell Telephone Labor Inc Jitter reduction in pulse multiplexing systems employing pulse stuffing
US3830981A (en) * 1973-04-02 1974-08-20 Bell Northern Research Ltd Pulse stuffing control circuit for reducing jitter in tdm system
US3920915A (en) * 1972-09-28 1975-11-18 Siemens Ag Circuit arrangement for mutual synchronization of the clock oscillators provided in the central offices of a pcm time-division multiplex telecommunication network
DE2931401A1 (en) * 1979-07-31 1981-02-19 Siemens Ag Sine wave-to-rectangular wave converter - has extra RC feedback from phase inverter output to amplifier input
US4393279A (en) * 1980-06-16 1983-07-12 The Post Office Digital data transmission system having frequency or phase modulated data carrying signals to provide supervisory channel
US4397017A (en) * 1981-03-02 1983-08-02 Nippon Electric Co., Ltd. Stuff synchronization device with reduced sampling jitter
EP0100077A2 (en) * 1982-07-26 1984-02-08 Siemens Aktiengesellschaft Circuit arrangement for clock generation in communication installations, especially TDM digital exchanges
EP0197492A2 (en) * 1985-04-01 1986-10-15 Qiang Hua University A method and an apparatus for modeling bit rate justification
FR2593337A1 (en) * 1986-01-23 1987-07-24 Berlinet Denis Device for synchronising a binary signal with elimination of jitter
US4730347A (en) * 1985-06-10 1988-03-08 Alcatel Method and apparatus for reducing jitter in a synchronous digital train for the purpose of recovering its bit rate
EP0266588A1 (en) * 1986-10-20 1988-05-11 Siemens Aktiengesellschaft Phase-locked loop
US4825437A (en) * 1986-04-22 1989-04-25 Telecommunications Radioelectriques Et Telephoniques T.R.T. Clock recovery arrangement especially for an information transmission system using the TDMA principle in one transmission direction

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3420956A (en) * 1966-01-04 1969-01-07 Bell Telephone Labor Inc Jitter reduction in pulse multiplexing systems employing pulse stuffing
US3920915A (en) * 1972-09-28 1975-11-18 Siemens Ag Circuit arrangement for mutual synchronization of the clock oscillators provided in the central offices of a pcm time-division multiplex telecommunication network
US3830981A (en) * 1973-04-02 1974-08-20 Bell Northern Research Ltd Pulse stuffing control circuit for reducing jitter in tdm system
DE2931401A1 (en) * 1979-07-31 1981-02-19 Siemens Ag Sine wave-to-rectangular wave converter - has extra RC feedback from phase inverter output to amplifier input
US4393279A (en) * 1980-06-16 1983-07-12 The Post Office Digital data transmission system having frequency or phase modulated data carrying signals to provide supervisory channel
US4397017A (en) * 1981-03-02 1983-08-02 Nippon Electric Co., Ltd. Stuff synchronization device with reduced sampling jitter
EP0100077A2 (en) * 1982-07-26 1984-02-08 Siemens Aktiengesellschaft Circuit arrangement for clock generation in communication installations, especially TDM digital exchanges
EP0197492A2 (en) * 1985-04-01 1986-10-15 Qiang Hua University A method and an apparatus for modeling bit rate justification
US4730347A (en) * 1985-06-10 1988-03-08 Alcatel Method and apparatus for reducing jitter in a synchronous digital train for the purpose of recovering its bit rate
FR2593337A1 (en) * 1986-01-23 1987-07-24 Berlinet Denis Device for synchronising a binary signal with elimination of jitter
US4825437A (en) * 1986-04-22 1989-04-25 Telecommunications Radioelectriques Et Telephoniques T.R.T. Clock recovery arrangement especially for an information transmission system using the TDMA principle in one transmission direction
EP0266588A1 (en) * 1986-10-20 1988-05-11 Siemens Aktiengesellschaft Phase-locked loop

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598445A (en) * 1994-03-28 1997-01-28 Alcatel N.V. Jitter reduction system in digital demultiplexers
WO1999063670A1 (en) * 1998-06-04 1999-12-09 Adc Telecommunications, Inc. Phase-locked loop with a loop filter
US6064273A (en) * 1998-06-04 2000-05-16 Adc Telecommunications Phase-locked loop having filter with wide and narrow bandwidth modes

Also Published As

Publication number Publication date
SE466474B (en) 1992-02-17
FI932330A (en) 1993-05-21
DE69128632D1 (en) 1998-02-12
DE69128632T2 (en) 1998-05-20
ES2110994T3 (en) 1998-03-01
AU8234391A (en) 1992-02-04
CA2095350A1 (en) 1992-01-11
SE9002408L (en) 1992-01-11
GR3026036T3 (en) 1998-04-30
FI932330A0 (en) 1993-05-21
MX9100088A (en) 1992-02-28
IE80859B1 (en) 1999-04-21
SE9002408D0 (en) 1990-07-10
AU660933B2 (en) 1995-07-13
EP0549591B1 (en) 1998-01-07
DK0549591T3 (en) 1998-09-07
NO931566D0 (en) 1993-04-29
CA2095350C (en) 1999-02-02
EP0549591A1 (en) 1993-07-07
IE912099A1 (en) 1992-01-15
NO931566L (en) 1993-04-29

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