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WO1991009395A1 - Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array - Google Patents

Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array

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Publication number
WO1991009395A1
WO1991009395A1 PCT/DE1990/000855 DE9000855W WO9109395A1 WO 1991009395 A1 WO1991009395 A1 WO 1991009395A1 DE 9000855 W DE9000855 W DE 9000855W WO 9109395 A1 WO9109395 A1 WO 9109395A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
signal
circuit
counter
rate
input
Prior art date
Application number
PCT/DE1990/000855
Other languages
German (de)
French (fr)
Inventor
Werner Wiedemann
Dieter Faber
Uwe Hovestadt
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems
    • H04N3/10Scanning details of television systems by means not exclusively optical-mechanical
    • H04N3/12Scanning details of television systems by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays
    • H04N3/127Scanning details of television systems by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays using liquid crystals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]

Abstract

In a circuit arrangement for controlling a liquid crystal display device with pixels in a grid array, in which video signals (R, G, B) and horizontal and vertical frequency synchronous pulses (H, V) can be supplied to an integrated control circuit, there is a controllable oscillator with a phase comparator circuit and a frequency divider to derive a beat signal. In addition, to the control circuit may be supplied a time control signal (DTMG) which essentially assumes a first logic level during the active lines of the video signal and a second logic level during the horizontal and line frequency synchronous pulses and subsequent predetermined times.

Description

Circuit arrangement for driving a liquid crystal display device having a grid-like arranged picture elements

The invention is based on a circuit arrangement according to the preamble of the main claim.

For reproducing video signals in increasingly liquid crystal display devices are used, in which the picture elements are arranged in grid form. Compared to conventional kinescopes a considerably more complicated control is required in addition to other differences known per se, for supplying each pixel the corresponding Momomentanwert the video signal. There are therefore different

Liquid crystal display devices, hereinafter referred to as LCD displays, integrated control circuits (controllers) become known. A control circuit of this type is available under the designation HD 66840 by Hitachi and is designed to drive TFT displays (thin film transistor displays).

Integrated control circuits for LCD displays are video signals supplied - in the case of a color display, the color value signals R, G, B. In addition, the control circuit requires horizontal rate and vertikalfreguente sync pulses. Both can for example a graphics card (for example EGA) are supplied to a personal computer.

The control circuit also needs a clock signal (hereinafter, called system clock) and a timing signal which defines the start of each line of the image as well as substantially. Object of the present invention is to provide a circuit arrangement for driving a liquid crystal display device in which the system clock and the timing signal are generated such that a constant frame-accurate position of the image is ensured on the LCD display.

The circuit arrangement according to the invention with the characterizing features of the main claim has the advantage that a system clock and a timing signal are derived with little effort.

By the provisions recited in the dependent claims, advantageous refinements and improvements of the main claim invention are possible.

Some developments make it possible in an advantageous manner that a displacement of the image in both the horizontal and in the vertical direction is also exactly possible pixel. An embodiment of the invention is illustrated in the drawing way of several figures and explained in detail in the following description. It shows:

Fig. 1 is a block diagram of the embodiment and

FIG. 2 voltage-time diagrams of some in the

Embodiment shown in FIG. 1 signals occurring.

In a known manner, an LCD display 1 is connected via a plurality of parallel lines 2 with an integrated control circuit 3, which is assigned to the intermediate storage, a static read-write memory 3 '. This is supplied with the color value signals R, G and B via inputs 4, 5,. 6 In addition, the control circuit 3 receives via inputs 7, 8 and horizontal rate synchronizing pulses H vertikalfreguente, V.

In addition, a clock signal CLK and a timing signal DTMG be for operation of the control circuit 3 needs. Both signals are derived using the below-described circuits. For the clock signal CLK, a controllable oscillator 11 is provided, which oscillates at a frequency of 14.3 MHz. The frequency of the clock signal is controlled by a control voltage, which is generated by a phase comparison circuit 12, where the horizontal rate sync pulse H and the output of a frequency divider is supplied. 13 The circuits 11, 12 and 13 illustrate a phase and frequency-locked loop (PLL) which causes an integral ratio n between the frequency of the clock signal CLK and the horizontal frequency. The timing signal DTMG comprises a horizontal rate and a vertical rate component which are respectively generated by means of an 8-bit down counter 14, 15 and a D flip-flop 16, 17th

For the horizontal rate component of the counter 14 is clocked with the clock signal CLK, while H-impulses with the aid of an inverter 9 inverts and an input PE are supplied. An output TC of the down counter 14 is connected to the clock input CP of D flip-flop 16 whose reset input receives RD H pulses. The D-input receives operating voltage (logic 1). The output Q of the D flip-flop 16 is connected to a further input TE of the counter 14 and to an input of a non-Undschaltung 18, which forms a Undschaltung together with another inverter 19th

The counter 15 and the D flip-flop 17 cooperate in the same way, the counter 15 is clocked with the inverted horizontal rate sync pulses H. The PE-input of the counter 15 are supplied to the inverter 10 inverted vertical rate sync pulses V.

Via inputs PO-P7 of counter 14 may be preset to a value Z, to which each of the inputs is connected on the one hand via a resistor 20 with supply voltage (logic 1) and can be acted upon via a switch 21 to ground potential. For clarity in the drawing only two resistors 20 and two switches 21 are shown. Preferably, so-called DIP-switches, of which eight pieces are available in a suitable housing. Similarly, the counter 15 may be preset 23 by means of the resistors 22 and of the switches. As counters 14, 15 are preferably integrated modules of the type 74 HC 103. The generation of suitable timing signal DTMG is explained below with reference to the circuit diagram and the timing charts shown in Fig. 2. In this case, only the signals used to derive the horizontal rate component of the timing signal DTMG are shown. The vertical rate component is generated in a corresponding manner. Line a) is inverted horizontal rate sync pulses H, line b), the output signal TC of the counter having the value 0, and during all other counters has the value 1 when the count 0th Line c) represents the output signal of the D flip-flops sixteenth

By the leading edge of a pulse H, the D flip-flop 16 is reset (Q = 0). The supply of the output signal of the D flip-flops in the input TE of the counter 14 causes it to be released when also the input PE of the value is fed to the first This is with the trailing edge of pulse H (in Fig. 2 highlighted by an arrow) of the case. From then on, the counter 14 counts in synchronism with the clock signal CLK from the count Z down. If the count reaches 0, the signal jumps at the output TC for a period of the clock signal CLK to 0, and clocked with the subsequent positive edge (indicated by arrow in) the D flip-flop 16, thereby the value at the D input, namely 1 takes over. Thereby also the input TE is given the value 1 and disables the counter until the next pulse by the D flip-flop 16 is reset again H.

As already mentioned, the vertical rate component of the timing signal DTMG is generated by means of the counter 15 and the D flip-flops 17th Due to the AND operation of both components a signal, which takes the value 1 during the so-called active lines, so when the video signals contain valid information is produced.

Claims

claims
1. A circuit arrangement for driving a liquid crystal display device with a grid-like arranged picture elements, an integrated control circuit video signals (R, G, B) and horizontal rate and vertical rate sync pulses (H, V) can be fed, characterized in that for deriving a clock signal, a controllable oscillator is provided with a phase comparison circuit and a frequency divider and in that the control circuit further comprises a timing signal (DTMG) can be supplied which is substantially during the active lines of the video signals a first logic level, and during the horizontal rate and line rate synchronizing pulses and subsequent predetermined time intervals a second logic level accepts.
2. A circuit arrangement as claimed in claim 1, characterized in that the predetermined time intervals are adjustable.
3. A circuit arrangement according to claim 1, characterized in that for the derivation of the timing signal, a first counter with said clock signal and to the horizontal rate sync pulse can be acted upon and the output side is connected to a first flip-flop, that a second counter with the horizontal rate sync pulse and the vertical rate is acted upon synchronizing pulse and has its output connected to a second flip-flop and in that output signals of both flip-flops are connected to the timing signal.
4. A circuit arrangement according to claim 3, characterized in that the clock signal to the clock input of the first counter (14) and the horizontal-sync pulse to a control input (PE) of the first counter (14) can be fed, that an output (TC) of the first counter (14 ) (to the clock input CP) of the first D-flip-flop (16) connected is, which is reset by the horizontal rate sync pulse, and that the output of the first D-flip-flop (16) having a further control input (TE) of the first counter (14) is connected.
5. A circuit arrangement according to claim 3, characterized in that the horizontal rate sync pulse to the clock input of the second counter (15) and the vertical rate sync pulse to a control input (PE) of the second counter (15) can be fed, that an output (TC) of the second counter ( 15) (to the clock input CP) of the second D-flip-flop (17) is connected, which is reset by the vertical rate sync pulse, and that the output of the second D-flip-flop (17) having a further control input (TE) of the second counter (15) is connected.
6. The circuit arrangement according to claim 3, characterized in that the number of pulses at the clock input of each counter is output to an output adjustable from a start of the counting operation.
7. The circuit arrangement according to claim 3, characterized in that the counters (14, 16) are presettable down counter.
PCT/DE1990/000855 1989-12-09 1990-11-10 Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array WO1991009395A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DEP3940750.0 1989-12-09
DE19893940750 DE3940750A1 (en) 1989-12-09 1989-12-09 Circuit arrangement for driving a liquid crystal display device having picture elements arranged rasterfoermig

Publications (1)

Publication Number Publication Date
WO1991009395A1 true true WO1991009395A1 (en) 1991-06-27

Family

ID=6395147

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1990/000855 WO1991009395A1 (en) 1989-12-09 1990-11-10 Circuit arrangement for controlling a liquid crystal display device with pixels in a grid array

Country Status (2)

Country Link
DE (1) DE3940750A1 (en)
WO (1) WO1991009395A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854615A (en) * 1996-10-03 1998-12-29 Micron Display Technology, Inc. Matrix addressable display with delay locked loop controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4275421A (en) * 1979-02-26 1981-06-23 The United States Of America As Represented By The Secretary Of The Navy LCD controller
JPS60158780A (en) * 1984-01-27 1985-08-20 Sony Corp Display

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4275421A (en) * 1979-02-26 1981-06-23 The United States Of America As Represented By The Secretary Of The Navy LCD controller
JPS60158780A (en) * 1984-01-27 1985-08-20 Sony Corp Display

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, Band 9, Nr., 328 (E-369), 24. Dezember 1985; & JP-A-60158780 (SONY KK) 20. August 1985 *
Society for Information Display - International Symposium, Digest of Technical Papers, Band XVIII, Mai 1987, New Orleans, Louisiana, US, Palisades Institute for Research Services, Inc., (New York, US), A. Kompolt: "Video to LCD interface (VLI) IC converts video signals into signals suitable for LCDs", Seiten 416-418 *

Also Published As

Publication number Publication date Type
DE3940750A1 (en) 1991-06-13 application

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