WO1991008565A1 - Video display - Google Patents

Video display Download PDF

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Publication number
WO1991008565A1
WO1991008565A1 PCT/GB1990/001834 GB9001834W WO9108565A1 WO 1991008565 A1 WO1991008565 A1 WO 1991008565A1 GB 9001834 W GB9001834 W GB 9001834W WO 9108565 A1 WO9108565 A1 WO 9108565A1
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WO
WIPO (PCT)
Prior art keywords
video
display
display device
unit
array
Prior art date
Application number
PCT/GB1990/001834
Other languages
French (fr)
Inventor
Sean Hillen
Original Assignee
Sean Hillen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB898926647A priority Critical patent/GB8926647D0/en
Priority to GB8926647.2 priority
Application filed by Sean Hillen filed Critical Sean Hillen
Publication of WO1991008565A1 publication Critical patent/WO1991008565A1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423Digital output to display device; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1446Digital output to display device; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026Video wall, i.e. stackable semiconductor matrix display modules
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers

Abstract

A video display unit consisting of a number of display units or modules arranged in a 2-D array which is fed with video signals from an interface unit connected to a convenient point on the array. Each unit preferably comprises a tile-shaped LCD module, enabling the display to be mounted on the wall, and includes its own control circuit on its rear surfaces. Since each unit takes part in decoding the video signals, an extremely versatile display can be realised, in which the overall size and/or aspect ratio may be changed by simply adding units to, or removing units from, the array. To enable interconnection, each unit has a recess lined with contacts at each edge, in a manner similar to a PCB edge connector, and contacts at the adjacent edges of adjacent units are connected by a coupling member. This interconnection arrangement removes the need for complex connections by means of a backplane. Each control circuit adapts its decoding system according to the size of the array and the position of the respective display unit within it, so that video signals which would otherwise be incompatible with the overall pixel array dimension of the display can be successfully decoded.

Description

Video Display

The present invention relates to video display devices for displaying a visual representation in response to electrical signals and in particular to flat screen type video display devices.

It is a common feature of display devices, whether flat screen types or cathode ray tube (CRT) type devices, to divide the display area up into a number of lines or strips and to further divide each line into a number of elements called pixels, each pixel capable of exhibiting various brightness and, where applicable, colour in response to varying electrical signals. This pixel array, in addition to displaying video images, is also of such a form that textual information may be displayed on such devices by forming and displaying characters in rectangular blocks of pixels, for example 6 pixels wide by 10 pixels (or lines) high. The pixels are normally rectangular or round.

There are technical difficulties in producing very large video displays because the predetermined display technology-raster-scan CRTs - is unsuitable for displays greater than 1m in size as such devices would be extremely bulky. In the alternative display technology - flat panel displays -it is difficult to manufacture, and produce the necessary connections for, devices with pixel arrays having the order of 0.4 million pixels or more.

In video display devices which display images conveyed by broadcast signals, such as television system, both the dimensions of the video display (number of lines and number of pixels per line) and the characteristics of the broadcast signals are standardised in order that all television receivers can satisfactorily receive the signals and display the corresponding visual images. Similar considerations apply to devices which reproduce video images from video signals stored on the various storage media which are available. The physical dimensions of existing video display are therefore limited to those of the screens of television receivers and similar devices (whether CRT, liquid crystal display (LCD)-type, or other) which are available, an in general, existing large screen displays tend to be very cumbersome and expensive.

Further, if a display to which a video signal is applied has pixel array dimensions which are less than or greater than that of the image corresponding to to the video signals, the images defined by the video signals will not be correctly displayed.

There is therefore a need for a video display device which is relatively simple and inexpensive to manufacture in a lightweight, convenient form, whose pixel array dimensions (and therefore physical size and aspect ratio) are easily variable to any arbitary specification, and which includes a decoding system adaptable to variations in size, so as to be capable of displaying a video image fitting a physical space in response to video signals which are incompatible (i.e. the pixel array dimensions of the video image corresponding to the video signals are greater than or less than those of the video display device) as well as compatible video signals. The present invention provides a video display device for display a video representation in response to electrical video signals, comprising: a plurality of display units, each display unit having a pre-determined number of pixels disposed in a surface thereof; an interface for coupling the electrical video signals to the plurality of display units; one or more control units, coupled to the interface unit and to each of the plurality of display units, for receiving electrical video signals from the interface unit and in response thereto, applying selected electrical video signals to the pixels of the plurality of display units.

Preferably the display units are in the shape of square tiles, but may be rectangular or any other suitable shape, enabling them to be arranged edge to edge in a two-dimensional array on any suitable flat surface, such as the wall of a building. Preferably the array of pixels on the display surface of each display unit has dimensions between 20 pixels and 50 pixels (i.e. minimum dimensions of 20 x 20 pixels; maximum dimensions of 50 x 50 pixels) or any other dimensions which are suitable for large-scale manufacture. The pixels may be of the LCD - Light Emitting Diode (LED) -' type or other suitable pixel type, and may be monochrome or colour. Alternatively, the display units may comprise CRT-type devices such as television receivers or VDU monitors and may have any screen dimensions of those which are available.

The number of display units in a row of an array, and the number of rows, may be varied in order to produce a display with any overall size or aspect ratio that may be required.

Preferably, the interface unit is coupled to one the display units which for convenience may be at one end of the lowest row in the array, but may be coupled to any of the display units and may include means by which a user can exert control over the display device, for example by means of switches, dials, visual indicators and the like. Such control may include switching to the first mode in which the video image is displayed pixel-for-pixel and only a relatively small section of the complete video frame is to be displayed or altered with time, or to the second mode in which a video from is to be generated from incompatible electrical video signals; and control over the aspect ratio of the displayed video frame (in which case some display units at the perimeter of the video frame may be unused). The interface unit may receive the electrical video signals directly from, for example, a charged coupled device (CCD) camera, from a receiver of broadcast or cable television signals, or from a graphics output port of a computer system. The interface unit also includes a bias control which, on operation by a user, sets a number of bias terms (signals) which affects the behavior of the control unit(s). The bias terms may be such as to give the control unit(s) the impression that the array display units has larger dimensions than it actually has: control units sense that the overall pixel array dimensions are larger than they really are and the resulting effect is zooming or enlargement of part of the video image. Conversely, if the bias terms indicate that the pixel array dimensions are smaller than they actually are, the result is image reduction. The bias terms may also be use to shift the video image relative to the video display screen, in the horizontal or vertical directions.

The control unit(s) are preferably configured to read and decode the electrical video signals in an intelligent manner and apply electrical signals to the pixels in accordance with the mode selected by the user. For example, in the first mode the video frame may be displayed pixel-for-pixel (i.e. each pixel of the video frame corresponding to the electrical video signals being displayed by one pixel of the video display). In the second mode the control unit(s) may sample the electrical video signals, in determining the electrical signals which are to be applied to the pixels of each display unit. The control unit(s) detects voltage signals received from the interference unit and determines therefrom the number of display units in two orthogonal (e.g. horizontal and vertical) directions. In this way, for of each display unit, the control unit(s) determines the dimensions of the array of display units and its position therein. With this information each control unit(s) selects which electrical video signals to use (corresponding to selected lines of the complete video frame) and determines when to start and stop selecting electrical video signals in the horizontal direction (i.e along a line of the video frame). This selection or sampling feature of the control unit(ε) enables the video display device having number of display units depending on how many are available to the user, to display the complete video frame, with maximum dimensions of the array of display units limited only by the upper limit of the display units which can be powered by the power supply being used. Since each display unit preferably has its own control unit, a single display unit is capable of acting as a stand-alone display and displaying the complete video frame, although the resolution may be relatively low. A more desirable display effect and higher resolution may be obtained when the number of display units used in the display device is relatively large. A user may improve the image reproduction by adding more display units to an existing array by attaching the units by means of coupling members.

In the case of tile-shaped LCD or LED display units, multi-contact connectors are provided at each edge of a display unit. Each edge is preferably provided with a recess having two elongate walls to which a plurality of electrical contacts are attached in parallel rows, in a similar manner to those of an edge connector for a printed circuit board (PCB). In the array of display units, the contacts in the recesses of adjacent edges are electrically connected by means of conductive coupling members which are partially inserted into each of the recesses. This arrangement facilitates interconnection of the display units in the plane of the display and avoids the problems with existing modular flat display devices of the need for a backplane.

Preferably each control unit comprises a control circuit which is mounted on each display unit, on the surface (hereinafter referred to as the reverse surface) opposite the display surface, and makes electrical connection with the contacts at the edges of the display unit by means of conductive tracks (such as copper strips) on the surface of the display unit and plated bores extending between the surface and the edge contacts. The control circuits may each include one or more ROM - type memories for storing data (used for sampling and processing the electrical video signals) when the display device is switched off.

As a result of the interconnections between adjacent display units and between the interface unit and one of the display units and the coupling between the control circuit and the contacts on each edge of the display unit, all the electrical video signals pass through the control circuit of each display unit. For each display unit the control circuit detects voltages appearing at contacts on four edges of the display unit. The control unit determines the voltage drop in the horizontal and vertical directions from a value set by the interface unit, and divides each of these two values by the voltage drop associated with each display unit to determine the horizontal and vertical dimensions (No of display units) of the array of display units and the position of the display unit with the array. With this size and position information each control circuit can modify the manner in which it decodes and processes the electrical video signals so that images can be properly displayed even" when the pixel array format of the display is not compatible with that of the incoming electrical video signal.

An advantage of the use of a completely controllable video signal decoding signal in the present invention is that a versatile text and graphics information display system may be provided, which can be supplied by any source of a composite video signal (for example, almost any computer). This may be done, for example, by loading and displaying every line of the video frame, starting from the left hand side of the top line and using a horizontal pixel "time-slot" equal to 63.2/640 s (corresponding to : time line in s divided by a notional 640 pixels per line), so that for instance, text from the simplest standard 10x7 pixel fonts may be displayed.

In the case where the display unit comprises CRT displays, the control units may comprise a control circuit associated with each CRT display, where all the control circuits are interconnected and operate in the same manner as described above with reference to the LCD file display units.

The conductive coupling members preferably have a cross-section in the shape of a capital H and are preferably made of a resilient material, enabling them to be fitted into the recess in the edges of display units or in the interface unit. The conductive coupling members and may therefore provide mechanical attachment and restraint between adjacent display units and between a display unit and the interface unit, as well as electrical connection therebetween.

A specific embodiment of the invention will now be. described by way of example with reference to the accompanying drawings, in which:

Figure 1 illustrates a flat screen type video display which is known from the prior art;

Figure 2 shows a perspective view of a part of the video display device according to a first embodiment of the invention, in a partially assembled condition;

Figure 3 is a view of the non-display surface or reverse surface of one of the display units shown in Figure 2;

Figure 4 shows a frontal view of the fully assembled display device according to an embodiment of ' the invention;

Figure 5 is a flow chart showing the operation of the control unit according to an embodiment of the present invention;

Figure 6 shows a lateral cross-sectional view of part of one of the display units in Fig. 4 in a second embodiment of the present invention;

Figure 7(a) is a schematic diagram of the connecters at the four edges of the display unit of Fig.

SUBSTITUTE SHEET 6 ;

Figure 7(b) is a block diagram of a preliminary stage of the control circuit of a display unit in the second embodiment;

Figure 7(c) is a block diagram of the main storage of the control circuit in the second embodiment; and

Figure 7(d) is a schematic diagram of the synchronisation technique employed in the second embodiment.

Referring to Figure 1 , a frontal view of a flat scree type video display 1 is shown, in which the display surface 2 is divided up into mn rectangular pixels 3. The display therefore has m pixel lines 4 and n pixel columns 5. Also shown is a single character block 6 which is 6 pixels wide by 10 pixels high and has a character 7 (capital B) displayed by the first seven lines and the first five columns of the character block 6.

In figure 2 part of a display device according to the invention is shown: the display device as a whole includes a large number of display units 10, only the two display units 10A, 10B immediately adjacent the interface unit 11 of the display device are shown.

Each display unit 10 in Figure 2 is in the shape of a square tile and has a display surface formed by 400 liquid crystal pixels in each 20 x 20 pixel array (only a small number of pixels are shown). Each of the four edges of the display unit 10 has a recess in the form of an elongated trench, the two opposing elongated walls of the recess having mounted thereon a plurality of electrical contacts made of thin metal strips which are electrically isolated from each other but which are each electrically connected (e.g. by soldering) to

SUBSTITUTE SHEET - 1 0

to metal-plate bores (not shown) which extend from the walls of the recess to the reverse surface (not shown) of the display unit 10, opposite the display surface.

The interface unit 11 includes a number of dials and indicators to facilitate control of the video display device by a user. The interface unit 11 receives electrical video signals and electrical power via a multi-conductor cable. The interface unit 11 has one relatively elongated dimension and one side is provided with a recess which is of the same form as the recesses of the display units 10 and is provided with a corresponding number of electrical contacts on its elongated walls.

Five conductive coupling members, are present in the part of the video display shown in Fig. 2 (only three - 123, 124, 125 are visable in. Figure 2). Each conductive coupling member comprises an elongate resilient member having H-shaped cross-section, with a number of thin metal strips fitted over the two outer surface of the resilient member and extending in a direction perpendicular to the direction of elongation of the resilient member. The metal strips are spaced apart (so as to be electrically isolated from each other) in the same spatial relationship as the contacts in the recesses of the display unit 10 and interface unit 11, respectively.

The video display device is assembled by inserting coupling member into the recess of the interface unit 11 until the leading edges of the coupling member abuts the the base of the recess (not shown) at which point just over half of the crosssectio of the coupling member protrudes from the surface. The coupling member has an elongate dimension slightly less than that of the recesses but has a width prior to

SUBSTITUTE SHEET insertion into the recess which is marginally greater than the separation of the rows of contacts on the opposing sides of the recess so that after' insertion of .the coupling member into the recess it is retained therein by strain relief, with each metal strip in electrical contact with one contact of the interface unit. The display unit lOA is then attached to the interface unit 11 by sliding the display unit lOA relative to the interface unit 11 , whereupon the protruding part of the coupling member slides into the recess in the leading edge of the display unit lOA until the coupling member abuts the base of the recess.

In this way each electrical contact in the recess of display unit lOA is electrically connected to a corresponding electrical contact in the recess of the interface unit.

Another coupling member is then inserted into the recess in the edge of display unit lOA opposite the edge to which the interface unit 11 is attached, in the same way as with the first coupling member. The display unit 10B is then fitted onto the coupling member in the same way as that display unit lOA was fitted onto coupling member, thereby joining display units lOA and 10B and electrically connecting corresponding contacts in the recesses of each of the display units.

Figure 2 shows part of the video display device when assembled, with the interface unit 11 and display units lOA, 10B mechanically and electrically joined.

The process of attaching more display units in the manner described above is repeated to build up an array of display units of the required size, with further attachments in the horizontal direction

SUBSTITUTE SHEET beginning with the attachment of couping members 123, and in the vertical direction beginning with the attachment of coupling members 124, 125.

Figure 3 illustrates the reverse surface or non-display surface of one of the display units 10 of Figure 2. The control circuit 13 is surf ce-mounted on the reverse surface 108 and has a number of input/output terminals 14 through which it receives and transmits electrical video signals and electrical power via tracks 15 which are made of thin copper strips and which are etched on the surface 108 of the display unit 10. Each of the tracks 15 is also connected to a metal-plated bore 16. A strip of bores 16 is arranged adjacent each edge 103.of the display unit 10, and each bore extends from the surface 108 to the wall 105 of the recess 104 where it connects with a corresponding contact 106.

The material below the surface 108 comprises an insulating layer of plastic material between 1 and 2 mm in thickness. The control circuit has 40 pixel driver outputs 17, each of which is connected to a plated bore 18 which extends from the surface 108 through to the lower surface of the insulating layer where it is connected to one end of one of a number of tracks (not shown) made of copper strips. The lower layer of tracks, the insulating layer, the plated bores 18 and the surface layer tracks 15 are formed using multi-layer printed circuit board (PCB) manufacturing techniques. The end of each lower layer track remote from the plated bore 18 is connected either to a pixel line conductor (delivering brightness and colour signals to the switching element associated with each pixel in each line) or a pixel column conductor (delivering scanning pulse signals to the switching element associated with each pixel in a column such that each of the 20 pixel line conductors and each of the 20 pixel column conductors is connected to one of the pixel driver outputs 17.

The control circuit 13 of each display unit 10 receives the electrical video signals and electrical power from the interface unit 11 via the above-described connections between the contacts 106 at one edge 103 and the corresponding set of input/output terminals 14 and then conveys the electrical video signals and electrical power to the contacts 106 on the other three edges 103. of the display unit 10 via the three corresponding sets of input output terminals. The control unit also samples the electrical video signals and electrical power levels at its input/output terminals 14 and selects, in response to the sampled signals, the electrical video signals which are to be applied to the pixels. The control circuit then applies the electrical video signals to the pixel line conductors and scanning pulse signals to the pixel column conductors in the conventional manner in order to produce the video representation of the electrical video signals.

Figure 4 shows the fully assembled video display 20 which comprises a 10 x 10 array of display units 10 connected to an interface unit 11. The video display 20 displays a video representation depending on the mode selected by the user on the interface unit 11.

In Figure 4, x and y denote the horizontal and vertical directions, respectively. The array of tiles in the video display 20. is Nx tiles wide, by y tiles high, and given display unit 10 is at a position TX f Ty/ where Tx lies in the range 1 to Nx, and Ty in the range 1 to Ny. For each display unit 10, Dx and Dy denote the dimensions of the display unit in pixels and for a square display unit Dx = Dy = D. The position of a pixel in the display unit 10 is given by Px, Py, where Px lies in the range 1 to Dx and Py in the range 1 to Dy.

Figure 5 illustrates a flow chart demonstrating the operations of the control unit(s) in decoding the video signals.

The additional parameters appearing in the flow chart are defined as follows.

H = height of the video frame (in lines) defined by the video signals (usually 312 or 625).

A = aspect ratio of the video frame.

W = width of the video frame in pixels (=HA).

S1X, S2x, S1y, S2y = horizontal and vertical bias terms set by the interface unit 11. tx - duration (in us) of one line of the video frame defined by the video signals (usually 64 us for 625 line system). n = number of lines in a group which is used for sampling and decoding the video signal in the second mode.

1 = line number of the video frame, where 1 lies in the range 1 to H.

1W = the number of lines during which the control unit waits before beginning to sample the video signals. c = column (or pixel) number in a line of the video frame, where c lies in the range 1 to W. cw = the numbers of columns (or pixels) which the control unit ignores in each line before beginning to sample the video signals. t = time elapsed after line sychronisation pulse. tw = total elapsed time corresponding to cw.

Referring to Fig. 6, a second embodiment is illustrated in which each display unit or "file" 10 in the array 20 of Fig. 4 comprises an array of LEDs 22 mounted on a board 24. The LEDs may be in available colour appropriate to the file application. In the embodiment described with reference to Figures 6 and 7 the array of LEDs on each tile has dimensions 4 x 4, and the array 20 of tiles is such that 1 < Nx < 4 and 1 < Ny < 4 (see Fig. 4} .

The control circuit 13 is constructed on two PCBs 26 mounted parallel to the board 24 and on the side opposite the LEDs 22. The boards 24 and 26 are mounted in a housing 28 by screws or adhesive in a suitable manner. Plugs and sockets (not shown) at each edge of each tile (which may be edge connectors of the conventional type which attach to the housing 28 so as to produce the minimum spacing between adjacent tiles) provide) connections between the control circuits 13 of adjacent tiles. Information about the array and critical tuning information, as well as video signals, pass from one file to the next through these connections.

The array of tiles is arranged such that every tile in the array is instructed about the overall size of the array and whether it has to supply master timing information.

In the second embodiment, every LED on a tile must contribute the same light output to the final display output, and this is especially important at the boundaries between tiles. For this reason, the output cone 30 form each LED projects onto a translucent screen 32 mounted at such a distance in front of the LEDs that the projections of the cones 30 onto the screen produces closely packed but distinct spots or pixels, without any appreciable overlap or inter-pixel black areas.

Referring to Figure 7, there is shown in Fig. 7(a) a schematic diagram, of the connections provided to and from the connectors at each of the four edges of the tile. Only four signal-carrying contact are shown at each edge, for clarity but any number of contacts may be provided on each tile, depending on its size, or the size of the intended array 20.

For a stable display without boundaries appearing between tiles, one tile (hereinafter referred to as the "marker tile") provides all the video input and output timing or synchronisation signals. The interface unit 11 may be connected to this file.

Each tile must receive the master timing signal and information regarding the total number of tiles in the array in the horizontal and vertical directions. With the exception of the master tile, each tile must disable its own generation of such signals, and to do this each tile must have information about its own position in the array.

To determine the aforementioned information, codes are passed through the array in each orthogonel direction. In the present embodiment of a 4 x 4 array, a two bit horizontal position code HSC1 , HSCO and a two bit vertical position code VSC1 , VSCO are sent in their respective directions to each tile of the array (see Fig. 1 (a)). (In the description referring to Fig. 7, the references to "codes" should be understood as references to signals passing between the control circuits via the conductors of the connectors provided at each edge of the tile, and references to codes having the values 0 and 1 correspond to the aforementioned signals being at LOW voltage level and HIGH voltage level in the system. )

The horizontal (HSC1 , HSCO) and vertical (VSC1 , VSCO) position code signals are pulled up at inputs. The bottom right hand tile in the array is thus coded (1 , 1.). (It will be appreciated that the use of two-bit position codes enables 4 x array to be addressed and that, in general, for position codes of r bits - and therefore position code connectors at each edge of each tile - a 2r x 2r array of tiles may be addressed, since binary coding signals are used.Using the term "input" to mean connectors (or pins) J1 and J2 at the bottom right of tile, and "output" to mean connectors (or pins) S1 and S2 to left of tile, two other codes termed HO and VO in figure 7 are routed through the array. ' HO and VO are horizontal and vertical enable codes, respectively. These signals are pulled up at their outputs. The corresponding tile input pins differ. The first is connected to ground and the second to the corresponding output pin. Thus if there is a tile to the left of the current tile, the local HO" signal is grounded (LOW level). Likewise, if there is a tile above the current tile, the local VO is grounded.

The HO signal is coupled to each tile in a column and, likewise, VO is commanded horizontally. Thus HO is a '1' (HIGH level) on the extreme left hand column of the array, and VO is '1' in the top row of tiles. As a result of this coding, only one tile (the master tile) at the top left hand corner of the array will be enabled to drive out the video input horizontal and vertical synchronization codes (signals) HSC and VSC, which are described in further below. The horizontal and vertical position codes are routed in each direction through the array; the codes HSC1 , HSCO through each row independently; the codes VSC1 and VSCO through each column independently.

The inputs to each tile VSC1 , VSCO and

Figure imgf000019_0001
HSCO go through an adder which subtracts 1 from the code and outputs horizontal position codes to the next tile horizontally as HS1C and HSOC and vertical position codes to the next tile vertically as VS1C and VSOC.

The codes for a (4x4) array will thus appear s (VSC1 , VSCO; HSC1 , HSCO):

0,0:0,0 0,0:0,1 0,0:1 ,0 0,0:1 ,10,1 :0,0

0,1 :0,1 0,1 :1 ,0 0,1 :1 ,1

1 ,0:0,0 1,0:0,1 1,0:1,0 1 ,0:1 ,1

1 ,1 :0,0 1 ,1 :0,1 1 ,1 :1 ,0 1 ,1 :1 ,1

The codes for the number of tiles in a row is HC1 , HCO (here 1,1) and in a column VC1 , VCO (here 1,1). The maximum values of HSC1 , HSCO and VSC1 , VSCO are enabled by HO and V0, respectively. The former enables the top row, which drives HC1 , HCO down through the columns. The latter enables the left hand column which drives across through the rows. Each column is independent.

Referring to Fig. 7(b), the composite video signal is routed to all tiles where it is buffered in a buffer 32 and applied to a separator 34 to recover the synchronization pulse signals HSC, VSC. The composite sync output signal is applied to a monostable pulse generator which generates 4us pulse signal HSC. The video equalizing pulses double the frequency at the end of the frame but this does not affect the tile timing system. The vertical synchronising output signal VSC is input to a monostable whose output lasts until all equalizing pulses are over, and is then synchronised with a bistable clocked with HSC. Odd and even fields are treated alike, though if this causes jitter, only odd fields may be used.

Referring to Figure 7(c), the processing of video signals involves two independent continuous processes. The first process takes video and video timing or sync signals from an incoming composite video signal, samples and quantizes the signal, and accumulates the resulting video data values for each point in the whole video tile display, that is for all tiles in the system. The second process takes video data from the store 42 for the current tile, normalities it and feeds it to the LED array 54.

The composite video is applied to a high speed analog to digital converter (ADC) 36 which is commanded to convert just before the output is needed.

The fundamental timing is taken from an 16MHz oscillator 56 with a low impedance output and terminated, resistively see Fig. 7(d). The number of horizontal and vertical picture elements is given by the tile width multiplied by the number of tiles. If the same area is to be covered by a one tile array as by a four tile array, the picture element time or pixel time slot must be divided by the number of tiles used.

To allow both this and the variation in active picture area two variations are included. The simplest is a blanking counter which is loaded by VSC or HSC. This counts up the picture elements until a carry is generated which inhibits further counting. The next" two counter chips therefore continue to count picture elements as soon as this stage is reached.

The other variation is to make an approximate compensation for the number of tiles by multiplying a basic period by 4, 2, 1 and 1 for tile numbers 1, 2, 3 and 4 and correcting the inaccuracy for three tiles and adjusting the overall picture width a counter and the data selectors and switches feeding it.

The picture element used to trigger the flash converter and access the store 42 is that generated before the division by the number of tiles. The pixel time slot is' typically a 1us period. After the horizontal blanking period, each of these sub-picture elements causes a counter to cycle. This produces 3 pulses which are, in order, TRG-, RD-, WR-. TRG- and RD- form a double pulse generating an accurate analog to digital conversation from the ADC 36.

This 6 bit quantised data is applied to one input of a 16 bit adder 38. The other input is connected to the store 42. The output of the store 42 is inhibited by two sequential bistables. The first is set by the disappearance of the carry signal to the vertical picture element counter 62 (see Fig. 7(d), that is at the beginning of each new picture element row. The first bistable is cleared by HSC at the end of the first video line of the new picture element row.

The second bistable is fed by the first. If the first is set, the second is set by the disappearance of the carry signal to the horizontal picture element counter (60), that is at the beginning of each new picture element. The second bistable is cleared by WR-. Since the outputs of the store 42 have pull-down resistors, the result is that the first contribution to each picture element is written store 42 without the store contents being first added to it.

The output of the adder 38 is latched through a latch 40 by the trailing edge of the store 42's read signal RD-. The store output to the next stage remains valid until the signal WR- is generated, which writes the output of the latches 46 back to the store 42. The . maximum number of contributions added to store depends on the number of tiles, and number of elements per tile.. If there is only 1 tile of 10 x 10 LED elements this number will be 100.

The output of the latch 46 applies on addresses to read only memory 48, whose output is applied to a digital-to-analog converter (DAC) 50. The output from the DAC 50 is fed to the LED driver circuit 52 which is coupled to the LED display matrix 54 of the tile. The picture element counters 60, 62, which makes up the store address, count from the values of VC1 , VCO and HC1 , HCO up to 1,1 and 1,1 and hence 0.0. When this overflow occurs, the top bit of the counters are used to disable the store chip cable. Alternatively it may be used to disable the TRG- generation.

Claims

Claims :
1. A video display device for displaying a video representation corresponding to electrical video signals, comprising; one or more display units arranged in a two dimensional array, each display unit having a pre-determined number of pixels disposed in a substantially flat surface layer thereof; an interface for coupling the electrical video signals to the plurality of display units; one or more conductive couplings for providing electrical connection between the interface unit and the array, and between adjacent display units in the array; one or more control units, coupled to the interface unit and to the display unit(s), for receiving electrical video signals from the interface unit and, in response thereto, applying selected electrical video signals to the pixels of the display unit(s).
2. A video display device according to claim 1 , wherein the or each control unit comprises a control circuit associated with a respective display unit.
3. A video display device according to claim 2, wherein the or each control circuit includes means for determining the dimensions of the array of display units.
4. A video display" device according to claim 2 or 3, wherein the or each control circuit includes means for determining the horizontal and vertical position of its respective display unit in the array of display units.
5. A video display device according to claim 4, wherein the or each control circuit includes means for generating said selected electrical video signals in dependence upon said horizontal and vertical position.
6. A video display device according to claim 4 or 5; wherein the, or each control circuit includes means for sampling the electrical video signal for a period corresponding to one or more consecutive lines of the video representation and for generating the selected electrical video signals therefrom.
7. A video display device according to claim 4, 5 or 6, wherein the or each control circuit includes means for sampling the electrical video signal for a period corresponding to one line of the video representation, at intervals corresponding to a predetermined number of lines of the video representation, and generating the selected electrical video signals therefrom.
8. A video display device according to any of the preceding claims, wherein each display unit comprises a rectangular tile-shaped unit.
9. A video display device according to claim 8, wherein each display unit includes an elongate recess provided in each edge thereof, a row of contacts at a pre-determined spacing being provided on the two opposing elongate walls thereof.
10. A video display device according to claim 9, wherein each conductive coupling comprises an elongate insulating member having two major elongate surfaces, a row of conductors at said predetermined spacing being provide on each major surface, each conductive coupling being adapted to slot into the recesses in the edges of adjacent display units in the array.
11. A video display device according to claim 10, wherein each elongate insulating member is formed of a resilient material so as to provide strain relief mechanical coupling between adjacent display units when a coupling is slotted into the adjacent recesses thereof.
12. A video display device according to claim 10 or 11 , wherein each elongate insulating member has an H- shaped cross-section.
13. A video display device according to any of claims 2 to 12, wherein the or each circuit is provided on the rear surface of a respect display unit.
14. A video display device according to any of claims 9 to 13, wherein the or each control circuit is coupled to one or more of the contacts in the recesses of a respective display unit.
15. A video display device according to any of the preceding -claims, wherein the or each display unit comprised a liquid crystal display (LCD) module.
16. A video display device according to any one of claims 1 to 7, wherein the or each display unit comprises a CRT-type display device.
17. A video display device according to claim 16 , wherein the control unit comprises a single control circuit coupled to each of the display units by a multi- conductor cable.
18. A video display device substantially as hereinbefore described with reference to Figures 1 to 5 of the accompanying drawings.
PCT/GB1990/001834 1989-11-24 1990-11-26 Video display WO1991008565A1 (en)

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FR2797341A1 (en) * 1999-08-04 2001-02-09 Rangheard Modular luminous notice board e.g. for road signals has matrix controlled by microprocessor and instruction emitters and receivers
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FR2797341A1 (en) * 1999-08-04 2001-02-09 Rangheard Modular luminous notice board e.g. for road signals has matrix controlled by microprocessor and instruction emitters and receivers
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WO2014070684A1 (en) 2012-11-01 2014-05-08 Lellan, Inc Seamless illuminated modular panel
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US9684483B2 (en) 2012-11-01 2017-06-20 Lellan, Inc. Seamless illuminated panel
CN105850229A (en) * 2013-09-20 2016-08-10 艾克斯-马赛大学 Programmable module for a modular installation of signal transmitters and method of driving the installation

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GB9025631D0 (en) 1991-01-09
GB8926647D0 (en) 1990-01-17

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