WO1989002643A1

WO1989002643A1 - Write precompensation techniques for magnetic recording

Info

Publication number: WO1989002643A1
Application number: PCT/US1988/003233
Authority: WO
Inventors: James L. Chiao
Original assignee: Unisys Corporation
Priority date: 1987-09-21
Filing date: 1988-09-21
Publication date: 1989-03-23

Abstract

Disclosed are disk drive recording techniques wherein a write data pattern is processed for ''write precompensation'' e.g., shifting bits time-wise relative to prescribed write clock pulses so that they may be read-back with less peak shift within a data window.

Description

TITLE

WRITE PRECOMPENSATION TECHNIQUES FOR MAGNETIC RECORDING

This invention relates to magnetic recording and more particularly to write precompensation techniques therefor.

Background features;

Workers in the art of asking and using high speed impact disk drive equipment are of the need for "precompensation" for write data bits to reduce the peak shift in read back data. Some problems are encountered with conventional methods. For instance, with higher density disk drives, the need to reduce "peak shift" has also been tightened. The limitation of fixed precompensation levels does not allow for the optimizing precompensation for all critical data patterns or for peak-shift variations with different heads.

My invention addresses such problems, in a novel precompensation technique which improves write precompensation so as to reduce the effect of peak shift in digital magnetic recording channels using a "run length limited" (RLL) code. My technique includes such features as the following: _A> I detect all critical data patterns which cause significant peak shifts. The data patterns include "worst case" peak shift patterns which have Tmin separation(s) , and data patterns which have Tmin+1 separation(s) • For "run length limited" codes, T in is minimum distance between two adjacent transitions. B. Instead of using hardwired logic to select the precompensation levels, my new methods store the precompensation. data on a PROM which allows for changing of precompensation data without changing hardwired logic. In addition, 16 equally spaced levels are available to provide a "best match" for precompensation. _ Four sets of precompensation data P-d can be selected which are chosen to match the spread of peak shift distribution for various heads. Each head is pre¬ tested to determine its peak shift characteristic. Then ONE of the four sets of precompensation data is used to

"tag" the head (i.e., with P-d matching that head's shift characteristic). The information which matches heads to precompensation data sets can be stored in a separate memory device.

Under normal operating condition, the proper precompensation data st can be selected according to the information stored in the memory device. ^■Q I prefer using 4 precompensation zones to best compensate for the change in peak shift as a function of disk radius (i.e., radial track position). _E. My technique can be implemented very easily and simply: e.g., in a circuit consisting merely of a shift register, a data latch, a PROM, a programmable delay module, and related control logic. "Control Method" (FIG. 1): FIG. 1 illustrates an arrangement PC adapted for write precompensation in a disk drive recording arrangement adapted to manipulate a write data pattern and process it, making the bits better "time-positioned" for recording; e.g., by shifting bits early or late, i.e., so that when they are read-back, the bits will be "on time" within the data windows.

In FIG. 1, write data bits "dd" and write clock signals wc are applied to a shift register stage SR, which applies its output signals in paralleled to a Data Pattern Logic stage DPL which processes the pattern of bits and applies it to a multiplexer unit MUX adapted to delay selected bits and output them by selecting one of the clock-pulses cp, outputting them serially as "new-clock-pulses" nc to a flipflop stage f/f where they are used to clock-out delayed write-bits "ddd, " precompensated, as output bits "p-dd." The MUX - A -

matches each input-bit-signal from DPL with a selected modified clock-pulse cp according to whether that bit was recognized as "normal, " "early," late," etc.

Thus, the "raw" clock pulses wc are also applied _v o a Delay Buffer stage DLB, adapted, as known in the art, to output various time-shifted signals which are shifted somewhat from nominal clock-time to "normal" or somewhat earlier ("early" or "early-early") or somewhat later ("late" or "late-late") than the normal clock pulse. DLB inputs these to multiplexer, MUX for correlation with each write-bit as known in the art.

For instance, in FIG. 2, by way of explanation a prescribed string of original unprecompensated write bits are shown as sample pattern 1001. Now, if these 1- its are not time-shifted or precompensated, the readback wave-form (see FIG. 2B) peaks, and the digital lead data bits displaced in time with a bit early and a __ _ ι_a e, relative to the initiation and termination of a pulse of write current (see Wave 2A) . For instance, such may be mistaken as a "next bit" [if the time-shift is outside a prescribed time "window" as known in the art]. Such is indicated;, for example, as pulses 2C. By performing the indicated precompensation (time-shift) on bits 1, 1 as indicated, the read-back data is time-corrected; e.g., as read-back pattern Delta suggests.

Preferred Precompensation Technique FIG. 3,

Method:

FIG. 3 schematically depicts a preferred precompensation method A, according to the subject invention which requires only a prescribed 8-bit shift register SRR, in-putting a latch L and a control stage C, together with a prescribed PROM (programmable ROM) plus a Delay Module DM and a Multiplexer MUX.

The PROM accepts input from register S-SRR by way of latch L in parallel with "zone select signals" and "delay select signals." The output from the PROM is directed to multiplexer MUX together with delayed output from the control stage C [delayed via Delay Module DM].

Thus, operation may proceed as follows: Input write data pulses dd are first clocked into the 8-bit shift register SRR (by write pulses WC). This gives 9 total bits of stored information including the input write data. According to this method A, we designate the "5th" bit as "center bit." When a ONE is detected as the "center bit," then the 1st, 2nd, 8th, and 9th bits are latched into data latc L.

For 1/2 (2, 7) data code, the 1st, 2nd, 8th, and 9th bits provide information as to the location of adjacent transitions. A ONE as bits 2 or 8 indicates a transition "Tmin away," while a ONE for bits 1 or 9 indicates a transition "Tmin+1 away." A ZERO in all 4 bits (bits 1, 2, 8 and 9 indicates that adjacent transitions are at least "Tmin+2 away." The PROM also gets input from two "zone select" lines and two precompensation "delay select" lines as indicated. The "zone select" lines correlate precompensation with the radial location of the head (where the subject track is radially on a given disk) and the "delay select" ("data set select") lines are determined by the predetermined "delay-characteristic" of the subject selected head.

Based on these inputs (data pattern, "zone" and "delay" selects), the output of the PROM yields the desired precompensation value. This controls the programmable Delay Module DM to shift the (now-delayed) center bit by the proper amount.

Workers will understand that the circuit is "event-driven" according to the center bit in any given bit pattern_; and, latch L retains such data pattern so that enough time will elapse to process the data through the delay module DM. Second Preferred Embodiment, FIG. 4: Method B:

FIG. 4 indicates a. precompensation arrangement PC-B much like that in FIG.^" 3 described above, but somewhat more complex and versatile, being otherwise the same as indicated in FIG. 3.

That is, FI_G. 4 shows a preferred precompensation circuit PC-B in block-diagram form, while a preferred circuit implementation therefore is shown in FIG. 5 with associated functional units similarly designated. In FIG. 4, the following units are noteworthy:

Element 1 is a shift register adapted to receive input "write data" which is clocked-in by read-write clock pulses as indicated, 9. bits of input data being stored at each clock cycle.

Element 2 is a control logic stage, taking input from shift register 1, as well as RW clock signals, and is adapted, generally, to generate control signals to be applied to data latches V and 5. This stage 2 also generates a delayed "data bit" applied to programmable delay module 6 as indicated.

Data latch 3 is adapted to receive input from shift register 1 and latch the 1st, 2nd, 8th, and 9th bit in each bit-pattern, wherever a "center bit" in position 5 is detected by control logic stage 2.

Delay PROM 4 is adapted to receive the output from data latch 3, which stores the data-pattern information_; also receiving input from "zone select" lines ZS [two indicated here] and from "precompensation data set select" lines PD-SS [two here also]. The output of PROM 4 provides the desired "precompensation delay" to be applied (directly or indirectly) to programmable delay module 6, in conjunction with the "delayed data bit" from control logic stage 2, and so provide the desired data output.

The foregoing are the more essential elements in terms of describing salient invention features^; other associated elements will now be described, referring to the Delta diagram in FIG. 4. A second latch 5 is adapted to take the output of delay PROM 4 and hold it for application to programmable Delay Module 6, as indicated. A second control logic stage 7 is adapted to combine the output of module 6 with external control signals as indicated, and apply an output signal to multiplexer stage 8. Multiplexer 8 •combines this "precompensated" data with external write-data and performs multiplex selection; e.g., controlled by a prescribed "ENARBER" signal from translater unit 9 [unit 9 converts TTL input control signals to ECL levels].

A first line receiver unit 10 receives differential write data input and outputs to register 1, while a second line receiver unit 11 receives differential read/write clock input and outputs to register 1, also.

In FIG. 4, it will be understood that a shift register 1 is provided inputting along with a Line Receiver stage 11 and Control Logic stage 2, to a data latch 3- The output from Latch DL is applied to a Delay PROM 4 along with certain select signals from a Translator stage 9 (see below) PROM 4 outputs to second Latch 5 and thence to a Programmable Delay Module 6, in conjunction with signals from control stage 2. The output from Module 6 is applied to an output Control

Logic stage 7 in conjunction with write-gate and Aτι-gate signals. The output from Logic stage 7 is applied to a multiplexer 8 in conjunction with plus write data signals and other signals (from Translator TTR as indicated). The out from MUX 8 is sent to the disk drive for use as precompensated write signals.

Claims

A _preferred circuit implementing the embodiment in FIG. 4 is indicated in FIG. 5, with parts thereof similarly designated.

Workers will recognize several key advantageous features of our precompensation techniques, such as the following:

1 A PROM is used to determine precompensation based on the input write data patterns, on a disk-zone select and on head characteristics. The precompensation can be changed by changing the PROM, without need for hardware logic modification.

2. Precompensation levels are expanded to a number (e.g., 16) of equally-spaced levels, instead of only a few predetermined levels. This allows a better matching of precompensation to reduce "peak-shifts" for various data patterns.

_3# The detection of "Tmin+1" data patterns for "run length limited" (RLL) code, in addition to "Tmin" data patterns, allows further reduction of peak shift.

4. The inclusion of (four) sets of head-precompensation data which allows for a better matching of the peak-shift characteristics of each head to one of the precompensation data sets.

5. Precompensation zones are also applied such that the precompensation levels are changed, depending on the location of the heads on the disk.

What is claimed is: . An arrangement for precompensating write data before writing on a given track of a diskdrive/recording system with a plurality of write-transducers wherein multi-bit patterns are to be recorded, this arrangement - involving: means D for determining the shift-characteristic

S-C for each transducer; a prescribed PROM; means I for inputting each write data bit pattern to said PROM and for advancing or delaying prescribed selected bits in this pattern according to the radial position of said head on the disk, according to the shift-characteristic of the involved transducer, and according to the content of the bit pattern.

2. The invention of claim 1 wherein said arrangement is adapted to reduce the effect of "peak shift" in digital magnetic recording channels using a "run-length-limited" code.

3. The invention of claim 2 including means A for first identifying all critical data patterns which cause significant "peak-shift," including "worst case peak shift" patterns which have "Tmin" separation and data patterns which have "Tmin+1" separation, assuming "Tmin" is the minimum distance between two adjacent bit transitions_; the precompensation data being stored in said PROM.

_,. The invention of claim 3 wherein means A includes

4 sixteen selection levels provided for a "best match" of precompensation.

5. The invention of claim 3 wherein means A is characterized by N sets of predetermined precompensation data to be stored in said PROM, and adapted for selection according to the peak-shift distribution of each said transducer, the transducer having been pretested to determine its peak-shift characteristic and "tagged" with one of said four sets of associated precompensation data which best matches its peak-shift characteristic^; and wherein a separate memory device is included to store said tag information.

6. The invention of claim 5 wherein four precompensation zones are set and identified to best compensate for the change in peak-shift as a function of radial position of the head on said disk.

7. The invention of claim 6 as implemented in a circuit consisting essentially of an input shift register, data latch means, PROM means, programmable delay means, and associated .control logic.

8. An arrangement for precompensating write-bits by a plurality of recording heads, in a diskdrive recording system, the arrangement comprising: register means R, adapted to store write-bits; latch means L adapted to receive output signals from said register means R, PROM means P adapted to receive output from said latch means L as well as zone signals S indicating radial location of the subject disk track and head signals h indicating a peak-shift characteristic of the subject head said PROM means P being adapted to correlate all said input for each bit, each track and each head and responsively time-shift each bit as its output P-o; output means O adapted to receive said PROM output P-o along with R/W clock pulses and responsively issue precompensated write-bit output; and control logic means C adapted to control .these operations.

9. The invention of claim 8 where a 1/2 (2, 7) code is assumed; and wherein register R is a 9-bit shift register, storing 9 write-bits.

10. The invention of claim 9 wherein latch means L is adapted to latch the 1st, 2nd, 8th, and 9th bit pattern according to prescribed condition of the 5th bit therein, as detected by said control logic C.

11. The invention of claim 10 wherein said output means 0 comprises a Programmable Delay Module adapted to clock-out said output as controlled by delayed data bits from control logic means C.