WO1988008576A3 - Apparatus and method for servicing interrupts utilizing a pended bus - Google Patents

Apparatus and method for servicing interrupts utilizing a pended bus Download PDF

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Publication number
WO1988008576A3
WO1988008576A3 PCT/US1988/001247 US8801247W WO8808576A3 WO 1988008576 A3 WO1988008576 A3 WO 1988008576A3 US 8801247 W US8801247 W US 8801247W WO 8808576 A3 WO8808576 A3 WO 8808576A3
Authority
WO
WIPO (PCT)
Prior art keywords
interrupt
node
servicing
interrupting node
interrupting
Prior art date
Application number
PCT/US1988/001247
Other languages
French (fr)
Other versions
WO1988008576A2 (en
Inventor
Douglas D Williams
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to JP63506377A priority Critical patent/JPH0679305B2/en
Priority to KR1019880701792A priority patent/KR910007643B1/en
Priority to DE88906581T priority patent/DE3882991T2/en
Publication of WO1988008576A2 publication Critical patent/WO1988008576A2/en
Publication of WO1988008576A3 publication Critical patent/WO1988008576A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Position Input By Displaying (AREA)

Abstract

Apparatus and method for servicing interrupt requests on a pended bus. An interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service an interrupt request message. The interrupt servicing node includes storage means for specifying the identity of a particular interrupting node and for indicating that an interrupt request is pending from a particular interrupting node. An interrupting node provides to the pended bus an interrupt request message including ID data for identifying the interrupting node as the source of an interrupt request. The interrupting node detects whether an interrupt acknowledge message on the bus includes destination data specifying that interrupting node.
PCT/US1988/001247 1987-05-01 1988-04-19 Apparatus and method for servicing interrupts utilizing a pended bus WO1988008576A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP63506377A JPH0679305B2 (en) 1987-05-01 1988-04-19 Device and method for responding to an interrupt using a hold bus
KR1019880701792A KR910007643B1 (en) 1987-05-01 1988-04-19 Apparatus and method for serving interrupts utilizing pended bus
DE88906581T DE3882991T2 (en) 1987-05-01 1988-04-19 ARRANGEMENT AND METHOD FOR OBTAINING INTERRUPTIONS WITH A "PENDED BUS".

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US4504687A 1987-05-01 1987-05-01
US045,046 1987-05-01

Publications (2)

Publication Number Publication Date
WO1988008576A2 WO1988008576A2 (en) 1988-11-03
WO1988008576A3 true WO1988008576A3 (en) 1988-12-29

Family

ID=21935728

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/001247 WO1988008576A2 (en) 1987-05-01 1988-04-19 Apparatus and method for servicing interrupts utilizing a pended bus

Country Status (8)

Country Link
US (1) US5146597A (en)
EP (1) EP0358725B1 (en)
JP (1) JPH0679305B2 (en)
KR (1) KR910007643B1 (en)
AU (1) AU604959B2 (en)
CA (1) CA1306068C (en)
DE (1) DE3882991T2 (en)
WO (1) WO1988008576A2 (en)

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US5581770A (en) * 1992-06-04 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Floating interruption handling system and method
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US5848279A (en) * 1996-12-27 1998-12-08 Intel Corporation Mechanism for delivering interrupt messages
US6240474B1 (en) * 1997-09-16 2001-05-29 International Business Machines Corporation Pipelined read transfers
US6493779B1 (en) * 1998-12-21 2002-12-10 International Business Machines Corporation Method and system for interrupt handling using device pipelined packet transfers
US7251690B2 (en) * 2002-08-07 2007-07-31 Sun Microsystems, Inc. Method and system for reporting status over a communications link
US8984199B2 (en) * 2003-07-31 2015-03-17 Intel Corporation Inter-processor interrupts
US7386642B2 (en) 2005-01-28 2008-06-10 Sony Computer Entertainment Inc. IO direct memory access system and method
US7680972B2 (en) * 2005-02-04 2010-03-16 Sony Computer Entertainment Inc. Micro interrupt handler
JP2006216042A (en) * 2005-02-04 2006-08-17 Sony Computer Entertainment Inc System and method for interruption processing

Citations (1)

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EP0139568A2 (en) * 1983-09-22 1985-05-02 Digital Equipment Corporation Message oriented interrupt mechanism for multiprocessor systems

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Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0139568A2 (en) * 1983-09-22 1985-05-02 Digital Equipment Corporation Message oriented interrupt mechanism for multiprocessor systems

Also Published As

Publication number Publication date
US5146597A (en) 1992-09-08
KR910007643B1 (en) 1991-09-28
DE3882991D1 (en) 1993-09-09
AU604959B2 (en) 1991-01-03
JPH02503367A (en) 1990-10-11
DE3882991T2 (en) 1994-03-24
WO1988008576A2 (en) 1988-11-03
KR890702138A (en) 1989-12-23
JPH0679305B2 (en) 1994-10-05
EP0358725B1 (en) 1993-08-04
AU2134788A (en) 1988-12-02
EP0358725A1 (en) 1990-03-21
CA1306068C (en) 1992-08-04

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