WO1986002488A1 - Coating of iii-v and ii-vi compound semiconductors - Google Patents

Coating of iii-v and ii-vi compound semiconductors Download PDF

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Publication number
WO1986002488A1
WO1986002488A1 PCT/US1985/001930 US8501930W WO8602488A1 WO 1986002488 A1 WO1986002488 A1 WO 1986002488A1 US 8501930 W US8501930 W US 8501930W WO 8602488 A1 WO8602488 A1 WO 8602488A1
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Prior art keywords
layer
semiconductor
silicon
iii
diffusion
Prior art date
Application number
PCT/US1985/001930
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French (fr)
Inventor
Irfan Camlibel
Aland Kwang-Yu Chin
Shobha Singh
Legrand Gerard Van Uitert
George John Zydzik
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American Telephone & Telegraph Company
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Publication date
Application filed by American Telephone & Telegraph Company filed Critical American Telephone & Telegraph Company
Priority to AT85904953T priority Critical patent/ATE53145T1/en
Priority to DE8585904953T priority patent/DE3577946D1/en
Publication of WO1986002488A1 publication Critical patent/WO1986002488A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/471—Inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal

Definitions

  • V and II-VI compound semiconductor devices and, in particular, to the formation of coatings on the surface of said devices.
  • III-V and II-VI compound semiconductor devices One of the critical steps in the fabrication of III-V and II-VI compound semiconductor devices is the formation of localized p-n junctions and ohmic contacts by diffusion of material into the semiconductor surface. Such diffusions require a mask which does not interact with the semiconductor, which is impermeable to the diffusing species and which remains intact at high temperatures. In some processing, it is also important to anneal the devices at high temperature. During such an annealing, the device is usually encapsulated with a coating to avoid thermal decomposition of the semiconductor. This coating must also remain intact and not interact with the semiconductor even at high temperatures.
  • silicon dioxide or silicon nitride is typically used as a diffusion mask or encapsulation coating. While generally adequate, use of such layers produces problems in reproducibility since the stoichiometry and physical properties of these films can vary depending on deposition conditions. Further, the thermal coefficient of expansion of these films differs greatly from that of the semiconductor, thereby causing stresses which can crack the coating during thermal treatments and can cause undesired lateral diffusion of the impurity in the semiconductor surface.
  • a layer of silicon is formed on the surface of the semiconductor in a manner avoiding significant damage to the surface.
  • the structure is subsequently heated to a temperature of at least 400 degrees C.
  • FIGS. 1-4 are cross-sectional views of a device in various stages of fabrication in accordance with one embodiment of the invention. Detailed Description
  • the starting material in the practice of this invention, FIG. 1, is usually a substrate, 10, of a III-V or II-VI semiconductor material.
  • the material is n-type InP with an impurity concentration of approximately 5 x 10 16cm—3.
  • an undoped epitaxial layer, 14, comprising
  • InGaAs with a thickness of approximately 4 ⁇ m.
  • the epitaxial layer is considered to be part of the substrate and no distinction between the two will be made herein.
  • a layer, 11, comprising undoped silicon is deposited on one major surface of the substrate. It is important that the deposition process not produce any significant damage to the substrate surface. If the layer were sputtered on, for example, the silicon layer would have a tendency to diffuse into the substrate during subsequent heat treatments. (See, for example, Antell, "The Diffusion of Silicon in Gallium Arsenide," Solid State Electronics, Vol. 8. pp.
  • the layer was deposited by a process which does not damage the surface, the silicon layer will not diffuse into the semiconductor to any significant degree and can therefore be used as an effective diffusion mask and/or encapsulation coating.
  • the layer was deposited by a standard electron-beam evaporation technique where the substrate was placed in a vacuum chamber along with a source of silicon and the source was bombarded by an electron beam while the substrate was held at a temperature of approximately 150 degrees C. Other methods which can be used include thermal evaporation and chemical vapor deposition.
  • the thickness of the layer in this example was approximately 3,000 Angstroms, although it is expected that layer thicknesses in the range 100- 10,000 Angstroms should provide useful coatings.
  • the resistivity of the undoped silicon in this example was 6000 ⁇ -cm. It is preferred that the silicon layer be undoped (carrier concentration i i 15 -3
  • the purer the film the lower will be the electrical leakage through the film during device operation.
  • the less pure silicon layer may be economically desirable if the devices can withstand some electrical leakage through the layer.
  • Deposition should also take place at a sufficiently low temperature to insure that the semiconductor substrate is not thermally damaged, otherwise reproducibility problems such as experienced in prior art processes may be encountered. Consequently, a useful temperature range for deposition is approximately 25-200 degrees C for II-VI semiconductor substrates and approximately 25-400 degrees C for III-V semiconductor substrates.
  • the layer apparently can be amorphous or polycrystalline. At the temperature employed in this example, it could be characterized as either since it contains some crystalline order and the boundary between "amorphous" and "crystalline” is not clearly drawn in the art.
  • the deposited layer has a thermal coefficient of expansion of approximately 4 x 10 per degrees centigrade which reasonably matches that of the III-V and II-VI semiconductors. In general, it is desirable that the coefficients of expansion of the layer and semiconductor differ by no more than 5 x 10 per degrees centigrade and preferably by no more than 2 x 10 ⁇ per degrees centigrade.
  • a window 12 was opened in the silicon layer by means of standard photolithographic etching techniques.
  • the photoresist layer (not shown) was positive photoresist manufactured by Shipley (Product No. AZ1350) which was developed to form circular openings approximately 75 ⁇ m in diameter.
  • the exposed silicon was etched using a freon plasma, but other standard etching techniques might be employed.
  • the structure was subsequently subjected to a diffusion process utilizing the silicon layer as a mask in order to form a localized p-type region, 13, in the exposed surface of the semiconductor substrate.
  • the diffusion was carried out in a sealed ampoule utilizing Zn as the diffusant at a temperature of approximately 550 degrees C for approximately 30 minutes. This produced a junction depth of approximately 2 ⁇ m.
  • other p-type or n-type diffusants can be employed.
  • diffusion will be done at temperatures of 200- - 600 degrees C for II-VI semiconductor substrates and 400- 1 ,000 degrees C for III-V semiconductor substrates for a period of time within the range 1 min-100 hrs. Some diffusion operations may require temperatures of at least 900 degrees C.
  • Ohmic contact to the p-region was provided by depositing a Cr-Au alloy metal 16 over the window.
  • ohmic contact to the n-region was provided by a layer, 17, of Cr- Au.
  • a window was provided for the entrance of light and into this window an antireflection coating, ' 18, typically comprising silicon nitride, was deposited.
  • the silicon layer, 11, remains on the surface of the device to provide electrical insulation in place of standard Si0 2 and Sio ⁇ layers.
  • the silicon layer, 11, can be removed by a suitable etchant subsequent to the diffusion operation.
  • the silicon layer 11 can also be utilized as an encapsulation coating to prevent out- diffusion of the semiconductor components during annealing operations. Typical annealing cycles, which the silicon layer should withstand, are the same ranges given previously for diffusion processes.
  • the inventive method can be employed for fabricating a wide variety of III-V and II-VI semiconductor devices requiring a diffusion and/or an annealing step such as heterostructure lasers and LEDs. In some situations, it may be desirable to etch the silicon layer only partially through to form the opening for diffusion.
  • the silicon layer can also be used as a mask in ion implantation processes .
  • III-V semiconductor substrates which can be used include GaAs and AlGaAs.
  • Some II-VI semiconductor substrates are HgCdTe, CdTe, PbTe and PbSnTe.
  • devices is intended to include integrated circuits as well as discrete devices.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method of fabricating III-V and II-VI compound semiconductors comprising depositing a silicon coating (11) on the semiconductor substrate (10), which coating serves as a diffusion mask and/or a passivation layer. The coating is deposited by avoiding damage to the semiconductor surface.

Description

COATING OF III-V AND II-VI COMPOUND SEMICONDUCTORS
Background of the Invention This invention relates to the fabrication of III-
V and II-VI compound semiconductor devices and, in particular, to the formation of coatings on the surface of said devices.
One of the critical steps in the fabrication of III-V and II-VI compound semiconductor devices is the formation of localized p-n junctions and ohmic contacts by diffusion of material into the semiconductor surface. Such diffusions require a mask which does not interact with the semiconductor, which is impermeable to the diffusing species and which remains intact at high temperatures. In some processing, it is also important to anneal the devices at high temperature. During such an annealing, the device is usually encapsulated with a coating to avoid thermal decomposition of the semiconductor. This coating must also remain intact and not interact with the semiconductor even at high temperatures.
In the fabrication of III-V and II-VI compound devices, silicon dioxide or silicon nitride is typically used as a diffusion mask or encapsulation coating. While generally adequate, use of such layers produces problems in reproducibility since the stoichiometry and physical properties of these films can vary depending on deposition conditions. Further, the thermal coefficient of expansion of these films differs greatly from that of the semiconductor, thereby causing stresses which can crack the coating during thermal treatments and can cause undesired lateral diffusion of the impurity in the semiconductor surface.
It is therefore an object of the invention to provide a coating for III-V and II-VI compound semiconductors, which coating is highly reproducible and has a close thermal expansion match with the semiconductor.
Summary of the Invention
A layer of silicon is formed on the surface of the semiconductor in a manner avoiding significant damage to the surface. The structure is subsequently heated to a temperature of at least 400 degrees C. Brief Description of the Drawing
FIGS. 1-4 are cross-sectional views of a device in various stages of fabrication in accordance with one embodiment of the invention. Detailed Description
The starting material in the practice of this invention, FIG. 1, is usually a substrate, 10, of a III-V or II-VI semiconductor material. In this example, the material is n-type InP with an impurity concentration of approximately 5 x 10 16cm—3. Formed on the substrate was an undoped epitaxial layer, 14, comprising
InGaAs with a thickness of approximately 4 μm. (The epitaxial layer is considered to be part of the substrate and no distinction between the two will be made herein.) On one major surface of the substrate a layer, 11, comprising undoped silicon is deposited. It is important that the deposition process not produce any significant damage to the substrate surface. If the layer were sputtered on, for example, the silicon layer would have a tendency to diffuse into the substrate during subsequent heat treatments. (See, for example, Antell, "The Diffusion of Silicon in Gallium Arsenide," Solid State Electronics, Vol. 8. pp. 943-946 (1965).) We have found, however, that if the layer is deposited by a process which does not damage the surface, the silicon layer will not diffuse into the semiconductor to any significant degree and can therefore be used as an effective diffusion mask and/or encapsulation coating. In this example, the layer was deposited by a standard electron-beam evaporation technique where the substrate was placed in a vacuum chamber along with a source of silicon and the source was bombarded by an electron beam while the substrate was held at a temperature of approximately 150 degrees C. Other methods which can be used include thermal evaporation and chemical vapor deposition. The thickness of the layer in this example was approximately 3,000 Angstroms, although it is expected that layer thicknesses in the range 100- 10,000 Angstroms should provide useful coatings. The resistivity of the undoped silicon in this example was 6000 ω-cm. It is preferred that the silicon layer be undoped (carrier concentration i i 15 -3 | D-NΛ| < 10 cm so that it can be assured of uniform properties after each deposition and to provide a high resistivity (at least
4 ω-cm). Furthermore, the purer the film, the lower will be the electrical leakage through the film during device operation. For some types of devices, however, the less pure silicon layer may be economically desirable if the devices can withstand some electrical leakage through the layer. Deposition should also take place at a sufficiently low temperature to insure that the semiconductor substrate is not thermally damaged, otherwise reproducibility problems such as experienced in prior art processes may be encountered. Consequently, a useful temperature range for deposition is approximately 25-200 degrees C for II-VI semiconductor substrates and approximately 25-400 degrees C for III-V semiconductor substrates. The layer apparently can be amorphous or polycrystalline. At the temperature employed in this example, it could be characterized as either since it contains some crystalline order and the boundary between "amorphous" and "crystalline" is not clearly drawn in the art.
The deposited layer has a thermal coefficient of expansion of approximately 4 x 10 per degrees centigrade which reasonably matches that of the III-V and II-VI semiconductors. In general, it is desirable that the coefficients of expansion of the layer and semiconductor differ by no more than 5 x 10 per degrees centigrade and preferably by no more than 2 x 10~ per degrees centigrade.
As shown in FIG. 2, a window 12 was opened in the silicon layer by means of standard photolithographic etching techniques. The photoresist layer (not shown) was positive photoresist manufactured by Shipley (Product No. AZ1350) which was developed to form circular openings approximately 75 μm in diameter. The exposed silicon was etched using a freon plasma, but other standard etching techniques might be employed.
As illustrated in FIG. 3, the structure was subsequently subjected to a diffusion process utilizing the silicon layer as a mask in order to form a localized p-type region, 13, in the exposed surface of the semiconductor substrate. The diffusion was carried out in a sealed ampoule utilizing Zn as the diffusant at a temperature of approximately 550 degrees C for approximately 30 minutes. This produced a junction depth of approximately 2 μm. Of course, other p-type or n-type diffusants can be employed. In general, diffusion will be done at temperatures of 200- - 600 degrees C for II-VI semiconductor substrates and 400- 1 ,000 degrees C for III-V semiconductor substrates for a period of time within the range 1 min-100 hrs. Some diffusion operations may require temperatures of at least 900 degrees C. It is desirable that no significant amount of SiO be formed on the semiconductor surface. This can be prevented either by diffusing in a sealed ampoule as in the present example, or diffusing in a relatively oxygen- free ambient. Cleaving and staining the wafer revealed no undue lateral diffusion of the impurity, which would have occurred if there had been excess stresses between the silicon layer and semiconductor substrate. Further, low leakage currents (less than 20 nA at 10V reverse bias) , comparable to those obtained using silicon nitride as a diffusion mask, were observed. Surprisingly, though silicon is often used as a dopant impurity in semiconductors, it was found that no significant diffusion of the silicon into the semiconductor had occurred. This is believed due to the lack of stress effects at the surface normally caused by the deposition of the silicon or by overlying the silicon with another layer. (See
Greiner et al, "Diffusion of Silicon in Gallium Arsenide Using Rapid Thermal Processing," Applied Physics Letters, Vol. 44, pp. 750-752 (April 15, 1984).)
In the final stages of fabrication, a second layer of silicon, 15, which was identical to the first layer, 11, was deposited over the first layer and a window opened over the p-region 13 by standard photolithography. Ohmic contact to the p-region was provided by depositing a Cr-Au alloy metal 16 over the window. Similarly, ohmic contact to the n-region was provided by a layer, 17, of Cr- Au. In the latter contact, a window was provided for the entrance of light and into this window an antireflection coating,' 18, typically comprising silicon nitride, was deposited. It will be noted in this example that the silicon layer, 11, remains on the surface of the device to provide electrical insulation in place of standard Si02 and Sio ^ layers. If desired, the silicon layer, 11, can be removed by a suitable etchant subsequent to the diffusion operation. If desired, the silicon layer 11 can also be utilized as an encapsulation coating to prevent out- diffusion of the semiconductor components during annealing operations. Typical annealing cycles, which the silicon layer should withstand, are the same ranges given previously for diffusion processes.
The inventive method can be employed for fabricating a wide variety of III-V and II-VI semiconductor devices requiring a diffusion and/or an annealing step such as heterostructure lasers and LEDs. In some situations, it may be desirable to etch the silicon layer only partially through to form the opening for diffusion. The silicon layer can also be used as a mask in ion implantation processes .
Other III-V semiconductor substrates which can be used include GaAs and AlGaAs. Some II-VI semiconductor substrates are HgCdTe, CdTe, PbTe and PbSnTe.
In the attached claims the term "devices" is intended to include integrated circuits as well as discrete devices.

Claims

Claims
1. A method for fabricating III-V and II-VI compound semiconductor devices characterized by the steps of forming a layer (11) comprising silicon on a major surface of a semiconductor substrate (10) in a manner which does not cause significant damage to the semiconductor surface and subsequently heating the structure without causing significant diffusion of the silicon layer into the surface of the semiconductor.
2. The method according to claim 1 wherein an opening (12) is formed in the silicon layer and impurities are introduced into the semiconductor through the opening while the silicon layer acts as a mask.
3. The method according to claim 2 wherein the structure is heated to a temperature within the range 200-
1,000 degrees C for a time within the range 1 min-100 hrs.
4. The method according to claim 1 wherein the thickness of the layer is within the range 100—
10,000 Angstroms.
5. The method according to claim 1 wherein the layer is deposited by electron-beam evaporation.
6. The method according to claim 1 wherein the structure is heated to a temperature within the range 200- 1,000 degrees C for a time of 1 min-100 hrs in order to anneal the semiconductor while the silicon layer prevents out-diffusion of the semiconductor components.
7. The method according to claim 1 wherein the layer consists essentially of undoped silicon.
8. A semiconductor device comprising a body of (10) semiconductor material selected from the group consisting of III-V and II-VI compounds, and a layer comprising silicon (11) formed on at least a portion of a major surface of said semiconductor.
9. The device according to claim 8 wherein the layer consists essentially of undoped silicon.
10. The device according to claim 8 wherein the thickness of the layer is within the range 100- 10,000 Angstroms.
PCT/US1985/001930 1984-10-09 1985-10-03 Coating of iii-v and ii-vi compound semiconductors WO1986002488A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AT85904953T ATE53145T1 (en) 1984-10-09 1985-10-03 PROTECTIVE COATING FOR III-V AND II-VI COMPOUND SEMICONDUCTORS.
DE8585904953T DE3577946D1 (en) 1984-10-09 1985-10-03 PROTECTIVE LAYER FOR III-V AND II-VI CONNECTION SEMICONDUCTORS.

Applications Claiming Priority (2)

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US658,569 1984-10-09
US06/658,569 US4634474A (en) 1984-10-09 1984-10-09 Coating of III-V and II-VI compound semiconductors

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EP (1) EP0202240B1 (en)
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US4772489A (en) * 1985-09-20 1988-09-20 Sumitomo Electric Industries, Ltd. Method of annealing a compound semiconductor substrate
US4987095A (en) * 1988-06-15 1991-01-22 International Business Machines Corp. Method of making unpinned oxide-compound semiconductor structures
US5086321A (en) * 1988-06-15 1992-02-04 International Business Machines Corporation Unpinned oxide-compound semiconductor structures and method of forming same
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CA1250055A (en) 1989-02-14
DE3577946D1 (en) 1990-06-28
EP0202240B1 (en) 1990-05-23
JPS62500414A (en) 1987-02-19
US4634474A (en) 1987-01-06

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