WO1982002789A1

WO1982002789A1 - Polyphonic music unit employing digital music synthesis

Info

Publication number: WO1982002789A1
Application number: PCT/US1982/000128
Authority: WO
Inventors: Eng Smith; Jay Smith; Gerald S Karr
Original assignee: Eng Smith
Priority date: 1981-02-04
Filing date: 1982-02-01
Publication date: 1982-08-19

Abstract

Electronic polyphonic music apparatus employing digital music synthesis circuitry. A preferred embodiment of the apparatus includes three digitally-controlled tone generators (200, 300, 400) which simultaneously produce three signals of independently selected frequencies. The generators (200, 300, 400) operate in response to a tone generator controller (150) which produces digital signals for controlling the rest or off period of each of the generators and frequency control circuitry for producing digital signals for controlling the tone or frequency of each of the generators. The output of each of three tone generators is coupled to a single digitally-controlled variable attenuator bank (205) by way of multiplexer circuitry (201, 202, 203). The tone generators are controlled so that only one generator is coupled to a given attenuator at any given time. The output of the attenuator bank is connected to an audio transducer (700) through a conventional audio amplifier (600). Also disclosed is a structure bonding the circuitry in LSI format to the transducer.

Description

POLYPHONIC MUSIC UNIT EMPLOYING DIGITAL MUSIC SYNTHESIS

BACKGROUND OF THE INVENTION

Field of the Invention

The field of this invention is music generators and more particularly, music generators employing digital music synthesis.

Description of the Prior Art

Music generators such as music boxes have long been known. The typical mechanical music box generates musical tones by striking a plurality of resonate mechanical elements. High quality units generate tones of exceptional clarity and of an alluring and highly pleasing quality. However, mechanical units, capable of such tonal quality are relatively expensive, and may be of substantial size if the tune to be played is of any substantial length. Care must be taken in the manu¬ facturing process to ensure appropriate dimensional tolerances for the resonant elements.

There have been in the past numerous attempts to synthesize music and/or reproduce electronically the type of sound produced by mechanical music boxes. Typical examples are disclosed in U.S. Patents 3,878,750 (Kapps), 4,090,349 (Takase), 4,012,979 (Wemekamp) and

O PI

- 3,890,871 (Oberheim). Kapps discloses a programmable music key board music synthesizer wherein each of a sequence of notes is digitally encoded in terms of a scalar value of the note, its time duration and relative octave range. The synthesizer is operable in a playback mode wherein the encoded information is automatically withdrawn in accordance with the order in which the notes are store. The Kapps device is limited in that the unit is not amenable to polyphonic music generation

10 without substantial duplication of the circuit elements. In order to obtain the capability of generating a plurality of notes in a time overlap manner, Kapps requires a plurality of the^' time recorders illustrated in Figure 2 of that reference. Another disadvantage of 5 Kapps is that the device described is limited to generating notes in a two octave range. Takase dis¬ closes an electronic music box circuit wherein the contents of a read only memory are utilized to select a signal output of a selective frequency, and to select a

20 signal level for that signal. A primary disadvantage of the Takase circuit is that individual frequency gener¬ ators are apparently required for each of the possible tones. Oberheim and eme amp also disclose keyboard synthesizers having "record" and playback modes.

^5 Each of the synthesizers disclosed in these references require relatively complex circuitry imple- ^* mentations and are not readily amenable to polyphonic^' music generation. The prior art apparatus known to applicants does not simulate the exceptional tonal

30 quality of mechanical music boxes in an inexpensive manner. As will be apparent from the following disclosure, these limitations are overcome by the present invention. Summary of the Invention

The preferred embodiment of the present invention provides a device which digitally synthesizes the unusual tonal qualities produced by a mechanical music generator, in an inexpensive manner and which uses a very inexpensive audio transducer means. The appar¬ atus may be implemented on a single monolithic LSI chip, which directly drive-s a piezoelectric transducer (a monomorph "bender^π ) . The present invention comprises a polyphonic electronic music generating apparatus which employs a novel digital music synthesis.

In the preferred embodiment, the apparatus includes three tone generators for producing simultane¬ ously three signals of independently selected frequen- cies. The tone generators include presettable digital down counters responsive to an eight bit input word containing frequency information, the down counter toggling a flip-flop to produce an output signal of the desired frequency. It has been discovered that a square- wave signal produced a very realistic music box tonal quality.

A single attenuator bank is coupled to the outputs of the tone generators for introducing sequen¬ tially a plurality of attenuators between the tone generators and the audio transducer so as to not only control the audio signal level but affect the attack and decay characteristics of the selected note.

The information which controls the operation of the tone generators comprises tone information (i.e. frequency) and an interval or "rest" value. The tone information comprises a digital word which is operated on by the tone generators to produce a signal of the desired frequency, while the "rest" information controls the time interval between successive enable ent of the

OMPI next tone generator. One aspect of the present inven¬ tion is that no tone duration information is required, as in prior art systems. The capability of selecting a number of discrete rest intervals is provided. By appro- priate selection of note and rest intervals, a musical tune of exceptional tonal quality may be generated.

The tone generators are operative simultane¬ ously and in a time overlap manner. Each generator produces a given tone until a new tone value is loaded into the down counter of the respective tone generator and the counter re-enabled. The tone generator output is sequenced through the individual resistors of the attenuator bank within a selected interval, one half second in the preferred embodiment. Upon expiration of the current rest interval, a new tone input word is. clocked into the succeeding tone generator, and a new rest value is loaded into the rest interval timer. In the preferred embodiment disclosed, a tone generator continues generation of the tone until a new tone value is loaded into the down counter and the generator enabled.

Only one resistor bank is needed, as the generators are controlled so that, except the final resistor, only one generator output is coupled to a given attenuator at any given time.

The invention is ideally suited to large scale integrated ("LSI") techniques.

In one embodiment, the circuit is fabricated in a single chip which may be bonded directly to a piezoelectric "bender" transducer.

Other features and improvements are disclosed.

_URE_ ^

OMPI ^* BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE 1 is a block diagram depicting the primary circuit components of the preferred embodiment of the present invention.

FIGURES 2a-d are schematic diagrams of the circuit of the controller.

FIGURE 3 is a flow chart depicting the logic operation of the controller.

FIGURE 4 is a flow chart depicting operation of a tone generator.

FIGURE 5 is a perspective view of a preferred physical embodiment of a music generator according to the present invention. Figures 6a-b are perspective views of a second preferred physical embodiment music generator according to the present inventipn.

DETAILED DESCRIPTION OF THE INVENTION

The present invention comprises a novel music synthesizer employing digital music synthesis. A plural¬ ity of tone generators are each sequentially enabled to generate tones, allowing the synthesizer to simultane¬ ously generate a plurality of tones. Variable attenua¬ tors are provided which vary the attenuation of each tone generator signal applied to an audio transducer. By appropriate selection of the attenuator values, one may affect the attack and decay characteristic of the notes to produce the type of musical effect created by the polyphonic synthesizer. In the preferred embodi¬ ment, the resistive values are selected to provide similar attack and decay characteristics as those of a mechanical music box.

In the embodiment of the invention described herein, the control logic is directly implemented without the use of microprocessors and the like. The direct logic implementation simplifies the circuit embodiment and allows an entire synthesizer (excluding the audio transducer) to be fabricated on a single semi¬ conductor chip. The chips may be produced in large quantities to provide low cost music synthesizers which produce music of surprisingly high tone quality. The invention is therefore ideally suited for such applica¬ tion as electronic music boxes and the like.

Another aspect of the invention is that only one note is attacked at any one time. This provides two major advantages. Firstly, this fits well with economi- zation of structure, requiring only a single resistive ladder for the three tone generators. Secondly, this enhances the similarity of the tone quality to that of the music box, since a mechanical music box typically strikes only one note at a time to avoid overloading the spring.

Referring to Figure 1, the general block diagram for the preferred embodiment of the present invention is disclosed. A clock generator is provided for generating several clock trains of different fre¬ quencies, namely 30 hz, 120 hz, 240 hz and 250 Khz. The circuitry for controlling the operation of the three tone generators 200, 300 and 400 is shown in a general sense as controller 150. Demultiplexers 201, 202 and 203 couple the tone generators to the attenuator bank 205. After passing through the -attenuator bank 205, the tone generator outputs are coupled to amplifier 600, which drives the audio transducer 700.

As will be discussed in more detail hereafter, the rest interval counter receives a series of rest interval data, which define the time interval between successive enablements of the tone generators. It is contemplated that this rest interval not be a constant period of time, but rather a variable parameter which may be used in the programming of a series of notes to produce a tune.

Frequency information is provided to all tone generators, and when a tone generator is enabled by the controller, that tone generator commences generation of a tone of that frequency. Generation of a particular tone by a tone generator continues until that generator is reenabled to generate another tone. Means are pro¬ vided for sequential enablement of the tone generators.

The demultiplexers and attenuator bank are used to provide an amplitude envelope to the generated tones by sequencing a generated tone signal through a plurality of resistors of different values. A steady state resistive level is achieved after approximately one-half second. By appropriate selection of the resistor values, the musical effect created by the synthesizer may be selected.

Referring now to Figures 2a and 2b, the pre- ferred embodiment of the controller and clock circuit is disclosed. Functionally, control of the circuit is achieved through the direct logic implementation shown. Of course, alternate embodiments utilizing programmable microprocessor or computer elements may be readily implemented.

Enclosed within phantom line 100 are the circuit elements comprising the clock circuit. NOR gate 102 and inverter sections 104 and 106 are coupled together with 47 Kohm resistor 111, 10 Kohm resistor 113 and 68 picofarad capacitor 115 to form a 250 Khz oscil¬ lator with output on line 118. This 250 Khz oscillator output is coupled to frequency divider 120 for dividing the 250 Khz signal into additional clock frequencies at 30 hz, 120 hz and 240 hz. Divider 120 comprises a counter in the preferred embodiment. Of course, other techniques for generating the clock trains are well known in the art, and could readily be substituted for the disclosed clock circuit. Also, the second input of NOR gate 102 is coupled to the Q terminal of latch 680 (shown in Figure 2d). This allows the oscillator to draw no quiescent current while the circuit is in the idle state, which is a characteristic of CMOS LSI Techniques. Referring to Figure 2a, rest interval coun¬ ter 125 receives a 30-hz clock pulse from the clock circuit, and a six bit digital input word at terminals J0-J5. This input word is used to define a "rest" time interval, and, in the disclosed embodiment, is received from memory 870 (discussed more fully hereinafter). Rest counter 125 is a presettable synchronous down counter. The value of the input "rest" word at ter¬ minals J0-J5 of counter 125 provides the presettable initial value of the counter. When the count reaches zero, the "CO" output of counter 120 goes low, and remains low for^' one full clock period. The "CO" output is coupled to the "SPE" terminal which causes the data at the "J" terminals to be forced into counter 125 and the counter recycled. The "CO" terminal of counter 125 is also coupled to counter 130 which is utilized as the circuit operation sequencer. When terminal "CO" of rest inter¬ val counter 125 goes low, signalling the expiration of the rest interval, sequencer counter 130 is initiated. Thus, it may be seen that the higher the value of the digital input word to counter 126, the longer the time interval required for the counter to cycle to the zero state. Counter 130 is a three bit counter with decoded outputs, functioning in the manner of the CD4022B type counter. The decoded outputs of the counter are normally low and go high at their respective decoded time slot, each decoded output remaining high for one full clock cycle.

The outputs 131-136 of counter 130 are used to sequentially initiate certain of the functions of the circuit as illustrated in the logic flow chart of Figure 3, discussed in detail hereinbelow. For example, output 131 is used to provide an enable pulse to counter 140 which is operative to select the tone' generator to be next enabled. Output 131 is also used to provide an instruction to provide another rest interval word to the rest interval counter 125, and another frequency data word to the tone generators. Specifically, output 131 provides a clock pulse to counter 138, increasing incrementally the digital state of the outputs Q1-Q8. The outputs of counter 138, toggled by the signal at output 131, are used to sequentially define the memory address from which the particular digital rest and tone information is to be retrieved, in a manner discussed hereafter. The retrieved rest interval data is presented to the "J" terminals of counter 125. As will be discussed in more detail hereinbelow, the frequency data is presented to tone generator latches 200, 300 and 400.

Referring now to Figures 2a and 2b, the manner in which the tone information and rest information is provided will now be discussed. Output 131 of sequence counter 130 toggles counter 138, whose output terminals Q]_ - Q_Q are coupled to the main read only memory ("ROM") 800 and provide the memory address location (at termi¬ nals Ag - A7) whose contents are provided at output terminals OQ - O7 of ROM 800. Thus, each time the counter 138 is clocked, the state of the counter incre¬ mentally increases to define a new memory location to be accessed.

OR gate 139 drives the "R" (reset) terminal of counter 138, and provides a reset signal which is opera¬ tive to initialize the state of counter 138 and hence the music synthesizer. The reset pulse is initiated either by a reset pulse generated by the operator, as by a switch, or by an "end" pulse derived from the time information, as is known in the prior art discussed previously, and hence not fully described herein.

The contents of each addressed memory location comprise an eight bit digital word. Bits at 0ø - O4 comprise another memory address used as a "look up table" locator, used to locate a digital word in ROM 870 which is used to define the tone. Similarly, bits O5 - O7 comprise a locator for "looking up" a digital word in ROM 870 which defines a rest interval.

Since the locator for the tone information is a five bit digital word, there are 32 possible locations from which tone information may be accessed in ROM 870. Two of these codes are reserved, one for silence (provid¬ ing N = 0 to tone generator) and one for tune end. Simi¬ larly, use of the three bit locator for the rest informa¬ tion allows eight, different locations in ROM 870 to access rest interval information. It is another aspect of this invention that the tones generated need not be incremental, but rather that any note or rest interval may be stored in ROM 870, so long as it is defineable by the eight bit output On - O7 of ROM 870. It is readily apparent that the number of possible tones and rest intervals may be adjusted by providing a larger memory by allocating more or less bits of the output of ROM 800 to tone information or rest information, as the case may be.

JOΛPI V-IPO, Referring to Figure 2A, it is apparent that, so long as either terminal 133 or 134 of counter 130 is "high," the output of OR gate 142 will be "high," and consequently that also of OR gate 144. The output of gate 144 is coupled to the control terminals SA and SB of data selector 840. Selector 940 functions in the manner of a type CD4081 unit. Where the output of gate 144 is high, at point Z (Figure 2b), NOR gate 818 inverts the "high" signal so that a "low" state exists at terminal "SA" of selector 840, thereby selecting and activating terminals Bø - B3 of the selector. Hence, in this state the digital word at output terminals Zø - Z3, together with the digital state at terminal A4 of ROM 870, supplied from terminal O4 of ROM 800 through OR gate 815, comprises the locator address from ROM 870 at which the tone determining word is located, and provided at output terminals Nn - N7 of ROM 870.

Similarly, when the logic state at point Z is "low," i.e., when terminals 133, 134 and 135 of counter 130 are' "low," the Ag - A_ terminals of selector 870 are activated, and the digital word at the output terminals 0ø - O7 of ROM 870 comprises rest interval information. It has been found that six bits of information is adequate to define the rest interval data for a music box synthesizer, and accordingly only six bits of information are provided to rest counter 125, shown in Figure 2A. ^* Eight bits of information are utilized with respect to the tone information supplied via N - N2 to latches 200, 300 and 400.

Terminal 131 of sequencer counter 130 is coupled to tone generator selector counter 140 as its clock enable input. The function and operation of counter 140 is one aspect of the present invention, which provides polyphonic tone generation without additional bits to define each tone duration. Counter

^"BURET

OΛ.PI 140 is operative to select the particular tone generator to be enabled for generating the next frequency value. The outputs of this counter are each coupled respec¬ tively to input terminals of AND gates 162, 163 and 164. The other input terminals of these AND gates are coupled to terminal 135 of sequencer counter 130. Accordingly, when both the respective output from selector counter 140 and terminal 131 of sequencer counter 130 are "high" a "high" signal will appear at the respective AND gate output. The AND gate outputs 202, 300 and 402 are each coupled respectively to the "CK" enable terminal of latches 200, 300 and 400, and cause the selected latch 200, 300 and 400 to load the new note value defined by the digital word ø - 7. At this instant, the data selector 840 is in. the tone interval mode, i.e. by selecting the "B" terminals of selector 840.

Referring now to Figures 2c and 2d, the pre¬ ferred embodiment of the tone generators will now be described. Since the tone generator circuits are indentical, only one will be described in detail. Eight bit latch 200 performs the well known function of pro¬ viding at its output terminals the logic levels which are presented at the corresponding input terminals when the latch is strobed by a clock pulse provided on line 202. The function of the latch used on the disclosed embodiment is of the type MMy4C374 latch.

Each of the latches 200, 300 and 400 are provided with common input signals on lines Nø - N7. The digital word defined by the state of Nø - N7 com¬ prises the information which determines the frequency of the signal to be generated. Each latch receives a separate trigger pulse on lines 202, 302 and 402 respec¬ tively. Upon receipt of a clock pulse by a latch, the logic states on input lines Nø - N7 are produced and held at the output terminals Qg - Q-j of the respective latch until receipt of the next clock pulse.

The output terminals of latch 200 are connected to eight bit down counter 220 via lines 211-218; the counter 220 operates in a function similar to that of CD40103 type counter units. The eight bit down counters 220, 320 and 420 each receive a clock signal of 250 Khz from the clock pulse generator. The counter 220 counts down from the digital value of the logic word at the input terminals "J0"-"J7" at a rate determined by the clock. When the counter reaches zero, a pulse is generated at the "CO" output terminal of the counter. The counter is then automatically recycled. By changing the value of the digital word expressed by the logic states at the terminals of J0-J7 of the counter 220, the frequency of the counter recycling may be varied; the higher the value of the digital word, the longer the cycle period and the lower the frequency of recycling of the counter. Terminal "CO" of the counter 220 is coupled to input "C" of flip-flop gate 230 via line 222. Each pulse on line 222 produces a change of state of the flip- flop output, causing a square-wave output at terminal 232 of flip-flop 230.

The flip-flop output at terminal 232 is connected to the input of demultiplexers 240 via lines 234 and 250. Demultiplexers 240 and 250 are used as "one of eight" data selectors, i.e. a three bit control word is used to select one of eight output terminals to be turned "on" and to which an input signal is coupled. In the embodiment of Figure 2C, two demultiplexers are used together to obtain the functional equivalent of a "one of sixteen" data selector. Whether one uses two "one of eight" selectors or one "one of sixteen"

^URET

O PI selectors is a matter of circuit design choice. The "one of eight" demultiplexers in the disclosed embodi¬ ment are functionally of the type CD 4051 units.

Each of the demultiplexer output terminals is coupled to the mixing amplifier circuit 600 via a resistor. The demultiplexers provide the capability of selecting the particular resistance through which the flip-flop 230 output is coupled to the mixing amplifier, and further provides means by which the resistance value may be sequentially varied through selection of dif¬ ferent resistors.

Demultiplexers 240 and 250 are controlled by four bit counter 260. Counter 260 receives a 30-hz^* clock circuit, and a reset signal on line 202 from AND gate 162. Output terminals 262, 263, 264 and 265 are each respectively coupled to the A, B, C and "disable" demultiplexer terminals of demultiplexers 240 and 250.

Inverter 280 couples terminals 265 of counter 260 to the "disable" terminal of selector 240. The .counter 260 output at terminal 265 thus operates to enable either selector 240 or 250, in dependence upon the logic state at terminal 265.

NAND gate 270 has its four inputs 282, 283, 284 and 285 coupled to terminals 265, 264, 263 and 262, respectively of the multiplexer counter 260. The output terminal 288 of NAND gate 270 is coupled to the disable "CE" terminal 269 of counter 260. When all inputs to the NAND are "high," resulting in the inverted "low" state at the output 288 of the NAND, the counter 260 operation is disabled and, the logic states at output terminals 262-265 are held until counter 260 is reset.

Until the logic state at terminal 265 of counter 260 reaches the "one" state, a logic "zero" will appear at the "disable" terminal of demultiplexer 240,

O PI due to operation of logic inverter 280. Demultiplexer 240 will therefore be disabled. Conversely, terminal 265 of counter 260 is coupled directly to the disable terminal of demultiplexer 250, so that until the logic state at terminal 265 is "high," demultiplexer 250 will be operative.

As the counter 260 proceeds through a cycle, the outputs 251-258 of multiplexer 250 are sequentially selected. Since counter 260 is being clocked by a 20-hz signal, the elapsed time required for the counter to cycle from a "0000" output to a "1111" output is about 16/30 seconds; each output 250-258 is selected for 1/15 second time interval. When the most significant bit at terminal 265 reaches the logical "1" state, multiplexer 250 will be disabled, and multiplexer 240 will then be sequentially selected. The entire cycle, sequencing through terminals 250-258 and 241-248 nominally consumes about 16/30 seconds.

A bank of sixteen resistors R0-R15 is employed to couple the sixteen output terminals 241-248 and 251-258 of multiplexers 240 and 250 to mixing amplifier circuit 600 via resistors R0-R15. The resistor values are selected to provide the desired attack and decay envelope of the tones, to produce an effect on the tone such as a plucked tine, or a calliope effect, or the like. A typical range is 30 Koh s to 400 Koh s.

In order to produce a music box effect, a resistor bank whose resistance values are selected so that the relative peak-to-peak amplitudes of the signal are as shown in the following table have been found to work well: Resistor: *o ^Ri R2 ^R3 R ^5 ^R6 ^R7

Relative signal 1. .72 .5 .45 .4 .32 .18 .17

Amplitude:

Resistor: *8 R₉ Rio *n *12 Rl3 R₁₄

Relative signal .3 .2 .17 .13 .13 .1 .08

Amplitude:

Table 1

-One aspect of the present invention is that the three tone generators are controlled such that only one tone generator output is applied to any resistor R0-R14 at any given time. The circuit logic operates the enablement of the three tone generators in a sequen¬ tial fashion, with a minimum 1/30 second delay between sequential enablement, so that a single resistor bank R0-R14 may be shared by the three tone generators. This allows a substantial saving in the number of resistive circuit elements needed for the circuit implementation and provides inherent matching of the relative ampli¬ tudes of the three tone generators.

Since the demultiplexing operation consumes only about one-half second in the disclosed embodiment, and the tone duration may be considerably longer, the tone generator 200 output may be applied to the final resistor Rl5 for an indefinite time interval. Conse¬ quently, to avoid the outputs for all three tone gen¬ erators being coupled through the same resistor Rl5₇ three resistors R15 are utilized, one for each tone generator.

_. OMPI Referring now to the mixing amplifier circuit enclosed within phantom line 600 in Figure 2C, NOR gates 630 and 660 are biased in a linear mode for opera¬ tion as an inverting amplifier. Gates 620 and 660 in the preferred embodiment function in the manner of CD4025B type units. The circuit is ideally suited for implementation in the CMOS type of LSI chip, for two reasons, firstly because the circuit is designed to draw no quiescent current when in the idle state and secondly, because the CMOS implementation allows the amplifier to be biased in a linear mode.. The fact that no current is drawn when the current is idle further provides the capability of implementing the circuit without a power on/off switch. With the CMOS technique, even though a circuit voltage is applied to the circuit elements at all times, since no current is drawn when, the circuit is idle, no power will be dissipated either. Transducer 700 is the audio transducer; in the preferred embodiment a piezoelectric raonomorph is utilized. Connection of gates 620 and 660 across transducer 700 produces a possible voltage swing of 18 volts peak to peak, from a 9 volt power source (i.e. a battery) . The ability to use such a low cost and hitherto low performing audio transducer is yet another aspect of the present invention. By utilization of the polyphonic techniques described about, the surprising result of high tonal quality with a bender transducer is achieved.

Input terminals 631 and 661 of gates 630 and 660 and gates 620 and 622 coupled to an initialization and shut-off logic gate 680.

Feedback resistor 635 couples the input and output of gate 630. Similarly, feedback resistor 665 couples the input and output of gate 660. Resistor 640

-_BU EAIT

OMPI _, coupling the gate 630 output to the gate 660 input is 22 Kohms in the preferred embodiment, while resis¬ tors 635 and 665 are 12 Kohms, respectively. The driving voltage for the transducer 700 is developed between the output of gate 630 and the output of gate 660.

Referring to Figure 2D, latch 680 is operative to activate the music synthesizer circuitry. The "Q" terminal of the latch, when "high," causes the circuit to be held in a quiescent mode. This occurs since the high Q state causes NOR gates 620, 622 and 102 to have low output states, thereby turning off the amplifier 600 and oscillator 100. Switch 682 couples the "set" terminal of latch 680 to ground, while the "reset." ^' Referring now to the logic flow diagram of

Figure 3, the logic operation of the circuit controller will now be described. Upon receipt of a "reset" instruction, either by a circuit "on" switch, or a "tune repeat" instruction, the circuit will be initialized at step 15.

Next, at decision point 20, the rest interval counter 125 is tested to determine if it is zero, i.e., that the rest interval has expired. If "no," the counter 125 is decremented, and operation delayed 1/30 second at steps 50 and 55 before decisions 20 is repeated.

If the rest interval has expired at decision point 20, then the program counter 130 is advanced by one count at step 25. At decision point 30, a determi- nation is made whether the end of the tune has been reached. If "yes," the circuit is shut off or the tune repeated at step 38, depending upon the circuit mode. If "not," then a new rest value is loaded into the next available latch at step 40, and the attenuator counter is reset at step 45.

_0MPI

A vr.po Next, at steps 50 and 55, the rest counter is decremented and circuit operation delayed for 1/30 of a second prior to repeating decision 20.

Referring now to Figure 4, the operation of a tone generator is disclosed by the logic flow diagram. Each tone generator operates continuously once ini¬ tiated. The operation shown in Figure 4 is after the tone generator has been initiated.

Step 850 is a 4-microsecond delay, i.e. one period of the 250 Khz clock to down counters 220, 320 and 420 -and results from the operation of the down counter. At step 860 the state of the down counter decrements, and at step 870 the state is tested to determine whether it is zero. If "no," then the next step is 900, where the state of the 30 hz clock signal to counter 260 is tested. If the state of the down counter is zero, then at step 880 the down counter 220 is reloaded from latch 200, and flip-flop 230 is toggled.

At step 900, the state of the 30 hz clock signal to counter 260 is tested. If not at the edge of the clock pulse, the logic flow is repeated commencing at step 860. If at the edge of the clock pulse, the attenuator counter 260 is incremented (the state will be held when 1, 1, 1, 1 is reached), and the logic flow is repeated commencing at step 850.

From the foregoing description, it is apparent that the tone generator will continue to generate a square wave signal of a particular frequency until the state of the latch is changed, which will change the frequency of operation of the flip-flop. The other two tone generators operate in a like manner. Hence it will be seen that all three tone generators will be operating simultaneously, producing a polyphonic signal composed

OΛiPI of three square wave components, each of selected fre¬ quency. While a logic flow chart is used to illustrate the operation of the circuit, it should be borne in mind that the chart is illustrative only, as the circuit operation in the disclosed embodiment is directly ^* implemented without any computer elements such as a microprocessor.

The circuit is not limited to a one or two octave note range. Rather, in the embodiment shown, the circuit may generate any one of 32 notes, and can readily be adapted to generate a -higher number of notes or to generate a wider range of notes by using larger, higher bit circuit elements.

With the polyphonic music generation, and the capability of providing an amplitude envelope, a music generator of exceptional tonal quality and range is obtained.

While the disclosed embodiment is of discrete components for clarify of description it should be recognized that the invention is ideally suited for fabrication in an LSI chip, and in particular by CMOS techniques. LSI techniques permit almost infinite variations on actual circuit implementations. For example, only one memory would be needed, as different areas of the memory would be accessed to provide the tone information and the rest interval information.

Figures 5 and 6 illustrate two embodiments which utilize this aspect of the invention. As is well known, piezoelectric transducer 900 generally comprises a metal (typically brass) disc 910 to which is bonded a piezoelectric ceramic disc 920. The brass disc is mounted (for example at the edges thereof) in order that the transducer disc may vibrate in accordance with the received electrical excitation to produce an audio

OIΛPI signal. The LSI chip or die 930 will be fabricated of a small size in relation to the physical dimensions of the transducer. Mounting the die directly on the transducer provides many advantages, including reduction of physi¬ cal size of the synthesizer apparatus. The die may be located as shown in Figure 5, i.e., such that part of the die 930 is located over ceramic disc 920 and part over the brass disc 910. The die is bonded by an appropriate bonding agent as is well known in the art. For the embodiment disclosed, this bonding agent is not electrically conductive. Electrical connection to die 930 is accomplished via annular plastic ring 940 which encircles die 930. Ring 940 also is bonded to the transducer, and the top surface thereof is provided with a plurality of metallized pads 942. Pads 942 provide surfaces for die bonding wire leads from die 930 and for soldering wire leads to the power source, operation controls and to ceramic 920 and brass 910 surfaces. While only four pads are illustrated, the number of pads is selected to accommodate the number of required out¬ side connections.

Figures 6A and 6B illustrate another embodi¬ ment of the invention. In this embodiment, plastic member 950 is fabricated with a recessed area 960 of substantially reduced thickness to form an indentation in which LSI die 955 may be disposed. The depth of the recessed area is selected so that no part of die 955 protrudes above the upper surface 952 of member 950, as shown in Figure 6A. Two indentations 962 are formed in part of member 950 surrounding the recessed area 960 to provide areas for mounting terminals 964 which include spring-like end members. Wire leads providing elec¬ trical contact to the LSI circuit of die 955 are brought out from die 955 to a plurality of terminals 965 and

EΛE

OMPI

Sλ,-_^ vripo bonded or soldered thereto. Terminals 965 are post-type members which are disposed through the reduced thickness of member 950 to the opposite side of member 950.

With the die 955 bonded into the recessed area 960, member 950 is inverted and bonded to the trans¬ ducer 900 as shown in Figure 6B. Member 950 is disposed so that one of the spring-like members 964 makes elec¬ trical contact with the surface of ceramic disc 920 and the other spring-like member of terminals 964 thus elimi¬ nate the need for wire leads between die 955 and the respective surfaces. Wire leads from the terminals 965 are then brought out to the operator controls (desig¬ nated as "A" and "B"), the power source (designated as "V"), and to ground. The bonding agent protects die 955 and the delicate wire bond leads located in the recessed area from dislocation. Plastic member 950 acts as a protective coating structure encapsulating the die and interior wire leads.

Numerous variations on the disclosed technique for mounting the LSI die to the transducer will be readily apparent to those skilled in the art.

Thus, while a preferred embodiment of the present invention has been described hereinabove, it is intended that all matter contained in the above descrip¬ tion and shown in the accompanying drawings be inter¬ preted as illustrative and not in a limiting sense and that all modifications, constructions and arrangements which fall within the scope and spirit of the invention may be made.

OMPI

Claims

WHAT IS CLAIMED IS:

1. A polyphonic audio synthesizer, operative to generate audio signals from digital representations thereof, comprising: at least two audio generators, each for generating signals from such digital representations; audio transducer means coupled to said generators for generating audio signals from said signals; and means for varying the level of said audio signals, said means adapted to provide more than one audio level for each generated signal.

2. The synthesizer of Claim 1 wherein said level varying means comprises variable attenuator means coupling each of said tone generators to said audio transducer.

3. The synthesizer of Claim 2 wherein said variable attenuator means includes a plurality of resistive elements.

4. The synthesizer of Claim 1 further com¬ prising controller means for controlling the operation of the tone generators, such that said generators do not simultaneously initiate generation of audio signals.

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5. The synthesizer of Claim 4 further com¬ prising fixed attenuator means coupled one to each tone generator and controlled by said controller for selec¬ tively attenuating the output signal thereof.

6. The synthesizer of Claim 4 wherein said controller means is adapted to sequentially enable the respective tone generators with a new digital represen- , tation so that such newly enabled generator commences generation of an audio signal from said new digital representation.

7. The synthesizer of Claim 6 wherein said controller means is responsive to a first input related to a time interval between successive enablement of said tone generators. •

8. The synthesizer of Claim 7 wherein said first input is determined in accordance with a data input which defines said time interval.

9. The synthesizer of Claim 8 wherein said data input is comprised of digital representations.

10. The synthesizer of Claim 8 wherein said time interval is a variable parameter, and a plurality of time intervals are preselected for determining the respective time intervals between successive enablement of the tone generators.

11. A polyphonic audio generator, operative to generate audio signals from a plurality of digital representations thereof, comprising: at least two tone generators respon¬ sive to such digital representations for generating signals; control means for controlling the tone generators, operative to sequentially enable said tone generators to generate said signals; and audio transducer means coupled to said tone generators for generating audio signals from said signals.

12. The generator of Claim 11 further com¬ prising means for determining the time interval between sequential enablement of said tone generators by the control means, said control means being responsive to said interval determining means.

13. The generator of Claim 12 wherein said time interval comprises a variable parameter.

14. The generator of Claim 13 wherein said time interval is predetermined and selected from a plurality of different intervals.

15. The generator of Claim 14 wherein said time interval is determined from digital representations thereof.

16. The generator of Claim 15 wherein said digital representations of said time interval are retrieved from memory means.

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17. A polyphonic music generator, operative to generate audio signals from digital representations thereof, comprising: at least two generators, each for generating signals from such digital representations and each adapted to generate signals from such digital repre¬ sentations until enabled with other digital representations; audio transducer means coupled to said generators for generating audio signals from said signals; means for varying the level of said audio signals, said means adapted to pro¬ vide more than one audio level for each generated signal; controller means for controlling the operation of said generators and respon¬ sive to data inputs defining rest inter¬ vals, said controller means operative to enable sequentially each generator with successive digital representations in time overlapping manner, the time interval between each sequential enablement defined by a preselected rest interval; whereby said synthesizer is operable -to sequentially generate audio signals from preselected digital representations in a time overlap manner, and successive audio signals are generated in accordance with a succession of rest interval data.

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18. An electronic music box, operative to generate audio signals from digital representations thereof and thereby to generate a tune, comprising: at least one audio generator for generating signals from such digital representations; audio transducer means coupled to said tone generators for generating audio signals from said signals produced by said generator; and means for varying the level of said audio signals, said means adapted to provide more than one audio level for each generated audio signal.

19. The electronic music box of Claim 18 wherein said means for varying the level of said audio signals comprises variable attenuator means.

20. The electronic music box of Claim 19 wherein said variable attenuator means is adapted to sequence through a plurality of attenuation levels upon commencement of generation of a particular audio signal.

21. The electronic music box of Claim 20 wherein said variable attenuator sequences through said attenuation levels within a preselected time interval.

22. The electronic music box of Claim 18 wherein said transducer means comprises a piezoelectric transducer, said generator and level varying means are fabricated on an integrated circuit chip, and said chip is fastened to said transducer.

23.^* The electronic music box of Claim 22 wherein said chip is bonded to said transducer.

24. The electronic music box of Claim 22 wherein said chip is disposed within a recessed area of a block of insulating material, and said block is fastened to said transducer.