Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
  • H01L21/68771—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by supporting more than one semiconductor substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
  • H01L21/6833—Details of electrostatic chucks
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
  • H02N13/00—Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect

Definitions

• a substrate is pro ⁇ Devoid of the photoresist material which thus functions as a stencil.
• the substrate (which may be con ⁇ ductive, semiconductive or insulative) is then mounted on a support and exposed in a high vacuum to the ion beam which is controlled to etch or mill away the exposed areas of the substrate to a desired depth.
• a voltage source is connected between the support and the substrate or wafer to be treated.
• One embodiment of the invention which achieves these objects, and other objects apparent in the following des ⁇ cription and in the practice of the invention, may be sum- marily and generally characterized as a substrate clamp comprising a thermally conductive support, multi-electrode capacitor means incorporated in the support and having at least two terminals for connection to a voltage source, and electrically insulative, thermally conductive means oriented to insulate said capacitor from said substrate, while providing * thermal conductivity between them.
• a second embodiment of the invention relates to a substrate clamp having a thermally conductive support and electric field generating capacitance with at least one electrode associated with the support, and particularly to an improvement thereto comprising a compressible layer between the capacitance and the substrate to be clamped for providing improved thermal conductivity between them.
• a further feature of this embodiment of the invention com- prises a substantially planar substrate carrier having a plurality of apertures, each for laterally constraining a substrate, the carrier being configured for attachment to the support in such manner as to bring the substrates into proximity with the support and mask the areas of the sup ⁇ port not covered by the substrates.
• a still further fea- ture involves a pneumatic release system in which gas unde pressure is applied via a manifold in the carrier to the clamped substrates to release them.
• FIGURE 1 is a schematic elevational view illustrating the electrostatic clamp of the invention in an ion beam high vacuum system, it being understood that the invention will serve in other applications as well;
• FIGURE 2 is a schematic plan view of the electrostati clamp on an enlarged scale;
• FIGURE 3 is a schematic elevational and partly sectio al view of the clamp with a substrate mounted thereon, on a still larger scale;
• FIGURE 4 is an enlarged cross-sectional schematic fragmentary view of the hold down plate of a second embodi ment;
• FIGURE 5 is a plan view of the second embodiment; and FIGURE 6 is an exploded and cross-sectional view show ing the substrate carrier of FIGURE 5 in section along lines 6-6 of FIGURE 5, together with substrates and the hold down plate of FIGURE 5.
• FIGURES 1-3 the system schematically illus ⁇ trated therein comprises an ion beam etching system which includes an ion beam source 1 for generating an ion beam 2 which is incident on a substrate 3 of semiconductive material such as silicon.
• the substrate 3 is mounted on a support 4 which includes an electrostatic plate 5 and connected thereto and in good thermal contact therewith, a water-cooled plate or jacket 6.
• a printed circuit capacitor 7 having electrical terminals 8 and 9 which are connected via respective leads 10 and 11 to a source of DC voltage, V.
• FIGURE 1 illustrates the electrostatic clamp in an ion beam etching function
• the source 1 including the usual grid structures, e.g., electron suppression and ion accel ⁇ eration grids, as well as an exit grid, neutralization grid and any other required beam controlling electrodes.
• the source 1 also includes an anode and hot cathode and may include a magnetic field for imparting epicycloidic trajec ⁇ tories to the emitted electrons.
• the ion source 1 also includes a source of gas such as neon or argon, and the entire system is enclosed within a high vacuum chamber.
• a source of gas such as neon or argon
• Examples of ion beam etching sys- terns are found in microetch systems sold by the assignee herein, Veeco Instruments Inc. (ion source 0313-901, power supply 0313-310; automatic pumping station VE 747).
• FIGURES 2 and 3 Further details of the printed capacitor 7 are shown in FIGURES 2 and 3. As shown therein the capacitor is of the printed circuit interdigital type and includes a first set of electrodes 8A connected to capacitor terminal 8 by way of a peripheral arcuate conductor segment 8B. Similarly, the oppositely polarized electrodes 9A are interdigitated with the plates 8A, and are connected by a printed arcuate segment 9B to capacitor terminal 9.
• a suitable material for forming the conductor pattern of the capacitor is Eccocoat CC2 silver ink spray sold by the Emerson and Cuming Company.
• the printed circuit pattern is in the order of about 1 mil thickness.
• the printed circuit pattern is sandwiched between a pair of layers 12A and 12B, the former being coated on the outer surface of plate 5.
• Each of the layers 12A and 12B is, in the exemplary embodiment, of a thickness of about 4 mils and is comprised of a compressibl electrically insulative, thermally conductive material.
• the preferred composition is a thermally conductive RTV silicone such as is marketed under the designation Eccosil 4952, sold by the Emerson and Cuming Company.
• the plate 5 is secured both mech ⁇ anically and with good thermal conductivity, to the water- cooled plate 6.
• the printed circuit capacitor 7 is energized to create an electrostatic field which brings substrate 3 into good thermal contact with outer layer 12B.
• a voltage appropriate in the illustrated embodiment for achieving the requisite contact is in the neighborhood of about 1.5 kilovolts.
• the voltage source which sup ⁇ plies the charge to capacitor 7 may be switched by use of switch S such that opening the switch disconnects the voltage source from the capacitor and discharges the latter thereby permitting release of the wafer being treated.
• the support plate 5 may be fabricated of a thermally conductive electrical insu ⁇ lator such as alumina on which the capacitor 7 is deposited as by silk screening or vacuum evaporation.
• a thermally conductive electrical insu ⁇ lator such as alumina on which the capacitor 7 is deposited as by silk screening or vacuum evaporation.
• the need for layer 12A can thus be obviated.
• the layer 12B can also be excluded.
• the substrates which may be held in place by the electrostatic clamp may be conductive, semi-conductive, or electrically polarizable insulative devices. It should also be understood that one of the terminals of the capaci ⁇ tor may be a grounded conductive surface or joint.
• the system described above employs compressible means between the electrostatic field generating capacitor and the clamped object, illustratively a layer of silicone rubber. It has been found that the closer clamping which is achieved with such a compressible layer, provides im- proved thermal conductivity between the substrate and the heat sink, a key requirement in many semiconductor fabri ⁇ cating processes.
• FIGURES 4-6 An alternative and preferred embodiment which provides improved thermal conductivity between the substrate and the heat sink is illustrated in FIGURES 4-6.
• Other improve ⁇ ments involve the structure of the hold down plate assembly which incorporates the capacitor, and a substrate carrier which transports the substrates, brings them into the active region of the hold down plate, serves to mask the hold down plate regions not covered by the substrates, and incorporates a manifold to facilitate pneumatic re ⁇ lease of the substrates.
• a support plate 15 is fabricated of a thermally conductive electrical insulator such as alumina on which the capacitor electrodes 18A, 19A are deposited as by silk screening or vacuum evaporation. Covering the printed capacitor is a hard overglaze 20 which may be, for example, porcelain. Covering the over ⁇ glaze is a compressible resilient layer 21, illustratively the RTV silicone previously described.
• the capacitor 18A, 19A takes the form previously described, and is energized as previously indicated.
• One of the terminals of the capacitor may be a grounded con ⁇ ductive surface or point, and one electrode of the capa ⁇ citor may be remote from the support.
• a disc-shaped carrier 30, FIGURES 5 and 6 For transporting the substrates to the electrostatic clamp a disc-shaped carrier 30, FIGURES 5 and 6, is employ It includes six peripheral apertures 31 and a central aper ture 32 for holding the substrates to be clamped.
• Each aperture wall includes a flange 33 for supportin the substrate rim, a conical, outwardly flaring section
• channels 36 each interconnecting the section 34B of center aperture 32 with the section 34B of a respective peripheral aperture 31.
• an inlet plenum 37 which communicates with main channel 35 and has an inlet port 38. The latter is threaded to receive a threaded plug (not shown) .
• carrier 30, loaded with substrates is clamped to the substrate holder 14 by means of a suitable mechanical clamp.
• a source of gas under pressure is applied to port 38.
• the gas traverses inlet chamber 37, channel 35 and branches 36 to the edges of the loaded wafers where it acts to loosen them from the substrate holder.
• the solid section of carrier 30 protects the hold down coating 21 from the effects of the treatment process; e.g., milling, etching or deposition.
• clamp 14 and carrier 30 are roughly 10 inches in diameter.
• the alumina layer of clamp 14 is 0.312 inches thick and consists of high density 99% pure; the electrodes 18A, 19A are 3-5 microns thick and the overglaze 18A is roughly .002-.004 inches.
• Resilient coat 21 is .015 inches thick.
• Carrier 30 is approximately 1/4 inch thick and fabricated from 304 stain- less steel. -10-

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Drying Of Semiconductors (AREA)
• Formation Of Insulating Films (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=27128118

Family Applications (1)

Country Status (4)

Cited By (29)

Families Citing this family (2)

Citations (7)

• 1978
  • 1978-12-15 IL IL56224A patent/IL56224A/xx unknown
• 1979
  • 1979-01-05 WO PCT/US1979/000007 patent/WO1979000510A1/en unknown
  • 1979-01-05 JP JP50034379A patent/JPS55500049A/ja active Pending
  • 1979-08-13 EP EP79900156A patent/EP0007918A1/en not_active Ceased

Patent Citations (7)

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