UST944001I4 - - Google Patents

Download PDF

Info

Publication number
UST944001I4
UST944001I4 US50847174A UST944001I4 US T944001 I4 UST944001 I4 US T944001I4 US 50847174 A US50847174 A US 50847174A US T944001 I4 UST944001 I4 US T944001I4
Authority
US
Grant status
Grant
Patent type
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
UST944001I4 1974-06-13 1974-09-23 Pending UST944001I4 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US47906974 true 1974-06-13 1974-06-13
UST944001I4 UST944001I4 (en) 1974-06-13 1974-09-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UST944001I4 UST944001I4 (en) 1974-06-13 1974-09-23

Publications (1)

Publication Number Publication Date
UST944001I4 true UST944001I4 (en) 1976-03-02

Family

ID=27046117

Family Applications (1)

Application Number Title Priority Date Filing Date
UST944001I4 Pending UST944001I4 (en) 1974-06-13 1974-09-23

Country Status (1)

Country Link
US (1) UST944001I4 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5113352A (en) * 1989-06-20 1992-05-12 Digital Equipment Corporation Integrating the logical and physical design of electronically linked objects
US5187671A (en) * 1990-08-24 1993-02-16 Microelectronics And Computer Technology Corporation Automated interconnect routing system
US5202840A (en) * 1990-12-19 1993-04-13 Vlsi Technology, Inc. Method for partitioning of connected circuit components before placement in one or more integrated circuits
US5229953A (en) * 1989-10-13 1993-07-20 Hitachi, Ltd. Method of and apparatus for assigning logic gates to a plurality of hardware components
US5251147A (en) * 1989-06-20 1993-10-05 Digital Equipment Corporation Minimizing the interconnection cost of electronically linked objects
US5282148A (en) * 1989-05-23 1994-01-25 Vlsi Technology, Inc. Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic
US5406497A (en) * 1990-09-05 1995-04-11 Vlsi Technology, Inc. Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler including a cell library
US5416717A (en) * 1989-09-06 1995-05-16 Hitachi, Ltd. Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern
US5461577A (en) * 1987-08-04 1995-10-24 Texas Instruments Incorporated Comprehensive logic circuit layout system
US6345378B1 (en) * 1995-03-23 2002-02-05 Lsi Logic Corporation Synthesis shell generation and use in ASIC design

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461577A (en) * 1987-08-04 1995-10-24 Texas Instruments Incorporated Comprehensive logic circuit layout system
US5282148A (en) * 1989-05-23 1994-01-25 Vlsi Technology, Inc. Method and apparatus for the design and fabrication of integrated circuits employing logic decomposition algorithms for the timing optimization of multilevel logic
US5113352A (en) * 1989-06-20 1992-05-12 Digital Equipment Corporation Integrating the logical and physical design of electronically linked objects
US5251147A (en) * 1989-06-20 1993-10-05 Digital Equipment Corporation Minimizing the interconnection cost of electronically linked objects
US5416717A (en) * 1989-09-06 1995-05-16 Hitachi, Ltd. Circuit simulation method for a circuit realized by an LSI layout pattern based upon a circuit of a logic gate level realized by the layout pattern
US5229953A (en) * 1989-10-13 1993-07-20 Hitachi, Ltd. Method of and apparatus for assigning logic gates to a plurality of hardware components
US5187671A (en) * 1990-08-24 1993-02-16 Microelectronics And Computer Technology Corporation Automated interconnect routing system
US5406497A (en) * 1990-09-05 1995-04-11 Vlsi Technology, Inc. Methods of operating cell libraries and of realizing large scale integrated circuits using a programmed compiler including a cell library
US5202840A (en) * 1990-12-19 1993-04-13 Vlsi Technology, Inc. Method for partitioning of connected circuit components before placement in one or more integrated circuits
US6345378B1 (en) * 1995-03-23 2002-02-05 Lsi Logic Corporation Synthesis shell generation and use in ASIC design

Similar Documents

Publication Publication Date Title
DE2401619C2 (en)
DE2401462C3 (en)
DE2401921C3 (en)
BE830202A (en)
DE2401708B2 (en)
DE2400582C3 (en)
DE2401842B2 (en)
DE2402072C3 (en)
DE2402399C3 (en)
DE2402517C3 (en)
DE2401732B1 (en)
DE2401684C2 (en)
DE2401809C3 (en)
DE2402634B2 (en)
BE525532A (en)
DE2402088C2 (en)
DE2401475C2 (en)
DE2402606C2 (en)
DE2402322B1 (en)
DE2402748C2 (en)
DE2401731B2 (en)
DE2402127C3 (en)
DE2401409C3 (en)
DE2401090A1 (en)
DE2401532B2 (en)