UST926012I4 - UST926012I4 - Google Patents

UST926012I4

Info

Publication number
UST926012I4
UST926012I4 US926012DH UST926012I4 US T926012 I4 UST926012 I4 US T926012I4 US 926012D H US926012D H US 926012DH US T926012 I4 UST926012 I4 US T926012I4
Authority
US
United States
Prior art keywords
queued
processor
instruction
becomes available
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Application granted granted Critical
Publication of UST926012I4 publication Critical patent/UST926012I4/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

A DEVICE IS DISCLOSED WHICH ALLOWS A PROCESSOR TO INITIATE A START 1/0 OPERATION WITHOUT WAITING FOR THE COMPLETION OF THE CONNECTION BETWEEN THE CHANNEL AND THE DESIRED INPUT/OUTPUT (I/0) UNIT. IN THE EVENT THAT THE I/O INTERFACE IS BUSY THE PROCESSOR IS RELEASED AND THE START I/O INSTRUCTION IS QUEUED IN THE CHANNEL UNTIL THE I/O INTERFACE BECOMES AVAILABLE AT WHICH TIME THE START I/O INSTRUCTION IS AGAIN INITATED WITHOUT PROCESSOR INTERACTION. WHENEVER AN I/O INTERFACE BECOMES AVAILABLE, THE

QUEUED INSTRUCTIONS ARE POLLED TO DETERMINE IF ONE HAS BEEN QUEUED FOR THE PARTICULAR UNIT. A PRIORITY MEANS IS INCLUDED WHICH CAUSES THE QUEUED INSTRUCTIONS TO BE REINITIATED IN A FIFO ORDER.
US926012D 1974-02-20 1974-02-20 UST926012I4 Pending UST926012I4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US44423074A 1974-02-20 1974-02-20

Publications (1)

Publication Number Publication Date
UST926012I4 true UST926012I4 (en) 1974-09-03

Family

ID=23764026

Family Applications (1)

Application Number Title Priority Date Filing Date
US926012D Pending UST926012I4 (en) 1974-02-20 1974-02-20 UST926012I4

Country Status (1)

Country Link
US (1) UST926012I4 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546430A (en) 1983-07-13 1985-10-08 Sperry Corporation Control unit busy queuing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546430A (en) 1983-07-13 1985-10-08 Sperry Corporation Control unit busy queuing

Similar Documents

Publication Publication Date Title
JPS52110535A (en) Interface device between cpu and input output bus and cpu
JPS51120636A (en) Input output device processor
UST926012I4 () UST926012I4
FR1263534A (en) Conveyor apparatus comprising a main part and an auxiliary part starting angularly from the first, intended in particular for electroplating machines
CA646597A (en) Gaseous-discharge device and system
CA652997A (en) Device and process for performing arithmetical operations
AU283630B2 (en) Apparatus for deflecting and guiding a descending slab orthe like
CA651139A (en) Pushing and pulling device
ES95935U (en) Device for establishing unión of metal formwork panels (Machine-translation by Google Translate, not legally binding)
AU4085864A (en) Apparatus for deflecting and guiding a descending slab orthe like
CA647298A (en) Emulsifying and extracting apparatus
JPS54127642A (en) Input/output control system
CA638908A (en) Excavating tooth point retaining device
CA678038A (en) Boron oxide-lead oxide etchant and etching process
CA693580A (en) Magnetically-stabilized low pressure arc apparatus and method of operation
CA640683A (en) Catalytic alkylation method and apparatus
CA637281A (en) Oblique cutting plier
AU282166B2 (en) Method and device for taking impressions of teeth
CA636709A (en) Etching process and apparatus
CA661189A (en) Method of and apparatus for verifying the operation of a tape reperforator photoelectrically
CA641313A (en) Refractory brick and process
JPS5251834A (en) Input/output bus switching device
CA692225A (en) Methods and apparatus for sheathing
AU4227764A (en) Method and device for taking impressions of teeth
CA650998A (en) Method and means for pressure casting