USRE42037E1 - Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter - Google Patents

Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter Download PDF

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USRE42037E1
USRE42037E1 US12/426,884 US42688409A USRE42037E US RE42037 E1 USRE42037 E1 US RE42037E1 US 42688409 A US42688409 A US 42688409A US RE42037 E USRE42037 E US RE42037E
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current
sensed current
correction
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Robert Haynes Isham
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Intersil Americas LLC
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40Testing power supplies
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M2001/0003Details of control, feedback and regulation circuits
    • H02M2001/0009Devices and circuits for detecting current in a converter
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00Electricity: power supply or regulation systems
    • Y10S323/907Temperature compensation of semiconductor

Abstract

A current-sensing and correction circuit having programmable temperature compensation circuitry that is incorporated into a pulse width modulation controller of a buck mode DC—DC converter. The front end of the controller contains a sense amplifier, having an input coupled via a current feedback resistor to a common output node of the converter. The impedance of a MOSFET, the current through which is sampled by a sample and hold circuit is controlled by the sense amplifier unit. A sensed current correction circuit is coupled between the sample and hold circuit and the controller, and is operative to supply to the controller a correction current having a deterministic temperature-compensating relationship to the sensed current. The ratio of correction current to sensed current equals a value of one at a predetermined temperature, and has other values at temperatures other than at that temperature.

Description

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the benefit of co-pending U.S. Provisional Patent Application, Serial No. 60/340,324, filed Dec. 14, 2001, entitled: “Continuous Control Temperature Compensated Current Sensing Technique for DC to DC,” by R. Isham, assigned to the assignee of the present application and the disclosure of which is incorporated herein.

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,765,372. The reissue applications are reissue application Ser. No. 11/488,927 (the parent reissue); and reissue application Ser. No. ( 12/426,884 ) (the present, continuation reissue application). Both Reissue applications are reissues of the same U.S. Pat. No. 6,765,372.

This reissue application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/340,324, filed Dec. 14, 2001.

FIELD OF THE INVENTION

The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved current-sensing and correction circuit with programmable, continuous compensation for temperature variations of an output switching MOSFET of a buck mode DC—DC converter.

BACKGROUND OF THE INVENTION

Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (DC) power sources, such as a buck-mode, pulse width modulation (PWM) based, DC—DC converter of the type diagrammatically shown in FIG. 1. As shown therein, a controller 10 supplies a PWM signal to a (MOSFET gate) driver 20, for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a load is coupled. In the illustrated DC—DC converter, these power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30, and a lower (or low side) power NFET device 40, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).

The upper NFET device 30 is turned on and off by an upper gate switching signal UGATE being applied to its gate from driver 20, and the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE from driver 20. A common node 35 between the upper and lower NFETs is coupled through an inductor 50 (which may typically comprise a transformer winding) to a load reservoir capacitor 60 coupled to a reference voltage terminal (GND). A connection 55 between inductor 50 and capacitor 60 serves as an output node from which a desired (regulated) DC output voltage Vout is applied to a LOAD 65 (shown as coupled to GND).

The output node connection 55 is also fed back to error amplifier circuitry (not shown) within the controller, the error amplifier being used to regulate the converter's output DC voltage relative to a reference voltage supply. In addition, the common node 35 is also coupled to current-sensing circuitry 15 within controller 10, in response to which the controller adjusts the PWM signal, as necessary, to maintain the converter's DC output within a prescribed set of parameters.

For this purpose, the controller may incorporate a current-sensing circuit of the type described in U.S. Pat. No. 6,246,220, entitled: “Synchronous-Rectified DC to DC Converter with Improved Current Sensing,” issued Jun. 12, 2001, by R. Isham et al, assigned to the assignee of the present application and the disclosure of which is incorporated herein. As described therein, the controller monitors the source-drain current flowing through the lower NFET 40 by way of a current-sensing or scaling resistor 37 electrically interconnected between node 35 and an current-sensing circuit 15.

The current-sensing circuit is operative to monitor the current ISENSE flowing through scaling resistor 37. This current is the product of the output current IOUT flowing from the common node 35 to the inductor 50 times the ratio of the ON-resistance RDS40ON of the lower NFET 40 to the resistance R37 of the scaling resistor 37, and is thus proportionally representative of the output current IOUT. The load current IL, namely the current I50 flowing through the inductor 50, is substantially equal to the output current IOUT minus the current ISENSE flowing through the scaling resistor 37.

As the ratio of RDS40ON to R37 is typically relatively small, the current ISENSE will be substantially smaller than the output current IOUT, so that the output current IOUT and the load current IL will have substantially similar magnitudes, making ISENSE representative of load current. The resistance of the scaling resistor 37 is selected to provide a prescribed value of current flow for the values of load current IL and/or the value of the ON-state resistance RDS40ON of the lower NFET 40. Thus, the sensitivity or magnitude of, for example, voltage droop, current limiting or trip, and current balancing incorporated into the DC/DC converter is effectively ‘scaled’ by selecting resistor 37 relative to the value of the on-state resistance RDS40ON of the lower NFET 40. Moreover, the voltage drop across the on-state resistance RDS40ON of the lower NFET 40 (usually negative) is accommodated in the converter without a negative voltage supply. In addition, since the ON-resistance RDS40ON of the lower NFET 40 varies with temperature, scaling resistor 37 must be selected to have a temperature coefficient which offsets the behavior of NFET 40. This may be accomplished by replacing scaling resistor 37 with a network of resistors and positive temperature coefficient thermistors.

As shown in greater detail in FIG. 2, the controller's current-sensing circuit 15 comprises a sense amplifier 200 having a first, non-inverting (+) input 201 coupled to a controller SENSE-port 11, and a second, inverting (−) input 202 coupled to a controller SENSE+ port 12. The SENSE-port 11 is coupled to the grounded termination of NFET 40, while the SENSE+ port 12 is coupled through scaling resistor 37 to common node 35. The sense amplifier 200 has its output 203 coupled to the gate 213 of an NFET 210, whose drain-source path is coupled between the SENSE+ port 12 and input terminal 221 of a sample-and-hold circuit 220. Sample-and-hold circuit 220 includes PFETs 240 and 250 coupled with a capacitor 260 and input sampling switching circuitry.

In operation, the sense amplifier 200 and NFET 210 (which serves as a controlled impedance) are operative to continuously drive the controller's SENSE+ port 11 toward ground potential. This forces the end of the current feedback resistor 37 which is connected to controller SENSE+ port 11 to be at ground potential and the end connected to common node 35 to have a negative voltage. The negative voltage at common output node 35 will be equal to the product of the output current IOUT and the on-state resistance RDS40ON between the drain and source of the lower NFET 40.

Current from the sample and hold circuit 220 flows into the drain and out of the source of NFET 210 into the SENSE+ port 11. Also flowing into the SENSE+ port 11 from the opposite direction is the current ISENSE which, as described above, is representative of load current IL. In order to maintain the SENSE+ port 11 at ground potential, sense amplifier 200 adjusts the current flowing through NFET 210 and into SENSE+ port 11 to be substantially equal to ISENSE. Since ISENSE is representative of the load current IL, the current flowing through NFET 210 and into SENSE+ port 11, as controlled by sense amplifier 200, is also representative of load current IL.

Within the controller 10, sampling control circuitry periodically supplies a sampling control signal to the sample-and-hold circuit 220, when NFET 210 is in its ON (conducting) state. In response to this sampling control signal, the sample-and-hold circuit 220 samples the current flowing through NFET 210 and stores the sampled value on capacitor 260 via node 236. Thus, the sampled current value acquired by the sample-and-hold circuit 220 is also representative of load current IL. This sampled value of sensed current is coupled from the sample and hold circuit's output port 223 to the controller's error amplifier circuitry that monitors the output node 55.

As pointed out above, the scaling resistor 37 that couples the common node 35 to the controller's SENSE+ port 11 must have a temperature coefficient that offsets the behavior of the on-state resistance RDS40ON of the lower NFET 40 (which varies with temperature and may be as high as forty percent over a typical operating range). As a result, it is customary to employ some form of complicated and costly feedback network in place of resistor 37.

SUMMARY OF THE INVENTION

In accordance with the present invention, the above-discussed temperature variation problem is successfully addressed by a new and improved current-sensing and correction circuit, containing programmable temperature compensation circuitry and being configured to be incorporated into a DC—DC converter, such as the buck mode architecture of the type shown in FIGS. 1 and 2, described above.

The front end portion of each embodiment of the invention includes sense amplifier, NFET and sample-and-hold components described above with reference to FIG. 2. In addition to providing the sampled sense current to the sample-and-hold output terminal, an auxiliary output of the sample-and-hold circuit supplies a copy of the sampled sense current to a programming resistor having a programmable resistance. The voltage produced across the programming resistor is coupled to respective high temperature compensation (HIGHtc) and low temperature compensation (LOWtc) auxiliary sense amplifiers.

The output of the HIGHtc auxiliary sense amplifier controls a HIGHtc NFET, the drain-source path of which is coupled to a HIGHtc scaling resistor. The temperature coefficient of resistance of the HIGHtc scaling resistor is higher than that of a LOWtc scaling resistor in the source-drain path of a LOWtc NFET at the output of the LOWtc auxiliary sense amplifier. The source-drain path of the HIGHtc NFET is coupled to a current mirror, which supplies a copy of the current in the source-drain path of the HIGHtc NFET to summing node, that serves as the output of the current-sensing and correction circuit. The summing node combines the HIGHtc and LOWtc currents and the sensed current to produce a “temperature-corrected” output current that is coupled to the controller's error amplifier circuitry in place of the sensed current.

Since the temperature coefficient of the HIGHtc scaling resistor is larger than the temperature coefficient of the LOWtc scaling resistor, the ratio of the resistance of the HIGHtc resistor to that of the programming resistor will have a larger slope with temperature than the ratio of the resistance of the LOWtc resistor to that of the programmiong resistor. As a result, the contribution of the HIGHtc current flowing into the output node will decrease with increasing temperature faster than the contribution of the LOWtc current flowing out of the output node, so that the composite corrected current will decrease with increase in temperature.

For temperatures greater than a HIGHtc/LOWtc current-equality temperature, at which point the HIGHtc and LOWtc resistors are equal, the ratio of the corrected current to the sensed current will be less than 1.0; for temperatures below this current-equality temperature, the ratio of the corrected current to the sensed current will be greater than 1.0. Namely, the temperature-compensating relationship of the corrected current to the sensed current is such that the ratio of corrected current to sensed current follows a deterministic curve at temperatures other than said predetermined temperature. It should be noted that the amount of temperature compensation is set by the programming resistor.

In a second embodiment, the first embodiment is modified to substitute an additional gain stage for the current mirror that supplies the replicated HIGHtc current to the output/summing node. This provides more temperature dependence for given values of thermal coefficients of resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 diagrammatically illustrates a conventional buck-mode, pulse width modulation (PWM) based, DC—DC converter;

FIG. 2 diagrammatically illustrates a current-sensing circuit for the controller of the DC—DC converter of FIG. 1;

FIG. 3 diagrammatically shows a current-sensing and programmable temperature-compensation circuit in accordance with a first embodiment of the present invention;

FIG. 4 graphically depicts the relationship between the ratio of temperature-compensated current ICORRECTED to sense current ISENSE over a temperature range (−20° C. to +125° C.), for a number of different resistance values RPROGRAM of the programming resistor of the embodiment of the current-sensing and programmable temperature-compensation circuit of FIG. 3;

FIG. 5 diagrammatically shows a current-sensing and programmable temperature-compensation circuit in accordance with a second embodiment of the invention, in which the embodiment of FIG. 3 is modified to incorporate an additional gain stage in place of the current mirror circuitry that is used to supply the replicated current component IHIGHtc to the output node.

DETAILED DESCRIPTION

Before describing a number of embodiments of the current-sensing circuit of the invention, which provides programmable, continuous compensation for variations in the operational temperature of an output switching MOSFET of a buck mode DC—DC converter, it should be observed that the invention resides primarily in an arrangement of conventional DC power supply circuit and control components, and the manner in which they are integrated together to realize a temperature-compensated power supply architecture of the type described briefly above.

It will also be appreciated that the invention may be embodied in a variety of other implementations, and should not be construed as being limited to only those shown and described herein. For example, although the non-limiting circuit implementations of the Figures shows the use of MOSFET devices, it is to be understood that the invention is not limited thereto, but also may be configured of alternative equivalent circuit devices, such as bipolar transistors, for example. The implementation examples to be described are intended to furnish only those specifics that are pertinent to the present invention, so as not to obscure the disclosure with details that are readily apparent to one skilled in the art having the benefit of present description. Throughout the text and drawings like numbers refer to like parts.

Attention is now directed to FIG. 3, which diagrammatically illustrates a first embodiment of a current-sensing and correction circuit in accordance with the present invention, containing programmable temperature compensation circuitry and being configured to be incorporated into a buck mode DC—DC converter of the type shown in FIGS. 1 and 2, described above. The front end portion of the temperature compensated current sensing and correction circuit of FIG. 3, shown within broken lines 300, contains the sense amplifier, NFET and sample-and-hold components shown in FIG. 2, discussed above. As such, these components will not be redescribed, except as necessary to explain the architecture and operation of the invention.

Within the front end circuitry 300 of the temperature compensated sense amplifier, a sample value storage node 224 of the sample-and-hold circuit 220 is connected to a sampled value storage capacitor 260, which is switchably coupled (via switching unit 231) to input node 221, so that it may receive and store a sampled value of the sensed current. Node 224 is further coupled to the gate of an output PMOSFET 250 that supplies the sampled sense current ISENSE to the sample-and-hold output terminal 223, and additionally to the gate of an auxiliary output PMOSFET 227, that supplies a copy of the sample sense ISENSE current to an auxiliary output terminal 228.

This copy of the ISENSE current provided by the auxiliary output terminal 228 is coupled to a programming resistor 310, referenced to ground and having a programmable resistance rPROGRAM. (Ideally, the temperature coefficient of the programming resistor 310 is zero or very close to zero). The programming resistor is used to change the slope of a deterministic curve, such as that shown in FIG. 4, which represents the ratio of corrected or temperature-compensated current to the sensed current ISENSE.

The voltage produced across the programming resistor 310 at node 228 is coupled to each of a first, non-inverting (+) input 321 of a first auxiliary sense amplifier 320, and to a first, non-inverting (+) input 331 of a second auxiliary sense amplifier 330. The first auxiliary sense amplifier 320 has its second, inverting (−) input 322 coupled to a node 324 between a first, ‘HIGHtc’ scaling resistor 325 and the source-drain current flow path of an NFET 340.

NFET 340 has its gate coupled to the output 323 of the first auxiliary sense amplifier 320. Scaling resistor 325, which is coupled to ground, has a first prescribed scaling resistance value rHIGHtc, that serves to reduce the ratio of a composite, temperature compensated, or corrected, output current ICORRECTED to the ISENSE current at temperatures above a predetermined temperature. In the present example, the temperature coefficient of resistance of the scaling resistance 325 is higher than the temperature coefficient of resistance of a second scaling resistor 335, to be described.

The source-drain path of NFET 340 is coupled to the source-drain path of a current mirror PFET 350, which is referenced to the VCC voltage rail. NFET 340 is controlled by the first auxiliary sense amplifier 320 to produce a first fractional, or scaled, version of sense current ISENSE as a first temperature compensation current IHIGHtc, that is combined with the sense current ISENSE and a second temperature compensation current ILOWtc, to realize the temperature corrected, output current ICORRECTED, as will be described.

PFET 350 is coupled in current-mirror configuration with PFET 360, which has its source-drain path referenced to the VCC voltage rail, and coupled via an output node 365 to the source-drain path an NFET 370. As result, the source-drain path of current mirror PFET 360 mirrors the ‘high’ temperature coefficient compensation current IHIGHtc (flowing through the scaling resistor 325 and the source-drain path of PFET 350) and couples this current to the output node 365.

Output node 365, from which the ‘corrected’ sense current ICORRECTED is derived, is coupled in common with the output port 223 of the sample and hold circuit 220. NFET 370 has its source-drain path coupled to a node 334 between a second, ‘LOWtc’ scaling resistor 335 and the source-drain current flow path of an NFET 370. Scaling resistor 335 is coupled to ground. Node 334 is coupled to an inverting (−) input 332 of the second auxiliary amplifier 330. As pointed out above, in the present example, the temperature coefficient of resistance of the scaling resistance 335 is lower than the temperature coefficient of resistance of a scaling resistor 325.

Similar to NFET 340, NFET 370 is controlled by the output of the second auxiliary sense amplifier 330 to produce a second scaled version of the sense current ISENSE as a second temperature compensation current ILOWtc. This second temperature compensation current is combined at output port 365 with the sense current ISENSE and the first temperature compensation current IHIGHtc, to realize the temperature corrected, output current ICORRECTED.

In operation, the copy of the current ISENSE provided by auxiliary output 228 flows through programming resistor 310 to produce a voltage VrPROGRAM across the programming resistor. This voltage is applied to the non-inverting (+) inputs of each of the auxiliary sense amplifiers 320 and 330. In response to this voltage, the first auxiliary amplifier 320 drives the gate of NFET 340, to produce a source-drain current IHIGHtc, that flows through scaling resistor 325; in a like manner, the second auxiliary amplifier 330 drives the gate of NFET 370, to produce a source-drain current ILOWtc, that flows through scaling resistor 335.

The value of the drain-source current IHIGHtc through NFET 340 is proportional to the current ISENSE in accordance with the ratio of the resistance (rPROGRAM) of the programming resistor 310 (through which the current ISENSE flows) and the resistance rHIGHtc of the scaling resistor 325 (through which the current IHIGHtc flows). Namely, IHIGHtc=ISENSE*(rPROGARM/rHIGHtc). Similarly, the value of the drain-source current ILOWtc through the NFET 370 is proportional to the current ISENSE in accordance with the ratio of the resistance (rPROGRAM) of the programming resistor 310 and the resistance rLOWtc of the scaling resistor 335 (through which the current ILOWtc flows). Namely, ILOWtc=ISENSE*(rPROGRAM/rLOWtc).

The two currents IHIGHtc and ILOWtc are set at the same value for a particular operating temperature (such as 25° C.). Since current mirror PFET 360 is operative to mirror the temperature compensation current IHIGHtc in the source-drain path of PFET 350 in accordance with the operation of NFET 340, the output node 365 is supplied with three current components: 1—the sense current ISENSE from port 223 of the sample and hold circuit 220; 2—the current IHIGHtc mirrored by PFET 360; and 3—the current ILOWtc produced by NFET 370. Due to the directions of current flow of these three current components relative to output node 365, a composite temperature-compensated output current ICORRECTED can be defined as:
ICORRECTED=ISENSE−ILOWtc+IHIGHtc, or
ICORRECTED=ISENSE*(1−(rPROGRAM/rLOWtc)+(rPROGRAM/rHIGHtc)).

This temperature-compensated current ICORRECTED is coupled to the controller's error amplifier circuitry in place of the sensed current ISENSE, as described above.

FIG. 4 contains a family of deterministic curves, that graphically depict the temperature-compensating relationship (i.e., ratio) of the temperature-compensated or correction current ICORRECTED to the sense current ISENSE over a typical operational temperature range (−20° C. to +125° C.), for a number of different resistance values RPROGRAM of the programming resistor 310, and with the two currents IHIGHtc and ILOWtc being the same at the above-referenced value of 25° C. As shown therein, for the temperature (25° C.) at which the two currents IHIGHtc and ILOWtc are equal, from the above equation for ICORRECTED, the ratio of ICORRECTED to ISENSE, i.e., ICORRECTED/ISENSE=1.0.

Since the temperature coefficient of resistance of resistor 325 is greater than the temperature coefficient of resistance of resistor 335, the ratio of the resistance of resistor 325 to the resistance of programming resistor 310 will increase with temperature faster than the ratio of the resistance of resistor 335 to the resistance of programming resistor 310. As a result, as the temperature increases, the contribution of the current component IHIGHtc into node 365 will decrease faster than the contribution of the current ILOWtc away from node 365, so that the composite current ICORRECTED will decrease.

Thus, for temperatures greater than the current-equality (IHIGHtc=ILOWtc) temperature, ICORRECTED/ISENSE will be less than 1.0, while for temperatures below the current-equality (IHIGHtc=ILOWtc) temperature, ICORRECTED/ISENSE will be greater than 1.0, as shown.

FIG. 5 diagrammatically shows a second embodiment of the current sensing circuit of the invention, in which the first embodiment of FIG. 3 is modified to incorporate an additional gain stage in place of the current mirror circuitry that is used to supply the replicated current component IHIGHtc to the output node. In particular, PFETs 350 and 360 of the first embodiment are replaced with a gain stage 500 having a third auxiliary amplifier 510 which drives a PFET 520. Amplifier 510 has its non-inverting (+) input 512 coupled to a node 514, which is connected in common to a scaling resistor 530 referenced to VCC and NFET 340. Scaling resistor 530 has a resistance rLOWtc2. Amplifier 510 has its inverting (−) input 511 coupled to a node 515, which is connected in common to a scaling resistor 540 referenced to VCC and PFET 520. Scaling resistor 540 has a resistance rHIGHtc2.

This modified architecture operates in the same manner as current mirror PMOSFETs 350 and 360, but modifies the current output of PMOSFET 520 dependent on temperature.

Resistance rHIGHtc2 has a higher thermal coefficient of resistance than resistance rLOWtc2. At some reference temperature, such as the temperature at which resistance rHIGHtc and resistance rLOWtc are equal, as described above, resistance rHIGHtc2 and resistance rLOWtc2 are equal. At this temperature, the current through the resistance rHIGHtc 325, and NMOSFET 340 into resistance rLOWtc2 530 is replicated by PMOSFET 520 through resistance rHIGHtc2 540. As the temperature increases above this point, the ratio of rHIGHtc2/rLOWtc2 increases and, conversely, the current out of PMOSFET 520 decreases. The current out of PMOSFET 520, or IHIGHtc, becomes equal to: ISENSE*(RPROGRAM/RHIGHtc)*(RLOWtc2/RHIGHtc2).

As described above, the current out of NMOSFET 370, or ILOWtc, is ISENSE*(RPROGRAM/RLOWTC).

The corrected current is ISENSE+IHIGHtc−ILOWtc, or
ISENSE(1+RPROGRAM(RLOWtc2/(RHIGHtc+RHIGHtc2+)−(1/RLOWtc)).

This gives a higher rate of change with temperature compared to the first embodiment, which is:
ISENSE(1+RPROGRAM((1/RHIGHtc)−(1/RLOWtc))).

It may be noted that additional gain stages such as gain stage 500 may be added for additional increases in thermal gain.

This temperature-compensated current ICORRECTED is coupled to the controller's error amplifier circuitry in place of the sensed current ISENSE, as described above.

As will be appreciated from the foregoing description, the inability of a simple scaling resistor installed between the common node of a DC—DC converter to a controller sense port to provide compensation for the temperature-responsive behavior of the on-state resistance of the lower NFET in the converter, (which may be as high as forty percent over a typical operating range), is successfully addressed by the current-sensing circuit of the invention, which provides programmable, continuous compensation for temperature variations of an output switching MOSFET of a buck mode DC—DC converter.

By coupling copies of the sampled current, that has been sensed through a sense resistor coupled to the common MOSFET node of the DC—DC converter, to prescribed programming and scaling resistors coupled to high and low auxiliary sense amplifiers, which drive ‘high’ temperature coefficient (hightc’) and ‘low’ temperature coefficient (‘lowtc’) associated, controlled ‘hightc’ and ‘lowtc’ current paths, a corrected current can be derived as a combination of the sensed current and the controlled ‘hightc’ and ‘lowtc’ currents. Due to the directions of current flow of these three current components relative to output the node, a composite temperature-compensated output current ICORRECTED can be defined in as:
ICORRECTED=ISENSE−ILOWtc+IHIGHtc or, in terms of the resistors, as:
ICORRECTED=ISENSE*(1−(rPROGRAM/rLOWtc)+(rPROGRAM/rHIGHtc)).

Thus the ratio of ICORRECTED to ISENSE can be written as:
ICORRECTED/ISENSE=1−(rPROGRAM/rLOWtc)+(rPROGRAM/rHIGHtc).

In a second embodiment an additional gain stage is inserted in place of the current mirror circuitry that is used to supply the replicated current component IHIGHtc to the output node, so that the output current of the PMOSFET is modified in dependence on temperature. The corrected current is ISENSE+IHIGHtc−ILOWtc, or
ISENSE(1+RPROGRAM(RLOWtc2/(RHIGHtc+RHIGHtc2+)−(1/RLOWtc)).

As noted above, this gives a higher rate of change with temperature compared to the first embodiment, as:
ISENSE(1+RPROGRAM((1/RHIGHtc)−(1/RLOWtc))).

The temperature-compensated current ICORRECTED is coupled to the controller's error amplifier circuitry to track the temperature variations in the drain-source resistance of the lower MOSFET of the converter.

While I have shown and described several embodiments in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art. I therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

Claims (32)

1. An apparatus for generating a regulated direct current (DC) output voltage comprising:
a DC—DC converter coupled to a supply voltage, and being operative to generate a regulated output voltage derived from said supply voltage, said DC—DC converter having a pulse width modulation generator which generates a PWM switching signal that switchably controls operation of a switching circuit containing first and second electronic power switching devices coupled between respective first and second power supply terminals, a common node thereof being coupled through an inductor element to an output voltage terminal; and
a controller for controlling the operation of said PWM generator, said controller including
a sense amplifier unit having an input coupled to said first power supply terminal, a second input and an output,
a current feedback resistor electrically coupled between said common output node and said second input of said sense amplifier unit,
a variable impedance coupled to said output of said sense amplifier unit and to said second input of said sense amplifier unit, said variable impedance configured to vary in impedance in response to said output of said sense amplifier unit,
a sample and hold circuit coupled to said variable impedance, and being operative to sample and hold current flowing through said variable impedance as a sensed current, and
a sensed current correction circuit, coupled between said sample and hold circuit and said controller, and being operative to supply, to said controller, a correction current having a prescribed temperature-compensating relationship to said sensed current as sampled and held by said sample and hold circuit.
2. The apparatus according to claim 1, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that the ratio of said correction current to said sensed current equals one at a predetermined temperature, and has a values other than one at temperatures other than said predetermined temperature.
3. The apparatus according to claim 1, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that the ratio of said correction current to said sensed current follows a deterministic curve at temperatures other than said predetermined temperature.
4. The apparatus according to claim 3, wherein said first electronic power switching device comprises a MOSFET, and said deterministic curve approximates a variation of drain-source resistance of said MOSFET with temperature.
5. The apparatus according to claim 3, wherein said sensed current correction circuit includes a programming element that is operative to change the slope of said deterministic curve.
6. The apparatus according to claim 1, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that said correction current equals said sensed current at a predetermined temperature and, at temperatures above said predetermined temperature the ratio of said correction current to said sensed current is less than one, and at temperatures below said predetermined temperature the ratio of said correction current to said sensed current is greater than one.
7. The apparatus according to claim 1, wherein said sensed current correction circuit includes a programming element that is effective to establish said prescribed temperature-compensating relationship to said current as sampled and held by said sample and hold circuit.
8. The apparatus according to claim 1, wherein
said sample and hold circuit is operative to generate first and second sensed currents, each of which is representative of said current as sampled and held by said sample and hold circuit, and
said sensed current correction circuit includes
a first sensed current path, that is operative to process said first sensed current to produce first and second scaled versions of said sensed current, and
a second sensed current path, coupled with said first sensed current path, and being operative to combine said second sensed current with said first and second scaled versions of said sensed current to produce said control current.
9. The apparatus according to claim 8, wherein said first sensed current path is operative to process said first sensed current in accordance with a programmable circuit element to produce first and second scaled versions of said sensed current.
10. The apparatus according to claim 9, wherein said first current path includes said programmable circuit element, and first and second auxiliary amplifier circuits coupled to said programmable circuit element to produce said first and second scaled versions of said sensed current.
11. The apparatus according to claim 10, wherein said first current path includes a current flow direction circuit coupled with one of said first and second auxiliary amplifier circuits and being operative to supply one of said first and second scaled versions of said sensed current with a prescribed current flow direction relative to said second sensed current.
12. The apparatus according to claim 11, wherein said current flow direction circuit comprises a current mirror circuit coupled to said first auxiliary amplifier circuit and being operative to supply said first scaled version of said sensed current with said prescribed current flow direction relative to said second sensed current.
13. The apparatus according to claim 11, wherein said current flow direction circuit comprises a third auxiliary amplifier circuit coupled to said first auxiliary amplifier circuit and being operative to supply said first scaled version of said sensed current with said prescribed current flow direction relative to said second sensed current.
14. A power supply comprising:
a buck mode pulse width modulator (PWM) DC—DC converter circuit having an input, a high side output and a low side output;
a high side switch coupled between a first voltage supply terminal and common output node, and being operative to control current flow therethrough in response to said high side output;
a low side switch coupled between said common output node and to a second voltage supply terminal, and being operative to control current flow therethrough in response to said low side output;
a sense amplifier unit having a first input, a second input and an output, said second input coupled to said second voltage supply terminal;
a current feedback resistor electrically coupled between said common output node and said first input of said sense amplifier;
a variable impedance component electrically connected to said output of said sense amplifier unit and to said first input of said sense amplifier, said variable impedance component configured to vary in impedance in response to said output of said sense amplifier unit;
a sample and hold circuit coupled to said variable impedance component, and being operative to sample and hold current flowing through said variable impedance component as a sensed current; and
a sensed current correction circuit, coupled between said sample and hold circuit and said buck mode PWM DC—DC converter, and being operative to supply, to said input of said buck mode PWM DC—DC converter, a correction current having a prescribed temperature-compensating relationship to said sensed current as sampled and held by said sample and hold circuit.
15. The power supply according to claim 14, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that the ratio of said correction current to said sensed current follows a deterministic curve at temperatures other than said predetermined temperature.
16. The power supply according to claim 15, wherein said first electronic power switching device comprises a MOSFET, and said deterministic curve approximates a variation of drain-source resistance of said MOSFET with temperature.
17. The power supply according to claim 16, wherein said sensed current correction circuit includes a programming element that is operative to change the slope of said deterministic curve.
18. The power supply according to claim 14, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that said correction current equals said sensed current at a predetermined temperature and, at temperatures above said predetermined temperature the ratio of said correction current to said sensed current is less than one, and at temperatures below said predetermined temperature the ratio of said correction current to said sensed current is greater than one.
19. A method of controlling the operation of a DC—DC converter, said DC—DC converter being coupled to a supply voltage, and being operative to generate a regulated output voltage derived from said supply voltage, said DC—DC converter including
a pulse width modulation generator, which generates a PWM switching signal that switchably controls operation of a switching circuit containing first and second electronic power switching devices coupled between respective first and second power supply terminals, a common node thereof being coupled through an inductor element to an output voltage terminal, and
a controller for controlling the operation of said PWM generator, said controller including a sense amplifier unit having a first input coupled to said first power supply terminal, a second input and an output, a current feedback resistor coupled between said common output node and said second input of said sense amplifier unit, a variable impedance coupled to said output of said sense amplifier unit, said variable impedance configured to vary in impedance in response to said output of said sense amplifier unit, and a sample and hold circuit coupled to said variable impedance, and being operative to sample and hold current flowing through said variable impedance as a sensed current,
said method comprising the steps of:
(a) generating a correction current having a prescribed temperature-compensating relationship to said sensed current as sampled and held by said sample and hold circuit; and
(b) coupling said correction current to said controller, so that said controller controls the operation of said PWM generator in accordance with said correction current.
20. The method according to claim 19, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that the ratio of said correction current to said sensed current equals one at a predetermined temperature, and has values other than one at temperatures other than said predetermined temperature.
21. The method according to claim 19, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that the ratio of said correction current to said sensed current follows a deterministic curve at temperatures other than said predetermined temperature.
22. The method according to claim 21, wherein said first electronic power switching device comprises a MOSFET, and said deterministic curve approximates a variation of drain-source resistance of said MOSFET with temperature.
23. The method according to claim 21, wherein step (a) comprises establishing the slope of said deterministic curve using a programming element.
24. The method according to claim 19, wherein said prescribed temperature-compensating relationship of said correction current to said sensed current is such that said correction current equals said sensed current at a predetermined temperature and, at temperatures above said predetermined temperature the ratio of said correction current to said sensed current is less than one, and at temperatures below said predetermined temperature the ratio of said correction current to said sensed current is greater than one.
25. A power supply comprising:
a first switch coupled to a first voltage supply terminal and to a common output node;
a second switch coupled to the common output node and to a second voltage supply terminal;
a control circuit operable to provide a first switching signal to the first switch and a second switching signal to the second switch; wherein the first and second switches are turned on and off in response to the first and second switching signals, respectively;
a current sense circuit generating a sensed current that is related to an output current of the power supply; and
a sensed current correction circuit, coupled to the current sense circuit and the control circuit, and being operative to provide, to the control circuit, a correction current used to adjust the first and second switching signals, the correction current having a prescribed temperature-compensating relationship to said sensed current, wherein said correction current is a combination of said sensed current, a first compensating current and a second compensating current.
26. The power supply according to claim 25, wherein the prescribed temperature-compensating relationship of the correction current to the sensed current is such that the ratio of the correction current to the sensed current follows a deterministic curve at temperatures other than a predetermined temperature.
27. The power supply according to claim 26, wherein the second switch comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), and the deterministic curve approximates an inverse of a variation of drain-source resistance of the MOSFET with temperature.
28. The power supply according to claim 26, wherein the sensed current correction circuit includes a programming element that is operative to change the slope of the deterministic curve.
29. The power supply according to claim 25, wherein the prescribed temperature-compensating relationship of the correction current to the sensed current is such that the correction current equals the sensed current at a predetermined temperature and, at temperatures above the predetermined temperature the ratio of the correction current to the sensed current is less than one, and at temperatures below the predetermined temperature the ratio of the correction current to the sensed current is greater than one.
30. The power supply according to claim 25, wherein the current sense circuit comprises:
a sense amplifier unit having a first input, a second input and an output, the first input coupled to the common output node and the second input coupled to the second voltage supply terminal;
a variable impedance component coupled to the output of the sense amplifier unit and to the first input of the sense amplifier unit, the variable impedance component configured to vary in impedance in response to the output of the sense amplifier unit; and
a sensed current providing circuit coupled to the variable impedance component, and being operative to provide a sensed current in accordance with a current flowing through the variable impedance.
31. The power supply according to claim 30, wherein the sensed current providing circuit comprises a sample and hold circuit operative to sample and hold current flowing through the variable impedance component as a sensed current.
32. The power supply according to claim 30, wherein the variable impedance component comprises an n-channel metal-oxide-semiconductor field-effect transistor (NFET).
US12/426,884 2001-12-14 2009-04-20 Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter Active USRE42037E1 (en)

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US11/488,927 USRE40915E1 (en) 2001-12-14 2006-07-18 Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter
US12/426,884 USRE42037E1 (en) 2001-12-14 2009-04-20 Programmable current-sensing circuit providing continuous temperature compensation for DC-DC converter

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10396660B2 (en) * 2016-05-31 2019-08-27 Rohm Co., Ltd. Switching regulator, semiconductor integrated circuit, and electronic appliance

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1316271B1 (en) * 2000-12-28 2003-04-03 Micron Technology Inc Pulse generator in offset voltage and temperature.
EP1424766A1 (en) * 2002-11-29 2004-06-02 SGS-THOMSON MICROELECTRONICS S.r.l. Switching voltage regulator
ITMI20031505A1 (en) * 2003-07-22 2005-01-23 St Microelectronics Srl Circuit of MULTISENSE-adaptive type reading, in particular for dc-dc interleaved and relative method of reading converters
US6946897B2 (en) * 2003-10-22 2005-09-20 Intersil Americas Inc. Technique for measuring temperature and current via a MOSFET of a synchronous buck voltage converter
JP4056965B2 (en) * 2003-10-29 2008-03-05 株式会社マキタ Charger
US6975146B1 (en) 2004-01-02 2005-12-13 Sauer-Danfoss Inc. High side NFET gate driving circuit
TWI233996B (en) * 2004-03-30 2005-06-11 Richtek Techohnology Corp Current-sensing device applied to multi-phase DC-to-DC converter
US7466116B2 (en) * 2004-04-12 2008-12-16 Renesas Technology America, Inc. Current sensing circuit for a multi-phase DC-DC converter
US7282894B2 (en) * 2004-08-25 2007-10-16 Matsushita Electric Industrial Co., Ltd. Method and apparatus for performing lossless sensing and negative inductor currents in a high side switch
TWI259273B (en) * 2004-09-22 2006-08-01 Richtek Technology Corp Temperature compensation device applied to voltage regulator and method thereof
US7693491B2 (en) * 2004-11-30 2010-04-06 Broadcom Corporation Method and system for transmitter output power compensation
US7504816B2 (en) * 2005-09-28 2009-03-17 Intersil Americas Inc. Circuit for multiplexing digital and analog information via single pin of driver for switched MOSFETs of DC-DC converter
US7568117B1 (en) 2005-10-03 2009-07-28 Zilker Labs, Inc. Adaptive thresholding technique for power supplies during margining events
US7375503B2 (en) * 2006-01-11 2008-05-20 Atmel Corporation System for current sensing in switched DC-to-DC converters
JP4795173B2 (en) * 2006-08-29 2011-10-19 セイコーインスツル株式会社 Temperature compensation circuit
GB2451467B (en) * 2007-07-28 2013-01-16 Zetex Semiconductors Plc Current driving method and circuit
US7994762B2 (en) 2007-12-11 2011-08-09 Analog Devices, Inc. DC to DC converter
CN101470142B (en) * 2007-12-27 2011-03-09 英业达股份有限公司 Overcurrent detection circuit, decompression converter and overcurrent detection method
US8232784B2 (en) 2008-04-01 2012-07-31 O2Micro, Inc Circuits and methods for current sensing
JP5169498B2 (en) * 2008-06-02 2013-03-27 株式会社リコー Current detection circuit and switching regulator including the current detection circuit
EP2230755B1 (en) * 2009-03-19 2017-09-06 Dialog Semiconductor GmbH Charge current reduction for current limited switched power supply
US8552693B2 (en) * 2009-07-17 2013-10-08 Tesla Motors, Inc. Low temperature charging of Li-ion cells
TWI387186B (en) * 2009-11-04 2013-02-21 Richtek Technology Corp Reference signal generator and method for providing a reference signal with adaptive temperature cofficient
CN102063139B (en) * 2009-11-12 2013-07-17 登丰微电子股份有限公司 Temperature coefficient regulation circuit and temperature compensation circuit
TWI409610B (en) * 2009-12-18 2013-09-21 Green Solution Tech Co Ltd Temperature coefficient modulating circuit and temperature compensation circuit
US8629669B2 (en) 2010-07-27 2014-01-14 Volterra Semiconductor Corporation Sensing and feedback in a current mode control voltage regulator
US8649129B2 (en) * 2010-11-05 2014-02-11 System General Corporation Method and apparatus of providing over-temperature protection for power converters
CN102005731B (en) * 2010-11-15 2014-05-14 崇贸科技股份有限公司 Controller, power converter and method for providing over-temperature protection
CN102478606A (en) * 2010-11-26 2012-05-30 鸿富锦精密工业(深圳)有限公司 Overcurrent protection resistance detection circuit for voltage-reduction transfer circuit
US9018930B2 (en) * 2010-12-23 2015-04-28 Stmicroelectronics S.R.L. Current generator for temperature compensation
KR20120078947A (en) * 2011-01-03 2012-07-11 페어차일드코리아반도체 주식회사 Switch control circuit, converter using the same, and switch controlling method
TWI444806B (en) * 2011-01-31 2014-07-11 Richtek Technology Corp Adaptive temperature compensation circuit and method
ITMI20111594A1 (en) 2011-09-05 2013-03-06 St Microelectronics Srl a switching voltage regulator
TWI470391B (en) * 2012-06-04 2015-01-21 Issc Technologies Corp Current regulation circuit and electronic device thereof
WO2014167719A1 (en) * 2013-04-12 2014-10-16 三菱電機株式会社 Power convertor, motor driver equipped with power convertor, blower and compressor equipped with motor driver, and air conditioner, refrigerator, and freezer equipped with blower and compressor
CN103296867B (en) * 2013-06-28 2015-07-15 成都芯源系统有限公司 Multiphase switching converter and controller and control method thereof
US9513318B2 (en) * 2014-05-29 2016-12-06 Infineon Technologies Ag Current or voltage sensing
EP2952914A1 (en) * 2014-06-06 2015-12-09 Dialog Semiconductor GmbH Output current monitoring circuit
US9991792B2 (en) 2014-08-27 2018-06-05 Intersil Americas LLC Current sensing with RDSON correction
US9588155B2 (en) * 2014-10-16 2017-03-07 Freescale Semiconductor, Inc. Current detection circuit with over-current protection
JP6519270B2 (en) * 2015-03-30 2019-05-29 横浜ゴム株式会社 Apparatus and method for observing a rubber contact surface
TWI549406B (en) * 2015-11-20 2016-09-11 明緯(廣州)電子有限公司 Novel feedback circuit with temperature compensation function
US9923455B2 (en) * 2016-06-15 2018-03-20 Murata Manufacturing Co., Ltd. Current-sensing and gain-switching circuit and method for using wide range of current
KR20200119641A (en) * 2019-04-10 2020-10-20 엘에스일렉트릭(주) Power device monitoring system and and method for monitoring thereof

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4325017A (en) 1980-08-14 1982-04-13 Rca Corporation Temperature-correction network for extrapolated band-gap voltage reference circuit
JPH0343809A (en) 1989-07-11 1991-02-25 Sanyo Electric Co Ltd Temperature compensating circuit and printer with this circuit
US5134355A (en) 1990-12-31 1992-07-28 Texas Instruments Incorporated Power factor correction control for switch-mode power converters
JPH06174489A (en) 1992-12-07 1994-06-24 Fujitsu Ten Ltd Temperature compensating circuit
US5481178A (en) 1993-03-23 1996-01-02 Linear Technology Corporation Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit
US5552695A (en) 1994-03-22 1996-09-03 Linear Technology Corporation Synchronously rectified buck-flyback DC to DC power converter
US5568044A (en) 1994-09-27 1996-10-22 Micrel, Inc. Voltage regulator that operates in either PWM or PFM mode
EP0778509A1 (en) 1995-12-06 1997-06-11 International Business Machines Corporation Temperature compensated reference current generator with high TCR resistors
US5705919A (en) 1996-09-30 1998-01-06 Linear Technology Corporation Low drop-out switching regulator architecture
US5767664A (en) 1996-10-29 1998-06-16 Unitrode Corporation Bandgap voltage reference based temperature compensation circuit
US5912552A (en) 1997-02-12 1999-06-15 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho DC to DC converter with high efficiency for light loads
JPH11194842A (en) 1990-12-26 1999-07-21 Fuji Electric Co Ltd Control method for power unit
EP0992799A2 (en) 1998-10-05 2000-04-12 Lucent Technologies Inc. Temperature compensation circuit for semiconductor switch and method of operation thereof
JP3043809B2 (en) 1991-11-15 2000-05-22 ファイザー・インコーポレイテッド Gram-negative vaccine
US6246220B1 (en) 1999-09-01 2001-06-12 Intersil Corporation Synchronous-rectified DC to DC converter with improved current sensing
US6528976B1 (en) 1999-09-24 2003-03-04 Fairchild Semiconductor Corporation Fet sensing programmable active droop for power supplies
JP6174489B2 (en) 2010-09-28 2017-08-02 アエゲリオン ファーマシューティカルズ,インコーポレイテッド Highly soluble leptin

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4325017A (en) 1980-08-14 1982-04-13 Rca Corporation Temperature-correction network for extrapolated band-gap voltage reference circuit
JPH0343809A (en) 1989-07-11 1991-02-25 Sanyo Electric Co Ltd Temperature compensating circuit and printer with this circuit
JPH11194842A (en) 1990-12-26 1999-07-21 Fuji Electric Co Ltd Control method for power unit
US5134355A (en) 1990-12-31 1992-07-28 Texas Instruments Incorporated Power factor correction control for switch-mode power converters
JP3043809B2 (en) 1991-11-15 2000-05-22 ファイザー・インコーポレイテッド Gram-negative vaccine
JPH06174489A (en) 1992-12-07 1994-06-24 Fujitsu Ten Ltd Temperature compensating circuit
US5481178A (en) 1993-03-23 1996-01-02 Linear Technology Corporation Control circuit and method for maintaining high efficiency over broad current ranges in a switching regulator circuit
US5552695A (en) 1994-03-22 1996-09-03 Linear Technology Corporation Synchronously rectified buck-flyback DC to DC power converter
US5568044A (en) 1994-09-27 1996-10-22 Micrel, Inc. Voltage regulator that operates in either PWM or PFM mode
EP0778509A1 (en) 1995-12-06 1997-06-11 International Business Machines Corporation Temperature compensated reference current generator with high TCR resistors
US5705919A (en) 1996-09-30 1998-01-06 Linear Technology Corporation Low drop-out switching regulator architecture
US5767664A (en) 1996-10-29 1998-06-16 Unitrode Corporation Bandgap voltage reference based temperature compensation circuit
US5912552A (en) 1997-02-12 1999-06-15 Kabushiki Kaisha Toyoda Jidoshokki Seisakusho DC to DC converter with high efficiency for light loads
EP0992799A2 (en) 1998-10-05 2000-04-12 Lucent Technologies Inc. Temperature compensation circuit for semiconductor switch and method of operation thereof
JP2000116119A (en) 1998-10-05 2000-04-21 Lucent Technol Inc Temperature compensation circuit
US6300818B1 (en) 1998-10-05 2001-10-09 Lucent Technologies Inc. Temperature compensation circuit for semiconductor switch and method of operation thereof
US6246220B1 (en) 1999-09-01 2001-06-12 Intersil Corporation Synchronous-rectified DC to DC converter with improved current sensing
US6528976B1 (en) 1999-09-24 2003-03-04 Fairchild Semiconductor Corporation Fet sensing programmable active droop for power supplies
JP6174489B2 (en) 2010-09-28 2017-08-02 アエゲリオン ファーマシューティカルズ,インコーポレイテッド Highly soluble leptin

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10396660B2 (en) * 2016-05-31 2019-08-27 Rohm Co., Ltd. Switching regulator, semiconductor integrated circuit, and electronic appliance

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USRE40915E1 (en) 2009-09-15
US20030111984A1 (en) 2003-06-19
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DE10297493T5 (en) 2004-12-23
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AU2002366486A8 (en) 2003-06-30
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JP2005518174A (en) 2005-06-16
TWI232022B (en) 2005-05-01

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