USRE41670E1 - Sram cell fabrication with interlevel Dielectric planarization - Google Patents

Sram cell fabrication with interlevel Dielectric planarization Download PDF

Info

Publication number
USRE41670E1
USRE41670E1 US09/488,686 US48868600A USRE41670E US RE41670 E1 USRE41670 E1 US RE41670E1 US 48868600 A US48868600 A US 48868600A US RE41670 E USRE41670 E US RE41670E
Authority
US
United States
Prior art keywords
layers
sram cell
layer
conductive layer
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/488,686
Inventor
Loi Nguyen
Ravishankar Sundaresan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Priority to US09/488,686 priority Critical patent/USRE41670E1/en
Application granted granted Critical
Publication of USRE41670E1 publication Critical patent/USRE41670E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Definitions

  • the present invention relates to integrated circuit fabrication methods and structures, and particularly to integrated circuits with minimum linewidths below one-half micron.
  • CMP Chemical-Mechanical-Polishing
  • SOG Sacrificial Etchback Spin-on-glass
  • Spin-on glass deposition is an example of a “sol-gel” process, which has been used in the semiconductor industry for many years.
  • the unprocessed spin-on glass material (available in numerous formulations) is a fluid material (actually a gel).
  • the wafer is rotated at high speed to throw off the excess material.
  • the surface tension and adhesion of the material provides a flat (planarized) surface with a controlled thickness.
  • the liquid material is then baked, to drive off solvents and provide a stable solid silicate glass.
  • FIG. 7 is a circuit diagram of such a cell (a 4-transistor 2-resistor MOS SRAM cell).
  • the numbering of the bitlines and wordlines indicates that this cell would be in the n-th row and m-th column of an array (or subarray) of memory cells.
  • NMOS driver transistors D 1 and D 2 loaded by resistors R 1 and R 2 , are cross-connected to form a latch.
  • Pass transistors PT 1 and PT 2 are both accessed by a respective wordline WL n , to connect the two complementary nodes of the latch to a respective complementary pair of bitlines BL m and BL m * when wordline WL n goes high.
  • wordline WL n goes high, whichever one of the driver transistors (D 1 or D 2 ) is ON will pull down one of the bitlines (BL m or BL m *), producing a data signal which can be read.
  • the bitlines will be clamped by strong drivers, and the pass transistors PT 1 and PT 2 will pass enough current to change the state of the latch to correspond to the bitline voltages.
  • the resistors R 1 and R 2 must pass enough current to offset the leakage currents which tend to discharge the high node of the latch.
  • These resistors are conventionally made from nearly intrinsic polysilicon, and therefore tend to have very high resistance values (which may range from many gigaohms up to teraohms).
  • the resistivity of such polysilicon is fairly variable, and an excessive value for the resistors may cause the cell to lose data under high-temperature conditions. An excessively low value for the polysilicon resistor may lead to excess static power consumption. Thus, precise control of the resistor values would be highly desirable.
  • This disclosure describes an improved method of four transistor SRAM cell fabrication, wherein planarization is performed before metal formation (and actually before resistor formation).
  • the pre-metal planarization utilizes a sandwich structure comprising permanent SOG, undoped glass, and permanent SOG.
  • the undoped glass is used as a buffer layer between two layers of spin-on-glass to prevent SOG cracks.
  • the double SOG spin enhances the degree of planarization.
  • the disclosed inventions thus provide the advantages of reduced topography at the poly-2 level, and hence more accurate patterning of the poly resistors, and hence a reduced poly-R resistance value by shortening resistor length (less surface contour due to better planarity). This provides more precise manufacturing control which can be used to set speed and power more reliably.
  • FIG. 1 shows a section of a standard 1 Mb SRAM
  • FIG. 2 shows a modification of the structure according to the disclosed innovations.
  • FIG. 3 is a micrograph of a plan view of a standard structure
  • FIG. 4 is a micrograph of a plan view of a comparable structure made according to the disclosed inventions.
  • FIG. 5 is a micrograph of a section view of a standard structure
  • FIG. 6 is a micrograph of a section view of a comparable structure made according to the disclosed inventions.
  • FIG. 7 is a circuit diagram of a 4-transistor 2-resistor MOS SRAM cell.
  • CMOS transistor formation and local interconnect formation in the poly-2 layer, if desired
  • a standard process flow (as shown in FIG. 1 ) would deposit e.g. 1K ⁇ of undoped oxide, spin on e.g. 1.5K ⁇ of SOG, deposit e.g. 1K ⁇ of undoped oxide, deposit and etch a second polysilicon layer to form polysilicon resistors, and then proceed with contact and metal formation.
  • fabrication of the lower poly level(s) is instead followed by:
  • FIG. 3 is a micrograph of a plan view of a standard structure
  • FIG. 4 is a micrograph of a plan view of a comparable structure made according to the disclosed inventions.
  • FIG. 5 is a micrograph of a section view of a standard structure
  • FIG. 6 is a micrograph of a section view of a comparable structure made according to the disclosed inventions.
  • This in turn can be used to provide faster memory operation, since the load resistors can have a greater pullup capability for the same layout area. That is, the reliably greater pullup capability of the load resistors means that the driver and pass transistor dimensions can be selected for faster operation, without risk of upsetting the latch when the pass transistors turn on.
  • FIG. 1 shows a cross-section through a partially fabricated triple-poly 4-T SRAM cell, which has been partially fabricated according to conventional methods.
  • Substrate 100 includes multiple IGFET transistors 110 separated by field oxide 120 .
  • the gates of these NMOS transistors are provided by a first polysilicon layer 130 , which is clad, in the presently preferred embodiment, with a tantalum silicide layer 132 .
  • This composite layer 130 / 132 is referred to herein as the “poly-1” layer.
  • the poly-1 layer 130 / 132 provides gate electrodes for the transistors 110 .
  • the gate oxide which separates the transistor gates from the substrate is too thin. e.g. 100-150 ⁇ , to be shown in this drawing.
  • Sidewall spacers 112 are self-aligned to the poly-1 layer 130 / 132 .
  • a second layer of polysilicon 230 (which, in the presently preferred embodiment, is also clad with a respective tantalum silicide layer 232 ) provides local interconnect within the cell.
  • This composite layer 230 / 232 is referred to herein as the “poly-2” layer.
  • a permanent SOG layer 150 overlaid by an undoped oxide layer 160 , provides some planarization over the poly-2 layer.
  • An additional layer of undoped oxide which is omitted from this drawing for simplicity, underlies the permanent SOG layer 150 .
  • a shared contact in the presently preferred embodiment, provides contacts from poly-1 and poly-2 to active.
  • a third polysilicon layer 330 made of substantially intrinsic polysilicon, provides the polysilicon resistors. (This layer 330 is referred to herein as the “poly-R” layer.) Another shared contact is used to provide contact from this layer to the poly-2 (and poly-1) layers.
  • FIG. 2 shows a cross-section through a partially fabricated triple-poly 4-T SRAM cell, which has been partially fabricated according to the disclosed innovative methods.
  • Elements 100 , 110 , 120 , 130 , 132 , 112 , 230 , 232 , and 150 all are generally the same as the corresponding elements in FIG. 1 .
  • an additional layer of undoped oxide 152 overlies the SOG 150
  • an additional planarizing layer 155 of permanent SOG e.g. P 114 from Allied
  • the disclosed inventions also provide the advantages of reduced topographical excursion for the contact and metal-1 layer, and hence reduced requirements for planarization after the poly-2 layer.
  • the resistors R 1 and R 2 are preferably laid out to have a target resistance value of about 1T ⁇ , but of course this value can be adjusted, by appropriate layout changes, to adjust for speed and power requirements as needed. However, the disclosed innovations permit the resistor value to be specified with greater precision.
  • this material may be doped with chlorine, or may be SIPOS (containing a large fraction of oxygen).

Abstract

A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Description

This application is a continuation of application No. 08/328,736, filed Oct. 25, 1995, which was abandoned upon the filing herein which is a divisional of 08/49,338, filed Dec. 17, 1993, now U.S. Pat. No. 5,395,785.
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit fabrication methods and structures, and particularly to integrated circuits with minimum linewidths below one-half micron.
Background: Planarization
As the degree of integration has advanced, it has become increasingly apparently that it is desirable to minimize the topographical excursion of the surface at each level, especially the upper levels. To accomplish this, various planarization schemes have been used to planarize the inter-level dielectric. Some of these include Chemical-Mechanical-Polishing (CMP), use of Permanent Spin-on-glass (left in place in the final chip), and Sacrificial Etchback Spin-on-glass (SOG).
Spin-on glass deposition is an example of a “sol-gel” process, which has been used in the semiconductor industry for many years. The unprocessed spin-on glass material (available in numerous formulations) is a fluid material (actually a gel). After the liquid material is coated onto the face of a wafer, the wafer is rotated at high speed to throw off the excess material. The surface tension and adhesion of the material provides a flat (planarized) surface with a controlled thickness. The liquid material is then baked, to drive off solvents and provide a stable solid silicate glass. See generally, e.g., Dauksher et al., “Three ‘low Dt’ options for planarizing the pre-metal dielectric on an advanced double poly BiCMOS process,” 139 J.ELECTROCHEM.SOC. 532-536 (1992), which is hereby incorporated by reference.
Background: SRAM Cell Operation
One of the two most common types of SRAM cell is the “4-T” cell, which uses resistive loads. FIG. 7 is a circuit diagram of such a cell (a 4-transistor 2-resistor MOS SRAM cell). In the example shown, the numbering of the bitlines and wordlines indicates that this cell would be in the n-th row and m-th column of an array (or subarray) of memory cells. In this cell, NMOS driver transistors D1 and D2, loaded by resistors R1 and R2, are cross-connected to form a latch. Pass transistors PT1 and PT2 are both accessed by a respective wordline WLn, to connect the two complementary nodes of the latch to a respective complementary pair of bitlines BLm and BLm* when wordline WLn goes high. Thus, in read mode, when wordline WLn goes high, whichever one of the driver transistors (D1 or D2) is ON will pull down one of the bitlines (BLm or BLm*), producing a data signal which can be read. In write mode, the bitlines will be clamped by strong drivers, and the pass transistors PT1 and PT2 will pass enough current to change the state of the latch to correspond to the bitline voltages.
In such a memory cell, the resistors R1 and R2 must pass enough current to offset the leakage currents which tend to discharge the high node of the latch. These resistors are conventionally made from nearly intrinsic polysilicon, and therefore tend to have very high resistance values (which may range from many gigaohms up to teraohms). Unfortunately, the resistivity of such polysilicon is fairly variable, and an excessive value for the resistors may cause the cell to lose data under high-temperature conditions. An excessively low value for the polysilicon resistor may lead to excess static power consumption. Thus, precise control of the resistor values would be highly desirable.
Innovative SRAM Structure and Process
This disclosure describes an improved method of four transistor SRAM cell fabrication, wherein planarization is performed before metal formation (and actually before resistor formation). The pre-metal planarization utilizes a sandwich structure comprising permanent SOG, undoped glass, and permanent SOG. The undoped glass is used as a buffer layer between two layers of spin-on-glass to prevent SOG cracks. The double SOG spin enhances the degree of planarization.
The disclosed inventions thus provide the advantages of reduced topography at the poly-2 level, and hence more accurate patterning of the poly resistors, and hence a reduced poly-R resistance value by shortening resistor length (less surface contour due to better planarity). This provides more precise manufacturing control which can be used to set speed and power more reliably.
BRIEF DESCRIPTION OF THE DRAWING
The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:
FIG. 1 shows a section of a standard 1 Mb SRAM, and FIG. 2 shows a modification of the structure according to the disclosed innovations.
FIG. 3 is a micrograph of a plan view of a standard structure, and
FIG. 4 is a micrograph of a plan view of a comparable structure made according to the disclosed inventions.
FIG. 5 is a micrograph of a section view of a standard structure, and
FIG. 6 is a micrograph of a section view of a comparable structure made according to the disclosed inventions.
FIG. 7 is a circuit diagram of a 4-transistor 2-resistor MOS SRAM cell.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
After completion of CMOS transistor formation (and local interconnect formation in the poly-2 layer, if desired), a standard process flow (as shown in FIG. 1) would deposit e.g. 1KÅ of undoped oxide, spin on e.g. 1.5KÅ of SOG, deposit e.g. 1KÅ of undoped oxide, deposit and etch a second polysilicon layer to form polysilicon resistors, and then proceed with contact and metal formation.
In the innovative process embodiments described, fabrication of the lower poly level(s) is instead followed by:
    • deposition of undoped oxide (not separately shown) to e.g. 1KÅ;
    • Spin-on and cure of SOG 150 (e.g. P112 from Allied) to e.g. 1.5KÅ;
    • deposition of additional undoped oxide 152 to e.g. 500Å;
    • spin-on and cure of additional SOG 155 (e.g. P112 from Allied) to e.g. 1.5KÅ;
    • deposition of additional undoped oxide 160 to e.g. 1KÅ;
    • contact etch (if desired); and
    • deposition and patterning of a top level 330 of polysilicon, to form planar resistors.
    • Processing then continues conventionally with contact and metal formation.
The disclosed inventions thus provide the advantages of reduced topography at the top poly level, and hence more accurate patterning of the poly resistors. A comparison of FIGS. 3 and 4 illustrates this advantage: FIG. 3 is a micrograph of a plan view of a standard structure, and FIG. 4 is a micrograph of a plan view of a comparable structure made according to the disclosed inventions.
The disclosed inventions also provide the advantages of reduced poly-R resistance value by shortening the effective resistor length (since the reduced surface contour leads to better planarity). A comparison of FIGS. 5 and 6 illustrates this advantage: FIG. 5 is a micrograph of a section view of a standard structure, and FIG. 6 is a micrograph of a section view of a comparable structure made according to the disclosed inventions. This in turn can be used to provide faster memory operation, since the load resistors can have a greater pullup capability for the same layout area. That is, the reliably greater pullup capability of the load resistors means that the driver and pass transistor dimensions can be selected for faster operation, without risk of upsetting the latch when the pass transistors turn on.
FIG. 1 shows a cross-section through a partially fabricated triple-poly 4-T SRAM cell, which has been partially fabricated according to conventional methods. (Metallization has been omitted for clarity.) Substrate 100 includes multiple IGFET transistors 110 separated by field oxide 120. The gates of these NMOS transistors are provided by a first polysilicon layer 130, which is clad, in the presently preferred embodiment, with a tantalum silicide layer 132. (This composite layer 130/132 is referred to herein as the “poly-1” layer.) The poly-1 layer 130/132 provides gate electrodes for the transistors 110. (The gate oxide which separates the transistor gates from the substrate is too thin. e.g. 100-150 Å, to be shown in this drawing.) Sidewall spacers 112 are self-aligned to the poly-1 layer 130/132.
A second layer of polysilicon 230 (which, in the presently preferred embodiment, is also clad with a respective tantalum silicide layer 232) provides local interconnect within the cell. (This composite layer 230/232 is referred to herein as the “poly-2” layer.) A permanent SOG layer 150, overlaid by an undoped oxide layer 160, provides some planarization over the poly-2 layer. (An additional layer of undoped oxide, which is omitted from this drawing for simplicity, underlies the permanent SOG layer 150.) A shared contact, in the presently preferred embodiment, provides contacts from poly-1 and poly-2 to active.
A third polysilicon layer 330, made of substantially intrinsic polysilicon, provides the polysilicon resistors. (This layer 330 is referred to herein as the “poly-R” layer.) Another shared contact is used to provide contact from this layer to the poly-2 (and poly-1) layers.
FIG. 2 shows a cross-section through a partially fabricated triple-poly 4-T SRAM cell, which has been partially fabricated according to the disclosed innovative methods. Elements 100, 110, 120, 130, 132, 112, 230, 232, and 150 all are generally the same as the corresponding elements in FIG. 1. However, in the structure of FIG. 2, an additional layer of undoped oxide 152 overlies the SOG 150, and an additional planarizing layer 155 of permanent SOG (e.g. P114 from Allied) overlies the oxide layer 152.
This results in a structure wherein the topographic excursion H2 of the more planar poly-R layer 330′0 provided by the disclosed innovations is much less than the topographic excursion H1 of the poly-R layer 330 of the more conventional structure shown in FIG. 1.
The disclosed inventions also provide the advantages of reduced topographical excursion for the contact and metal-1 layer, and hence reduced requirements for planarization after the poly-2 layer.
The resistors R1 and R2 are preferably laid out to have a target resistance value of about 1TΩ, but of course this value can be adjusted, by appropriate layout changes, to adjust for speed and power requirements as needed. However, the disclosed innovations permit the resistor value to be specified with greater precision.
Further Modifications and Variations
It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts.
While the inventions have been described with primary reference to a 4-T SRAM cell, it will be readily recognized that these inventions can also be applied to other integrated circuits which use resistive loads. Note, however, that the disclosed innovations would not be as applicable to processes which include floating-gate memory cells or poly-to-poly capacitors in the top poly level, since the planarization provided by the disclosed inventions would require additional process complexity to achieve the close coupling from the top poly level to the next lower poly level.
Although the presently preferred embodiment actually uses a triple-poly cell layout, it will be readily recognized that the disclosed ideas can also be adapted for use in a double-poly resistive-load SRAM cell.
Although the resistors are formed from intrinsic polysilicon in the presently preferred embodiment, it will be recognized that a slight amount of doping may be desirable to stabilize the characteristics of this material. For example, this material may be doped with chlorine, or may be SIPOS (containing a large fraction of oxygen).
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.

Claims (34)

1. An integrated circuit SRAM cell, comprising:
a substrate which includes at least one substantially monolithic body of semiconductor material;
a first patterned thin-film layer comprising polysilicon;
a second patterned thin-film layer comprising polysilicon and overlying said first thin-film layer, said second layer being doped to provide high conductivity;
a patterned interlevel dielectric overlying portions of said first and second thin-film layers, said interlevel dielectric including multiple independently planarized layers of dielectric material therein, said multiple independently planarized layers including a lower portion of a spin-on glass a middle portion of a dielectric material which is not spin-on glass, and an upper portion of spin-on glass;
a third patterned thin-film layer comprising substantially undoped polysilicon having a very high resistivity;
wherein said first patterned thin-film layer is configured to provide transistor gates, and said first and second thin-film layers are interconnected to provide an array of latches, and said third thin-film layer overlies said patterned interlevel dielectric and is interconnected through contact holes with said first and second layers to provide resistive loads for each said latch.
2. The integrated circuit of claim 1, wherein said first thin-film layer also comprises a silicide cladding.
3. The SRAM cell of claim 1, wherein said interlevel dielectric comprises two layers of spin-on glass.
4. The SRAM cell of claim 1, wherein said interlevel dielectric also comprises at least two dielectric layers which are not planarized.
5. The SRAM cell of claim 1, wherein said second interlevel dielectric comprises at least four layers.
6. The SRAM cell of claim 1, wherein said loads each have a resistance value of about 1TΩ.
7. An integrated circuit SRAM cell, comprising:
first and second overlaid thin-film conductor layers, each comprising clad polysilicon; , at least one of said conductor layers being capacitively coupled to substantially monolithic semiconductor material to define field-effect transistor channels therein;
a patterned interlevel dielectric overlying portions of said second thin-film layer, and including multiple independently planarized layers of dielectric material therein, said multiple independently planarized layers of dielectric material including at least three different layers of dielectric material, with at least two of said layers of dielectric material being independently planarized layers of pin-on glass;
a third patterned thin-film layer comprising substantially undoped polysilicon having a very high resistivity, and lying on a substantially planar top surface of said patterned interlevel dielectric;
wherein said first patterned thin-film layer is configured to provide transistor gates, and lust first and second thin-film layers are interconnected to provide an array of latches, and said third thin-film layer overlies said patterned interlevel dielectric and is interconnected through contact holes with said first and second layers to provide passive loads for respective ones of said latches.
8. The SRAM cell of claim 7, wherein said interlevel dielectric comprises two layers of spin-on glass.
9. The SRAM cell of claim 7, wherein said interlevel dielectric also comprises at least two dielectric layers which are not planarized.
10. The SRAM cell of claim 7, wherein said interlevel dielectric comprises at least four layers.
11. The SRAM cell of claim 7, wherein said loads each have a resistance value of about 1TΩ.
12. An integrated circuit SRAM cell, comprising:
at least one patterned thin-film conductor layer comprising polysilicon and being capacitively coupled to substantially monolithic semiconductor material to define field-effect transistor channels therein;
a patterned interlevel dielectric overlying said at least one patterned thin-film conductor layers , and including multiple independently planarized layers of dielectric material therein, said multiple independently planarized layers of dielectric material including at least three different layers of dielectric material, with at least two of said layers of dielectric material being independently planarized layers of spin-on glass;
an additional patterned thin-film layer comprising substantially intrinsic polysilicon, and lying on a substantially planar top surface of said patterned interlevel dielectric;
wherein said at least one patterned thin-film conductor layer are is interconnected to provide an array of latches, and said additional thin-film layer overlies said patterned interlevel dielectric and is interconnected through contact holes with said conductor layers to provide passive loads for respective ones of said latches.
13. The SRAM cell of claim 12, wherein said additional layer comprises SIPOS.
14. The SRAM cell of claim 12, wherein said additional layer comprises polysilicon doped with chlorine.
15. The SRAM cell of claim 12, wherein said interlevel dielectric comprises two layers of spin-on glass.
16. The SRAM cell of claim 12, wherein said interlevel dielectric also comprises at least two dielectric layers which are not planarized.
17. The SRAM cell of claim 12, wherein said interlevel dielectric comprises at least four layers.
18. The SRAM cell of claim 12, wherein said loads each have a resistance value of about 1TΩ.
19. The integrated circuit SRAM cell of claim 1 wherein the third patterned thin-film layer comprises substantially undoped polysilicon.
20. The integrated circuit SRAM cell of claim 19 wherein the substantially undoped polysilicon comprises intrinsic polysilicon.
21. The integrated circuit SRAM cell of claim 1 wherein the third patterned thin-film layer comprises a polysilicon layer doped with chlorine.
22. The integrated circuit SRAM cell of claim 7 wherein the third patterned thin-film layer comprises substantially undoped polysilicon.
23. The integrated circuit SRAM cell of claim 22 wherein the third patterned thin-film layer comprises intrinsic polysilicon.
24. The integrated circuit SRAM cell of claim 7 wherein the third patterned thin-film layer comprises a polysilicon layer doped with chlorine.
25. The integrated circuit SRAM cell of claim 12 wherein the third patterned thin-film layer comprises substantially intrinsic polysilicon.
26. An integrated circuit SRAM cell formed in a semiconductor substrate, a plurality of active transistor regions being formed in the substrate, the SRAM cell comprising:
a first conductive layer disposed on the semiconductor substrate, the first conductive layer forming a plurality of respective control nodes for respective transistors in the substrate;
a second conductive layer disposed over the first conductive layer, the second conductive layer being coupled to the first conductive layer and to active transistor regions to interconnect groups of transistors and thereby form respective data latches;
an interlevel dielectric disposed on the second conductive layer and including three different dielectric layers, two of the three dielectric layers being independently planarized spin-on glass layers;
an insulating layer disposed on the interlevel dielectric; and
a third conductive layer formed on the insulating layer, the third conductive layer being coupled to the data latches to form respective resistive loads for the respective latches.
27. An integrated circuit SRAM cell formed in a semiconductor substrate, a plurality of active transistor regions being formed in the substrate, the SRAM cell comprising:
a first conductive layer disposed on the semiconductor substrate, the first conductive layer forming a plurality of respective control nodes for respective transistors in the substrate;
a second conductive layer disposed over the first conductive layer, the second conductive layer being coupled to the first conductive layer and to active transistor regions to interconnect groups of transistors and thereby form respective data latches;
a plurality of independently planarized spin-on glass layers disposed on the second conductive layer;
an insulating layer disposed on a top one of the planarizing spin-on glass layers;
a third conductive layer formed on the insulating layer, the third conductive layer being coupled to the data latches to form respective resistive loads for the respective latches; and
wherein the plurality of independently planarized spin-on glass layers includes a first independently planarized spin-on glass layer disposed on the second conductive layer, an oxide layer disposed on the first spin-on glass layer, and a second independently planarized spin-on glass layer disposed on the oxide layer.
28. The integrated circuit SRAM cell of claim 26 wherein each of the conductive layers comprises a suitably doped polysilicon layer.
29. The integrated circuit SRAM cell of claim 26 wherein the first conductive layer comprises a first polysilicon layer and a cladding layer formed on the first polysilicon layer.
30. The integrated circuit SRAM cell of claim 29 wherein the cladding layer comprises tantalum silicide.
31. The integrated circuit SRAM cell of claim 26 wherein the second conductive layer comprises a second polysilicon layer and a cladding layer formed on the second polysilicon layer.
32. The integrated circuit SRAM cell of claim 31 wherein the cladding layer comprises tantalum silicide.
33. An integrated circuit SRAM cell formed in a semiconductor substrate, a plurality of active transistor regions being formed in the substrate, the SRAM cell comprising:
a first conductive layer disposed on the semiconductor substrate, the first conductive layer forming a plurality of respective control nodes for respective transistors in the substrate;
a second conductive layer disposed over the first conductive layer, the second conductive layer being coupled to the first conductive layer and to active transistor regions to interconnect groups of transistors and thereby form respective data latches;
a plurality of different independently planarized spin-on glass layers disposed on the second conductive layer;
a dielectric layer disposed between two of the independently planarized spin-on glass layers, the dielectric layer being different from the two independently planarized spin-on glass layers;
an undoped oxide layer disposed on a top one of the planarized spin-on glass layers; and
a third conductive layer formed on the insulating layer, the third conductive layer being coupled to the data latches to form respective resistive loads for the respective latches.
34. The integrated circuit SRAM cell of claim 26 wherein the third conductive layer comprises intrinsic polysilicon.
US09/488,686 1993-12-17 2000-01-20 Sram cell fabrication with interlevel Dielectric planarization Expired - Lifetime USRE41670E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/488,686 USRE41670E1 (en) 1993-12-17 2000-01-20 Sram cell fabrication with interlevel Dielectric planarization

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/169,338 US5395785A (en) 1993-12-17 1993-12-17 SRAM cell fabrication with interlevel dielectric planarization
US32873694A 1994-10-25 1994-10-25
US08/781,429 US5710461A (en) 1993-12-17 1997-01-10 SRAM cell fabrication with interlevel dielectric planarization
US09/488,686 USRE41670E1 (en) 1993-12-17 2000-01-20 Sram cell fabrication with interlevel Dielectric planarization

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/781,429 Reissue US5710461A (en) 1993-12-17 1997-01-10 SRAM cell fabrication with interlevel dielectric planarization

Publications (1)

Publication Number Publication Date
USRE41670E1 true USRE41670E1 (en) 2010-09-14

Family

ID=22615253

Family Applications (3)

Application Number Title Priority Date Filing Date
US08/169,338 Expired - Lifetime US5395785A (en) 1993-12-17 1993-12-17 SRAM cell fabrication with interlevel dielectric planarization
US08/781,429 Ceased US5710461A (en) 1993-12-17 1997-01-10 SRAM cell fabrication with interlevel dielectric planarization
US09/488,686 Expired - Lifetime USRE41670E1 (en) 1993-12-17 2000-01-20 Sram cell fabrication with interlevel Dielectric planarization

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US08/169,338 Expired - Lifetime US5395785A (en) 1993-12-17 1993-12-17 SRAM cell fabrication with interlevel dielectric planarization
US08/781,429 Ceased US5710461A (en) 1993-12-17 1997-01-10 SRAM cell fabrication with interlevel dielectric planarization

Country Status (1)

Country Link
US (3) US5395785A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5595917A (en) * 1995-01-31 1997-01-21 Hughes Aircraft Company Method for hydrogen treatment of field effect transistors for use in hermetically sealed packages
US5674773A (en) * 1996-03-15 1997-10-07 Vanguard International Semiconductor Corporation Method for planarizing high step-height integrated circuit structures
US5691247A (en) * 1996-12-19 1997-11-25 Tower Semiconductor Ltd. Method for depositing a flow fill layer on an integrated circuit wafer
TW330334B (en) * 1997-08-23 1998-04-21 Winbond Electronics Corp Static random access memory polysilicon load structure and manufacturing method
US6022788A (en) * 1997-12-23 2000-02-08 Stmicroelectronics, Inc. Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby
US6248638B1 (en) * 1998-12-18 2001-06-19 Texas Instruments Incorporated Enhancements to polysilicon gate
JP2004221234A (en) * 2003-01-14 2004-08-05 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
KR100796654B1 (en) * 2006-06-02 2008-01-22 삼성에스디아이 주식회사 Organic light emitting display and method of manufacturing the same

Citations (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987000828A1 (en) 1985-08-08 1987-02-12 Aktieselskabet Aalborg Portland-Cement-Fabrik A shaped article and a method for producing the article
US4676867A (en) 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
US4797717A (en) * 1986-04-18 1989-01-10 Hitachi, Ltd. Semiconductor memory device
JPS6435044A (en) 1987-07-30 1989-02-06 Mazda Motor Idle rotation controller for engine
JPH0199243A (en) 1987-10-13 1989-04-18 Seiko Epson Corp Semiconductor device
US4920071A (en) 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
JPH02251722A (en) 1989-03-27 1990-10-09 Toshiba Corp Water level sensor
US4975875A (en) 1988-09-13 1990-12-04 Sony Corporation Static random access memory with tri-layer conductor construction over access transistors
US4990998A (en) 1985-06-21 1991-02-05 Hitachi, Ltd. Semiconductor device to prevent out-diffusion of impurities from one conductor layer to another
US5001539A (en) 1988-07-08 1991-03-19 Mitsubishi Denki Kabushiki Kaisha Multiple layer static random access memory device
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices
US5077238A (en) 1988-05-18 1991-12-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with a planar interlayer insulating film
US5083190A (en) 1989-09-05 1992-01-21 Motorola, Inc. Shared gate CMOS transistor
US5110763A (en) 1990-01-29 1992-05-05 Yamaha Corporation Process of fabricating multi-level wiring structure, incorporated in semiconductor device
US5132774A (en) 1990-02-05 1992-07-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including interlayer insulating film
US5151376A (en) 1990-05-31 1992-09-29 Sgs-Thomson Microelectronics, Inc. Method of making polycrystalline silicon resistors for integrated circuits
US5159416A (en) 1990-04-27 1992-10-27 Nec Corporation Thin-film-transistor having schottky barrier
US5169491A (en) 1991-07-29 1992-12-08 Micron Technology, Inc. Method of etching SiO2 dielectric layers using chemical mechanical polishing techniques
US5177238A (en) 1991-07-16 1993-01-05 W. R. Grace & Co.-Conn. Preparation of dialkyl allylphosphonic acid diesters
US5188987A (en) 1989-04-10 1993-02-23 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device using a polishing step prior to a selective vapor growth step
US5204288A (en) 1988-11-10 1993-04-20 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material
US5219792A (en) 1991-01-14 1993-06-15 Samsung Electronics Co., Ltd. Method for forming multilevel interconnection in a semiconductor device
US5290399A (en) * 1991-02-05 1994-03-01 Advanced Micro Devices, Inc. Surface planarizing methods for integrated circuit devices
US5319247A (en) 1990-10-30 1994-06-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an interlayer insulating film of high crack resistance
US5321280A (en) * 1990-09-13 1994-06-14 Nec Corporation Composite semiconductor integrated circuit device
US5373170A (en) 1993-03-15 1994-12-13 Motorola Inc. Semiconductor memory device having a compact symmetrical layout
US5381046A (en) 1990-07-31 1995-01-10 International Business Machines Corporation Stacked conductive resistive polysilicon lands in multilevel semiconductor chips
US5418393A (en) * 1993-11-29 1995-05-23 Motorola, Inc. Thin-film transistor with fully gated channel region
US5496776A (en) * 1995-04-27 1996-03-05 United Microelectronics Corporation Spin-on-glass planarization process with ion implantation
US5521401A (en) * 1992-08-21 1996-05-28 Sgs-Thomson Microelectronics, Inc. P-N junction in a vertical memory cell that creates a high resistance load
US5534731A (en) 1994-10-28 1996-07-09 Advanced Micro Devices, Incorporated Layered low dielectric constant technology
US5549786A (en) * 1995-08-29 1996-08-27 Advanced Micro Devices, Inc. Highly selective, highly uniform plasma etch process for spin-on glass
US5552628A (en) 1990-04-02 1996-09-03 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US5591659A (en) * 1992-04-16 1997-01-07 Fujitsu Limited Process of producing a semiconductor device in which a height difference between a memory cell area and a peripheral area is eliminated
US5593921A (en) * 1991-09-23 1997-01-14 Sgs-Thomson Microelectronics, Inc. Method of forming vias
US5631197A (en) * 1995-08-30 1997-05-20 Taiwan Semiconductor Manufacturing Company, Ltd Sacrificial etchback layer for improved spin-on-glass planarization
US5674784A (en) * 1996-10-02 1997-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming polish stop layer for CMP process
US5702980A (en) * 1996-03-15 1997-12-30 Taiwan Semiconductor Manufacturing Company Ltd Method for forming intermetal dielectric with SOG etchback and CMP
US5717254A (en) * 1993-09-20 1998-02-10 Fujitsu Limited Semiconductor device including a plurality of transistors
US5948700A (en) * 1996-05-20 1999-09-07 Chartered Semiconductor Manufacturing Ltd. Method of planarization of an intermetal dielectric layer using chemical mechanical polishing
US5973349A (en) * 1992-03-13 1999-10-26 Fujitsu Limited Stacked capacitor semiconductor device
US20020017669A1 (en) * 1989-03-20 2002-02-14 Jun Sugiura Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same

Patent Citations (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920071A (en) 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4990998A (en) 1985-06-21 1991-02-05 Hitachi, Ltd. Semiconductor device to prevent out-diffusion of impurities from one conductor layer to another
WO1987000828A1 (en) 1985-08-08 1987-02-12 Aktieselskabet Aalborg Portland-Cement-Fabrik A shaped article and a method for producing the article
US4797717A (en) * 1986-04-18 1989-01-10 Hitachi, Ltd. Semiconductor memory device
US4676867A (en) 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
JPS6435044A (en) 1987-07-30 1989-02-06 Mazda Motor Idle rotation controller for engine
JPH0199243A (en) 1987-10-13 1989-04-18 Seiko Epson Corp Semiconductor device
US5077238A (en) 1988-05-18 1991-12-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with a planar interlayer insulating film
US5001539A (en) 1988-07-08 1991-03-19 Mitsubishi Denki Kabushiki Kaisha Multiple layer static random access memory device
US4975875A (en) 1988-09-13 1990-12-04 Sony Corporation Static random access memory with tri-layer conductor construction over access transistors
US5204288A (en) 1988-11-10 1993-04-20 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material
US20020017669A1 (en) * 1989-03-20 2002-02-14 Jun Sugiura Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same
JPH02251722A (en) 1989-03-27 1990-10-09 Toshiba Corp Water level sensor
US5188987A (en) 1989-04-10 1993-02-23 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device using a polishing step prior to a selective vapor growth step
US5083190A (en) 1989-09-05 1992-01-21 Motorola, Inc. Shared gate CMOS transistor
US5110763A (en) 1990-01-29 1992-05-05 Yamaha Corporation Process of fabricating multi-level wiring structure, incorporated in semiconductor device
US5132774A (en) 1990-02-05 1992-07-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including interlayer insulating film
US5552628A (en) 1990-04-02 1996-09-03 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices
US5159416A (en) 1990-04-27 1992-10-27 Nec Corporation Thin-film-transistor having schottky barrier
US5151376A (en) 1990-05-31 1992-09-29 Sgs-Thomson Microelectronics, Inc. Method of making polycrystalline silicon resistors for integrated circuits
US5381046A (en) 1990-07-31 1995-01-10 International Business Machines Corporation Stacked conductive resistive polysilicon lands in multilevel semiconductor chips
US5321280A (en) * 1990-09-13 1994-06-14 Nec Corporation Composite semiconductor integrated circuit device
US5319247A (en) 1990-10-30 1994-06-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having an interlayer insulating film of high crack resistance
US5219792A (en) 1991-01-14 1993-06-15 Samsung Electronics Co., Ltd. Method for forming multilevel interconnection in a semiconductor device
US5290399A (en) * 1991-02-05 1994-03-01 Advanced Micro Devices, Inc. Surface planarizing methods for integrated circuit devices
US5177238A (en) 1991-07-16 1993-01-05 W. R. Grace & Co.-Conn. Preparation of dialkyl allylphosphonic acid diesters
US5169491A (en) 1991-07-29 1992-12-08 Micron Technology, Inc. Method of etching SiO2 dielectric layers using chemical mechanical polishing techniques
US5593921A (en) * 1991-09-23 1997-01-14 Sgs-Thomson Microelectronics, Inc. Method of forming vias
US5973349A (en) * 1992-03-13 1999-10-26 Fujitsu Limited Stacked capacitor semiconductor device
US5591659A (en) * 1992-04-16 1997-01-07 Fujitsu Limited Process of producing a semiconductor device in which a height difference between a memory cell area and a peripheral area is eliminated
US5521401A (en) * 1992-08-21 1996-05-28 Sgs-Thomson Microelectronics, Inc. P-N junction in a vertical memory cell that creates a high resistance load
US5373170A (en) 1993-03-15 1994-12-13 Motorola Inc. Semiconductor memory device having a compact symmetrical layout
US5717254A (en) * 1993-09-20 1998-02-10 Fujitsu Limited Semiconductor device including a plurality of transistors
US5418393A (en) * 1993-11-29 1995-05-23 Motorola, Inc. Thin-film transistor with fully gated channel region
US5534731A (en) 1994-10-28 1996-07-09 Advanced Micro Devices, Incorporated Layered low dielectric constant technology
US5496776A (en) * 1995-04-27 1996-03-05 United Microelectronics Corporation Spin-on-glass planarization process with ion implantation
US5549786A (en) * 1995-08-29 1996-08-27 Advanced Micro Devices, Inc. Highly selective, highly uniform plasma etch process for spin-on glass
US5631197A (en) * 1995-08-30 1997-05-20 Taiwan Semiconductor Manufacturing Company, Ltd Sacrificial etchback layer for improved spin-on-glass planarization
US5702980A (en) * 1996-03-15 1997-12-30 Taiwan Semiconductor Manufacturing Company Ltd Method for forming intermetal dielectric with SOG etchback and CMP
US5948700A (en) * 1996-05-20 1999-09-07 Chartered Semiconductor Manufacturing Ltd. Method of planarization of an intermetal dielectric layer using chemical mechanical polishing
US5674784A (en) * 1996-10-02 1997-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming polish stop layer for CMP process

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, Hot-Carrier Aging of the MOS Transistor in the Presence of Spin-On Glass as the interlevel Dielectric, by N. Lifshitz and G. Smolinsky, pp. 140-142.
Journal Electrochem. Soc., vol. 139, No. 2, Feb. 1992, Polysilicon Planarization Using Spin-On Glass, by Shrinath Ramaswami and Andrew nagy, pp. 591-599.
Journal Electrochem. Soc., vol. 139, No. 2, Feb. 1992. Three "Lot Dt" Options for Planarizing the Pre-Metal Dielectric on an Advanced Double Poly BiCMOS Process, by W. Dauksher, M. Miller, and C. Tracy, pp. 532-536.
Journal Electronicem. Soc., vol. 140, No. 4, Apr. 1993, The Effect of Plasma Cure Temperature on Spin-On Glass, by Hideo Namatsu and Kazushige Minegishi, pp. 1121-1125.

Also Published As

Publication number Publication date
US5710461A (en) 1998-01-20
US5395785A (en) 1995-03-07

Similar Documents

Publication Publication Date Title
US5536674A (en) Process for forming a static-random-access memory cell
US5485420A (en) Static-random-access memory cell and an integrated circuit having a static-random-access memory cell
US6858504B2 (en) Method for forming gate segments for an integrated circuit
US5757050A (en) Field effect transistor having contact layer of transistor gate electrode material
US5780326A (en) Fully planarized thin film transistor (TFT) and process to fabricate same
US6417045B1 (en) Method of manufacturing a semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity
KR100199258B1 (en) Semiconductor integrated circuit device
US6525399B2 (en) Junctionless antifuses and systems containing junctionless antifuses
US6005296A (en) Layout for SRAM structure
US5612241A (en) Method of manufacturing a DRAM having peripheral circuitry in which source drain interconnection contact of a MOS transistor is made small by utilizing a pad layer
US5381046A (en) Stacked conductive resistive polysilicon lands in multilevel semiconductor chips
US6924525B2 (en) Semiconductor integrated circuit device including memory cell section having capacitor over bitline structure and with the memory and peripheral sections having contact plug structures containing a barrier film and effecting electrical contact with misfets of both memory and peripheral sections
US6037215A (en) Fabricating methods including capacitors on capping layer
US6429474B1 (en) Storage-capacitor electrode and interconnect
US6194262B1 (en) Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors
JPH077084A (en) Semiconductor memory and its manufacture
US6534805B1 (en) SRAM cell design
USRE41670E1 (en) Sram cell fabrication with interlevel Dielectric planarization
US5578854A (en) Vertical load resistor SRAM cell
US6091628A (en) Static random access memory device and method of manufacturing the same
US6040596A (en) Dynamic random access memory devices having improved peripheral circuit resistors therein
US5882997A (en) Method for making devices having thin load structures
US5200356A (en) Method of forming a static random access memory device
US5652174A (en) Unified stacked contact process for static random access memory (SRAM) having polysilicon load resistors
US5285110A (en) Interconnection structure in semiconductor device