USRE40738E1 - Active matrix electroluminescent display and method of operation - Google Patents

Active matrix electroluminescent display and method of operation Download PDF

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USRE40738E1
USRE40738E1 US08447717 US44771795A USRE40738E1 US RE40738 E1 USRE40738 E1 US RE40738E1 US 08447717 US08447717 US 08447717 US 44771795 A US44771795 A US 44771795A US RE40738 E1 USRE40738 E1 US RE40738E1
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transistor
connected
line
data
voltage
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Roger G. Stewart
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Transpacific Infinity LLC
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Transpacific Infinity LLC
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • G09G3/2011Display of intermediate tones by amplitude modulation
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243Details of the generation of driving signals
    • G09G2310/0259Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/027Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • G09G3/2018Display of intermediate tones by time modulation using two or more time intervals

Abstract

An active matrix electroluminescent display (AMELD) having an improved light emitting efficiency and methods of operating the AMELD to produce gray scale operation comprises a plurality of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line and its drain connected to the gate of a second transistor, the second transistor having its source connected to the data line and its drain connected to a first electrode of an electroluminescent (EL) cell. The EL cell's second electrode is connected to alternating high voltage means. A method for producing gray scale performance including the step of varying the length of time the second transistor is on while the alternating voltage is applied to the EL cell is also disclosed.

Description

This invention is an active matrix electroluminescent display (AMELD) having an improved light emitting efficiency and methods of operating the AMELD to produce gray scale operation.

BACKGROUND OF THE INVENTION

Thin film electroluminescent (EL) displays are well known in the art and are used as flat screen displays in a variety of applications. A typical display includes a plurality of picture elements (pixels) arranged in rows and columns. Each pixel comprises an EL phosphor active layer between a pair of insulators and a pair of electrodes.

Early EL displays were only operated in a multiplexed mode. Recently active matrix technology known in the liquid crystal display art has been applied to EL displays. A known AMELD includes a circuit at each pixel comprising a first transistor having its gate connected to a select line, its source connected to a data line and its drain connected to the gate of a second transistor and through a first capacitor 22 to ground. The drain of the second transistor is connected to ground potential, its source is connected through a second capacitor to ground and to one electrode of an EL cell. The second electrode of the EL cell is connected to a high voltage alternating current source for excitation of the phosphor.

This AMELD operates as follows. During a first portion of a frame time (LOAD) all the data lines are sequentially turned ON. During a particular data line ON, the select lines are strobed. On those select lines having a select line voltage, transistor 14 turns on allowing charge from data line 18 to accumulate on the gate of transistor 20 and on capacitor 22, thereby turning transistor 20 on. At the completion of the LOAD cycle the second transistors of all activated pixels are on. During the second portion of the frame time (ILLUMINATE), the AC high voltage source 28 is turned on. Current flow from the source 28 through the EL cells 26 and the transistor 20 ground in each activated pixels, producing an electroluminescent light output from the activated EL cell.

This AMELD and known variants require a number of components at each pixel and do not have gray scale operation. Thus there is a need for alternative AMELDs having fewer components and gray scale operation.

SUMMARY OF THE INVENTION

The invention is an AMELD comprising a plurality of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line and its drain connected to the gate of the second transistor; the second transistor having its source connected to the data line and its drain connected to a first electrode of an electroluminescent (EL) cell and the EL cell having its second electrode connected to means for providing alternating voltage between the second electrode of the EL cell and a source of reference potential. The invention is also a method for producing gray scale performance by varying the length of time that the EL cell of a given pixel is on during the period of high voltage excitation of the pixel array.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a schematic circuit diagram for a pixel of a prior art AMELD.

FIG. 2 is a schematic circuit diagram for a pixel of an AMELD of the invention.

FIG. 2(a) an another embodiment of the AMELD of FIG. 2.

FIG. 3 is a schematic circuit diagram for a pixel of another embodiment of the AMELD of the invention.

FIG. 4 is schematic circuit diagram for a high voltage alternating current source used in the AMELD of the invention.

FIG. 5(a) to (j), is a schematic cross-sectional illustration of steps in a process for forming the active matrix circuitry.

FIG. 6 is a cross-sectional illustration of the structure of an alternative embodiment of the AMELD of the invention.

FIG. 7 depicts an illustrative timing relationship of the signals used for gray scale control of the invention; and

FIG. 8 depicts an illustrative timing relationship of the signals used for digital gray scale control of the invention.

DETAILED DESCRIPTION

In FIG. 1 a prior art AMELD 10 includes a plurality of pixels arranged in rows and columns. The active matrix circuit at a pixel 12, i.e. the pixel in the Ith row and the Jth column comprises a first transistor 14 having its gate connected to a select line 16, its source connected to a data line 18 and its drain connected to the gate of a second transistor 20 and through a first capacitor 22 to ground. The source of transistor 20 is connected to ground, its drain is connected through a second capacitor 24 to ground and to one electrode of an EL cell 26. The second electrode of the EL cell 26 is connected to a high voltage alternating current source 28.

During operation, the 60 Hertz (Hz) field period of a frame is subdivided into separate LOAD and ILLUMINATE periods. During a LOAD period, data is loaded, one at a time, from the data line through transistor 14 allowing charge from data line 18 to accumulate on the gate of transistor 20 and on capacitor 22, in order to control the conduction of transistor 20. At the completion of the LOAD period, the second transistors of all activated pixels are on. During the ILLUMINATE period, the high voltage alternating current source 28 connected to all pixels is turned on. Current flows from the source 28 through the EL cell 26 and the transistor 20 to ground in each activated pixels, producing an electroluminescent light output from the pixel's EL cell.

In FIG. 2, an AMELD 40 includes a plurality of pixels arranged in rows and columns. The active matrix circuit at a pixel 42 comprises a first transistor 44 having its gate connected to a select line 46, its source connected to a data line 48 and its drain connected to the gate of a second transistor 50. A capacitor 51 is preferably connected between the gate of the second transistor 50 and the source of reference potential. The source of transistor 50 is also connected to the data line 48 and its drain connected to one electrode of an EL cell 54. The second electrode of the EL cell 54 is connected to a bus 58 for a single, resonant, 10 kilohertz (KHz)-AC high-voltage power source, such as that shown in FIG. 4, to illuminate the entries array at the same time. Also shown therefore a parasitic capacitor 60 which is between the gate and drain of the transistor 44 therefore is typically present in this structure. Each data line of the AMELD 40 is driven by circuitry including an analog-to-digital converter 62 and a low impedance buffer amplifier 64. Despite its complicated appearance the active matrix circuit actually comprises only a small fraction of the pixel area, even with pixel densities of up to 400 per/cm. An EL call is often shown in series with two capacitors which are the blocking capacitors formed as part of the structure of an EL cell.

In FIG. 2(a) another embodiment of the AMELD 40 of FIG. 2 includes a capacitor 66 connected between the data line 48 and the gate of the transistor 50. Capacitor 51 is preferably present for analog grey scale operation of the AMELD 40. Capacitor 66 or capacitor 51 is preferably present for binary or digital grey scale operation of the AMELD 40.

Images are displayed on the AMELD as a sequence of frames, in either an interlace of progressive scan mode. During operation the frame time is sub-divided into separate LOAD periods such as ILLUMINATE periods. During LOAD periods, data is loaded, one at a time, from the data line through transistor 44 in order to control the conduction of transistor 50. During a particular data line ON, all select lines are strobed. On those select lines having a select line voltage, transistor 44 turns on allowing charge from data line 48 to accumulate on the gate of transistor 50, thereby turning transistor 50 on. At the completion of a LOAD period the second transistors of all activated pixels are on. During the ILLUMINATE period the high voltage AC source 59, connected to all pixels, is turned on. Current flows from the source 59 through the EL cell 54 and the transistor 50 to the data line 48 at each activated pixel, producing an electroluminescence light output from the activated pixel's EL cell.

The low impedance buffer amplifier 64 holds the voltage on the data line 48 at its nominal value during the ILLUMINATE period. The data and select line driver design is straightforward and well known since both data and select lines operate at low (15 V) voltages and low currents of about 0.1 milliampere (0.1 mA). These inexpensive drivers can either be built onto the substrate supporting the AMELD or built externally.

The data which are capacitively stored on the gate of transistor 50 operate through transistor 50 to control whether the pixel will be white, black, or gray. If, for example, the gate of transistor 50 stores a 5 V level (select @ −5 V and data @ 0 V), then transistor 50 will conduct through both the positive and negative transitions of the input voltage at the buss 58, which effectively grounds Node A. This allows all of the displacement current to flow from the input electrode 58 through the EL cell 54, which in turn lights up the pixel. If the gate of transistor 50 stores a −5 V level (select @ −5 V and data @ −5 V), then transistor 50 will remain off through all positive transitions of the input voltage at the input buss 58. Transistor 50 thus behaves like a diode which, in combination with the capacitance associated with the EL cell, will quickly suppress the flow of displacement current through the EL phosphor thereby turning the pixel off.

Accurate gray scale control of each pixel is readily achieved by varying the voltage on the data line during each of the individual (typically 128) ILLUMINATE sub-period during each field of a frame. The voltage variation can be a linear ramp of the voltage, a step function in voltage with each step corresponding to a level of gray or some other function. If, for example, the gate of transistor 50 stores a −1.5 V gray-scale level (select @ −5 V and, Vth=1 V) and the data line is ramped linearly from 5 V to −5 V during the field, then transistor 50 will conduct for precisely 32 of the 128 ILLUMINATE sub-cycles resulting in a time-averaged gray-scale brightness of 25%.

Note that the AMELD pixel always operates digitally even when displaying gray-scale information. All transistors are either fully-on or fully-off and dissipate no power in either state. When a pixel is off, it simply acts as if it is disconnected from the resonant power source and therefore doesn't dissipate or waste any power. The AMELD therefore steers almost 100% of the power from the high voltage source into the activated into the activated EL cells for light generation. FIG. 7 depicts an illustrative timing relationship of the signals used for gray scale control including a frame time, a plurality of LOAD and ILLUMINATE periods, a drive current, data signals, a linear ramp control signal and a stepped control signal.

Another method for providing gray scale control of the AMELD comprises executing, during a frame time, a number of LOAD/ILLUMINATE periods, preferably equal to or less than the number of bits used to define the levels gray. During the LOAD period of the first of these subframes, data corresponding to the least significant bit (LSB) is loaded into the circuitry of each pixel. During the ILLUMINATE period of this subframe, the high voltage source emits a number of pulses NLSB. This procedure is repeated for each subframe up to the one corresponding to the most significant bit, with a greater number of pulses emitted for each more significant bit. For example, for an eight bit gray scale, the high voltage source emits one pulse for the LSB, two pulses for the next most significant bit, four pulses for the next most significant bit and so on, up to 128 pulses for the most significant bit; thereby weighting the excitation of the EL cell and its emission corresponding to the significant of the particular bit. This procedure is equivalent to dividing a frame into a number of subframes, each of which is then operated in a similar way to the procedure outlined above for no gray scale.

These approaches can be combined to handle several bits in one subframe by varying the voltage on the data line. For example, the effect of the LSB and the next LSB could be combined during the first subframe by varying the voltage on the data line to turn the second transistor off after one or three ILLUMINATE pulses.

The second transistor operates as a means for controlling the current through an electroluminescent cell. The gate is either on or off during the ILLUMINATE periods but gray scale information is provided by limiting the total energy supplied to the pixel. This is done by varying the length of time this second transistor is on during the ILLUMINATE period or by varying the number of ILLUMINATE pulses emitted during an ILLUMINATE period. FIG. 8 depicts an illustrative timing relationship of the signals used for digital gray scale control including a frame time, a plurality of LOAD and ILLUMINATE periods, a drive current, data signal and a stepped control signal.

An advantage of the AMELD display is that all pixel transistors may operate during all ILLUMINATE cycles. This reduces the total transistor driver scaling requirements to less than one μA for the AMELD of the invention. Also, the voltage standoff provided by transistor 50 means that the drain of transistor 50 is the only part of this circuit exposed to high voltages. This feature will greatly reduce the cost, improve the yield, and improve the realiability of an AMELD incorporating the principles of the invention.

In FIG. 3, an alternative AMELD 60 includes a plurality of pixels arranged in rows and columns. The active matrix circuit at a pixel 62, i.e. the pixel in the Ith row and the Jth column comprises a first transistor 64 having its gate connected to a select line 66, its source connected to a data line 68 and its drain connected to the gate of a second transistor 70. The drain of transistor 70 is also connected to the select line 66 and its drain connected through a first capacitor 72 to one electrode of an EL cell 74. The second electrode of the EL cell 74 is connected through a second capacitor 76 to a high voltage alternating current source 78.

In FIG. 4, a resonant 10 kHz, AC high voltage power source 100 capable of supplying power to the AMELD of the invention includes an input electrode 102 for receiving low voltage power at the desired pulse rate. A resistor 104 and an EL cell 106 are connected in series through a switch 108 between the electrode 102 and a node 110 which is all of the nodes A shown in FIG. 2. The EL cell 106 is shown as a variable capacitor because it behaves that way in the operation of the AMELD of the invention as discussed above. The input electrode 102 is also connected through an inductor 112 and a switch 114 to a source of reference potential 116. A comparator 118 is connected across the EL cell 106 to the reset input 120 of a set/reset latch 122. Set/reset latch 122 has a set input 124, an initial charge output 126, a bootstrap output 128 and an off output 130. The initial charge output 126, when activated, closes switches 108 and 114. The bootstrap output 128, when activated, open switches 108 and 114 and closes switch 132 which is connected across the input electrode 102, the inductor 112, the switch 108 and the resistor 104; thereby providing a direct connection between the inductor 112 and the input of the EL cell 106. In operation, switches 108 and 114 are initially closed, current flows from input electrode through resistor 104, EL cell 106 and through inductor 112 to reference potential until comparator 118 senses that the preselected voltage on the variable capacitor load 106 has been reached. At this time comparator 118 reaches the latch 122, opening switches 104 and 114 and closing switch 132. Inductor 112 then discharges through switch 132 and drives the voltage on the variable capacitor 106 to a fixed multiple of the preselected voltage. The values of the resistor 104 and the inductor 112 are chosen to provide a multiplication of the voltage applied to the input electrode 102. Preferably, the impedance of the resistor and inductor are such that a large fraction of the energy flows to the inductor. Approximately ninety-five percent of the current would flow into the inductor to achieve a voltage multiplication of twenty.

The AMELD of the invention can be formed using one of several semiconductor processes for the active matrix circuitry. The process which I believe will produce the best performance uses crystalline silicon (x-Si) as the material in which the high voltage transistors are formed. This process comprises forming the high voltage transistors, pixel electrodes an peripheral drive logic in/on the x-Si layer, and depositing the phosphors and other elements of the EL cell.

The key aspect of forming the x-Si layer is the use of the isolated silicon (Si) epitoxy process to produce a layer of high quality Si on a insulating layer as disclosed for exemplary by Salerno et al in the Society For Information Display SID 92 Digest, pages 63-66. x-Si-on-insulator material (x-SOI) is formed by first growing a high quality thermal silicon oxide (SiOx) of the desired thickness on a standard silicon wafer depositing a polycrystalline silicon (poly-Si) layer on the SiOx and capping the poly-Si layer with an SiOx layer. The wafer is then heated to near the melting point of Si and a thin movable strip heater is scanned above the surface of the wafer. The movable heater melts and recrystallizes the Si layer that is trapped between the oxide layers, producing single crystal Si layer. A particular advantage of the x-SOI process is the use of grown SiOx, which can be made as thick as necessary, and much thicker and more dense than ion-implemented SiOx layers.

The circuitry in/on the x-SOI is formed using a high voltage BiCMOS process for the fabrication of BiCMOS devices, such as transistors and peripheral scanners. Results indicate that high voltage (HV) transistors can be fabricated with breakdown voltages of over 100 V in/on 1 μm thick x-SOI. In FIG. 5(a) to (j), the high voltage BiCMOS process, shown schematically, starts with the etching of the Nconductivity type x-SOI layer 200, typically about 1 μm thick, on the dielectric layer 202 into discrete islands 204a, 204b and 204c isolated by oxide 205, forming both the P- and N-wells using masking and ion implantation steps; first of an N-type dopant, such as arsenic, then of a P-type dopant, such as boron, as shown, to form the N-type wells 204a and 204c and the P-type wells 204b. Masks 206, typically formed of SiON, are shown in FIGS. 5(a) and (d). A channel oxide 208 and a thick field oxide 210 and are then grown over the surface of the Si islands to define the active regions, poly-Si is then deposited and defined to form the gate 212 of the high voltage DMOS transistor 214 and the gates 216 of the low voltage CMOS transistors 218. In FIG. 5(f), the gate 212 of the DMOS transistor extends from the active region over the field oxide, forming a field plate 220. The edge of the gate 212 that is over the active region is used as a diffusion edge for the P-channel diffusion 222 while the portion of the gate that is over the field oxide is used to control the electric field in the N-type conductivity drift region 224 of the DMOS transistor 214. The N+-channel source/drain regions 226 are formed using arsenic ion implantation. The P+-channel source/drain regions 228 are then formed using boron ion implantation. The process is completed by depositing a borophosphosilicate glass (BPSG) layer 230 over the structure, flowing the BPSG layer 230, opening vias 232 down to the Si islands 204, and interconnecting the devices using aluminum metallization 234. The process has nine mask steps and permits the fabrication of both DMOS and CMOS transistors.

In operation, the N+-P junction of the DMOS transistor 214 switches on at low voltage causing the transistor to conduct, while the N-N+ junction holds off the voltage applied to the EL cell when the DMOS transistor is not conducting.

The high voltage characteristics of the DMOS transistors depend on several physical dimensions of the device as well as the doping concentrations of both the diffused P-channel and N-well drift region. The total channel length for a 300 V transistor is typically about 30 μm. The important physical dimensions are the length of the N-well drift region, typically about 30 μm, the spacing between the edge of the poly-Si gate in the active region and the edge of the underlying field oxide, typically about 4 μm, and the amount of overlap, typically about 6 μm, between the poly-Si gate over the field oxide and the edge of the field oxide. The degree of current handling in the DMOS transistor is also a function of some of these parameters as well as a function of the overall size of the transistor. Since a high density AMELD having about 400 pixels/cm is desirable, the pixel area (and hence the transistors) must be kept as small as possible. In some cases, however, the conditions that produce high voltage performance also reduce the overall current handling capability of the transistor and therefore require a large transistor area for a given current specification. For example, the N-well doping concentration controls the maximum current and breakdown voltage inversely, usually making careful optimization necessary. However, this is much less of a factor in this approach, since the design eliminates the requirement for high current (only 1 μA/pixel needed).

The layer thicknesses can be adjusted to provide the required breakdown voltages and isolation levels for the transistors in the AMELD. High quality thermal SiOx can be easily grown to the required thickness. This tailoring cannot be obtained easily or economically by other techniques. This x-SOI is characterized by high crystal quality and excellent transistors. A second advantage of the x-SOI process is the substrate removal process. Owing to the tailoring of the oxide layer beneath the Si layer, the substrate can be removed using lift-off techniques, and the resultant thin layer can be remounted on a variety of substrates such as glass, lexan, or other materials.

The process for forming the EL cell, whether monochrome or color, begins with the formation of the active matrix circuitry. The next steps are sequentially depositing the bottom electrode, which is preferably the source or drain metallization of the second transistor in the pixel circuit, the bottom insulating layer, the phosphor layer and the top insulating layer. The top insulating layers are then patterned to expose the connection points between the top electrodes and the active matrix, and also to remove material from the areas to which external connections will be made to the driver logic. The top transparent electrode, typically indium tin oxide, is then deposited and patterned. This step also serves to complete the circuit between the phosphors and the active matrix.

The process for forming a color phosphor layer comprises depositing and patterning the first phosphor, depositing an etch stop layer, depositing and patterning the second phosphor, depositing a second etch stop layer, and depositing and patterning the third phosphor. This array of patterned phosphors is then coated with the top insulator. Tuenge et al in U.S. Pat. No. 4,954,747 have disclosed a multicolor EL display including a blue SrS:CeF3 or ZnS:Tm phosphor or a group II metal thiogallate doped with cerium, a green ZnS:TbF3 phosphor and a red phosphor formed from the combination of ZnS:Mn phosphor and a filter. The filter is a red polyimide or CdSSe filter, preferably CdS0.62Se0.38, formed over the red pixels, or alternatively, incorporated on the seal cover plate if a cover is used. The red filter transmits the desired red portion of the ZnS:Mn phosphor (yellow) output to produce the desired red color. These phosphors and filters are formed sequentially using well known deposition, patterning and etching techniques.

The insulating layers may be Al2O3, SiO2, SiON or BaTa2O6 or the like between about 10 and 80 nanometers (nm) thick. The dielectric layers may be Si3N4 or SiON. The presence of the insulating oxide layers improves the adhesion of the Si3N4 layers. The dielectric layers are formed by sputtering, plasma CVD or the like and the insulating oxide layers by electron beam evaporation, sputtering, CVD or the like. The processing temperature for the insulator deposition steps is about 500° C. The silicon wafer is exposed to a maximum temperature during processing would be 750° C. which is necessary to anneal the blue phosphor.

An alternative process to form the AMELD of the invention when a large area display is desired includes forming the transistors in amorphous silicon (a-Si) or poly-Si, although a-Si is preferred because better high voltage devices can presently be fabricated in a-Si as disclosed, for example, by Suzuki et al in the Society For Information Display SID 92 Digest, pages 344-347. In this case, whether a-Si or poly-Si is used, the process of forming the AMELD is reversed; the EL cell is first formed on a transparent substrate and the transistors are formed on the EL cell. In FIG. 6 an AMELD 300 incorporating a-Si transistors includes a transparent substrate 302, a transparent electrode 304, a first insulating layer 306, an EL phosphor layer 308 patterned as described above, a second insulating layer 310, a back electrode 312 and an isolation layer 314. The active matrix circuitry is formed on the isolation layer 314 in/on a a-Si island 316 deposited using standard glow discharge in silane techniques and isolated from adjacent islands using standard masking and etching techniques to define the pixels along with the segmentation of the back electrode 312. It is understood that the pixels can equally well defined by segmenting the transparent electrode 304.

The first transistor 318 includes a gate 320 overlying a gate oxide 322 and connected to a select line 324, a source region 326 connected by a data line bus 328, a drain region 330 connected by conductor 332 to a gate 334 overlying a gate oxide 336 of a second transistor 338. The second transistor 336 has a source region 340 contacted to the data line bus 328 and a drain region 342 connected by conductor 344 through opening 346 to the back electrode 312. The entire assembly is sealed by depositing a layer of an insulator 348 composed of a material such as BPSG.

It is to be understood that the apparatus and the method of operation taught herein are illustrative of the general principles of the invention. Modifications may readily be devised by those skilled in the art without departing from the spirit and scope of the invention. For example, different layouts of the components in a pixel are possible. Still further, the invention is not restricted to a particular type of high voltage excitation and pulse shape, to a particular type of power source or its capacity to a particular transistor type. The system provided by the invention is not restricted to operation at a particular frequency.

Claims (21)

1. An electroluminescent display comprising an array of pixels, each pixel including
a first transistor having its gate connected to a select line, its source connected to a data line and its drain connected to the gate of a second transistor;
the second transistor having it source connected to the data line and its drain connected to a first electrode of an electroluminescent cell; and
said electroluminescent cell having a second electrode which is connected to means for providing an alternating voltage power source with the voltage power source means being connected between the second electrode and a source of reference potential.
2. The display of claim 1 wherein the means for providing an alternating voltage power source comprises a resonant alternating current high voltage power source.
3. The display of claim 2 wherein the power source includes:
first means for receiving an input voltage;
a resistor connected at one end and in series through a first switch to the first means and at another end to the second electrode of the electroluminescent cell;
an inductor connected to the first means and in series through a second switch to a source of reference potential;
a third switch connected across the first means, the inductor, the first switch and the resistor;
a comparator having an input connected to the second electrode of the electroluminescent cell and its output connected to an input of a set/reset latch, the latch having a second input, and first and second outputs;
wherein the first output of the latch, when activated, closes the first and second switches, the second output of the latch, when activated opens the first and second switches and closes the third switch;
wherein the values of the resistor and the inductor are chosen to provide a multiplication of the voltage applied to the first means.
4. The display of claim 1 wherein the second transistor is a drift type MOS transistor.
5. The display of claim 4 further comprising a capacitor connected between the gate of the second transistor and a source of reference potential.
6. The display of claim 4 further comprising a capacitor connected between said data line and the gate of the second transistor.
7. A method of operating an active matrix electroluminescent display, said display comprising a plurality of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line and its drain connected to the gate of a second transistor; the second transistor having its source connected to the date line and its drain connected to a first electrode of an electroluminescence cell, the electroluminescent cell having a second electrode, the method comprising the steps of
applying voltages to the select and data lines to enable the second transistor of a given pixel;
applying a power source to the second electrode of the electroluminescent cell of the given pixel for a period of time; and
disabling the second transistor of the given pixel prior to the conpletion of said period of time.
8. In an electroluminescent display comprising an array of pixels, where each pixel contains a circuit for controlling application of energy to an electroluminescent cell associated with each pixel in said array of pixels, a method of providing gray scale illumination during a frame time comprising the steps of:
subdividing said frame time into a plurality of LOAD periods and a plurality of ILLUMINATE periods;
loading, during each LOAD period, data from a data line into said circuit; and
varying, during each of said ILLUMINATE periods, a voltage on the data line, to selectively illuminate said electroluminescent cell in response to said voltage and said data.
9. The method of claim 8 wherein said voltage on said data line is a linear ramp.
10. The method of claim 8 wherein said voltage on said data line is a step function.
11. The method of claim 8 wherein, during each ILLUMINATE period, a high voltage power supply applies at least one pulse to said circuit and, in response to said voltage, said at least one pulse is applied to said electroluminescent cell.
12. An electroluminescent display comprising an array of pixels for providing gray scale illumination during a frame time, where said frame time is divided into a number of LOAD and ILLUMINATE periods, each pixel comprising:
a first transistor and a second transistor;
said first transistor having a first transistor gate, a first transistor source and a first transistor drain, where said first transistor gate is connected to a select line, said first transistor source is connected to a data line and said first transistor drain is connected to a second transistor gate of said second transistor;
said second transistor having said second transistor gate, a second transistor source and a second transistor drain, where said second transistor source is connected to said data line and second transistor drain is connected to an electroluminescent cell;
during each of said LOAD periods and when a select line signal on the select line activates the first transistor, said data line supplies, through said first transistor, a data signal to the second transistor gate where said data signal is stored; and
during each of said ILLUMINATE periods, said data line supplies a voltage to said second transistor to control illumination of said electroluminescent cell.
13. The display of claim 12 wherein said voltage is a linear ramp.
14. The display of claim 12 wherein said voltage is a step function.
15. An electroluminescent display comprising an array of pixels for providing gray scale illumination during a frame time, where said frame time is divided into a number of LOAD and ILLUMINATE periods, each pixel comprising:
a control circuit, connected to a select line, a data line and a first electrode of an electroluminescent cell, for selectively applying energy to said electroluminescent cell in response to signals carried by said select line and said data line;
during each of said LOAD periods and when a select line signal on the select line activates the control circuit, said data line supplies a data signal to the control circuit where said data signal is stored; and
during each of said ILLUMINATE periods, in response to a state of said stored data signal, said control circuit applies pulsed energy from a power supply means to a second electrode of said electroluminescent cell for a particular period of time.
16. The display of claim 15 wherein a number of ILLUMINATE periods and LOAD periods that are used to illuminate said electroluminescent cell during a frame time is equivalent to a number of bits used to define a number of levels of gray.
17. The display of claim 15 wherein said control circuit further comprises:
a first transistor and a second transistor;
said first transistor having a first transistor gate, a first transistor source and a first transistor drain, where said first transistor gate is connected to a select line, said first transistor source is connected to a data line and said first transistor drain is connected to a second transistor gate of said second transistor; and
said second transistor having said second transistor gate, a second transistor source and a second transistor drain, where said second transistor source is connected to said data line and second transistor drain is connected to a first electrode of an electroluminescent cell.
18. The display of claim 15 wherein a number of ILLUMINATE periods and LOAD periods that are used to illuminate said electroluminescent cell during a frame time is equivalent to a number of bits used to define a number of levels of gray.
19. An electroluminescent display comprising an array of pixels, each pixel comprising:
a first transistor, a second transistor and an electroluminescent cell;
said first transistor having a first transistor gate connected to a select line, a first transistor source connected to a data line, and a first transistor drain connected to a second transistor gate of said second transistor;
said second transistor having a second transistor source connected to said select line and a second transistor drain coupled to a first electrode of said electroluminescent cell; and
said electroluminescent cell having a second electrode coupled to means for providing an alternating current to the electroluminescent cell.
20. The display of claim 19 further comprising:
a first capacitor, connected between said second transistor drain and said first electrode of said electroluminescent cell, for coupling said second transistor to said electroluminescent cell.
21. The display of claim 19, further comprising:
a second capacitor, connected between said second electrode of said electroluminescent cell and said means for providing an alternating current, for coupling said electroluminescent cell to said means for providing alternating current.
US08447717 1992-06-02 1995-05-23 Active matrix electroluminescent display and method of operation Expired - Lifetime USRE40738E1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060273995A1 (en) * 1997-02-17 2006-12-07 Seiko Epson Corporation Display apparatus

Families Citing this family (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7071910B1 (en) 1991-10-16 2006-07-04 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device and method of driving and manufacturing the same
JP2784615B2 (en) * 1991-10-16 1998-08-06 株式会社半導体エネルギー研究所 Electro-optical display device and a driving method
US6759680B1 (en) 1991-10-16 2004-07-06 Semiconductor Energy Laboratory Co., Ltd. Display device having thin film transistors
US7253440B1 (en) * 1991-10-16 2007-08-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having at least first and second thin film transistors
JPH07140441A (en) * 1993-06-25 1995-06-02 Hosiden Corp Method for driving active matrix liquid crystal display element
JPH0728431A (en) * 1993-07-13 1995-01-31 Sharp Corp Transmission circuit and transmission system of display signal for liquid crystal display
US6943764B1 (en) 1994-04-22 2005-09-13 Semiconductor Energy Laboratory Co., Ltd. Driver circuit for an active matrix display device
US5714968A (en) * 1994-08-09 1998-02-03 Nec Corporation Current-dependent light-emitting element drive circuit for use in active matrix display device
US5463279A (en) * 1994-08-19 1995-10-31 Planar Systems, Inc. Active matrix electroluminescent cell design
US5587329A (en) * 1994-08-24 1996-12-24 David Sarnoff Research Center, Inc. Method for fabricating a switching transistor having a capacitive network proximate a drift region
JPH08129360A (en) * 1994-10-31 1996-05-21 Semiconductor Energy Lab Co Ltd Electroluminescence display device
US5652600A (en) * 1994-11-17 1997-07-29 Planar Systems, Inc. Time multiplexed gray scale approach
US5576726A (en) * 1994-11-21 1996-11-19 Motorola Electro-luminescent display device driven by two opposite phase alternating voltages and method therefor
US6853083B1 (en) 1995-03-24 2005-02-08 Semiconductor Energy Laboratory Co., Ltd. Thin film transfer, organic electroluminescence display device and manufacturing method of the same
US5594305A (en) * 1995-06-07 1997-01-14 Texas Instruments Incorporated Power supply for use with switched anode field emission display including energy recovery apparatus
US5644327A (en) * 1995-06-07 1997-07-01 David Sarnoff Research Center, Inc. Tessellated electroluminescent display having a multilayer ceramic substrate
US5877735A (en) * 1995-06-23 1999-03-02 Planar Systems, Inc. Substrate carriers for electroluminescent displays
US5959598A (en) * 1995-07-20 1999-09-28 The Regents Of The University Of Colorado Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images
US5767623A (en) * 1995-09-11 1998-06-16 Planar Systems, Inc. Interconnection between an active matrix electroluminescent display and an electrical cable
US5793342A (en) * 1995-10-03 1998-08-11 Planar Systems, Inc. Resonant mode active matrix TFEL display excitation driver with sinusoidal low power illumination input
FR2745410B1 (en) * 1996-02-27 1998-06-05 Thomson Csf A method of controlling an image display screen displaying half-tones, and display device embodying the METHOD
DE69739633D1 (en) * 1996-11-28 2009-12-10 Casio Computer Co Ltd display device
US5990629A (en) * 1997-01-28 1999-11-23 Casio Computer Co., Ltd. Electroluminescent display device and a driving method thereof
US6462722B1 (en) * 1997-02-17 2002-10-08 Seiko Epson Corporation Current-driven light-emitting display apparatus and method of producing the same
US6147362A (en) * 1997-03-17 2000-11-14 Honeywell International Inc. High performance display pixel for electronics displays
US6229506B1 (en) 1997-04-23 2001-05-08 Sarnoff Corporation Active matrix light emitting diode pixel structure and concomitant method
KR20050084509A (en) * 1997-04-23 2005-08-26 사르노프 코포레이션 Active matrix light emitting diode pixel structure and method
US6175345B1 (en) * 1997-06-02 2001-01-16 Canon Kabushiki Kaisha Electroluminescence device, electroluminescence apparatus, and production methods thereof
JP3840746B2 (en) * 1997-07-02 2006-11-01 ソニー株式会社 The image display apparatus and image display method
JP3520396B2 (en) * 1997-07-02 2004-04-19 セイコーエプソン株式会社 Active matrix substrate and the display device
JP3580092B2 (en) * 1997-08-21 2004-10-20 セイコーエプソン株式会社 Active matrix display device
CN101068025B (en) * 1997-08-21 2010-05-12 精工爱普生株式会社 Display device
JPH1173158A (en) * 1997-08-28 1999-03-16 Seiko Epson Corp Display element
JPH1175166A (en) * 1997-08-29 1999-03-16 Sony Corp Superimposition method and device for additional information to video signal
US6069597A (en) * 1997-08-29 2000-05-30 Candescent Technologies Corporation Circuit and method for controlling the brightness of an FED device
US6229508B1 (en) 1997-09-29 2001-05-08 Sarnoff Corporation Active matrix light emitting diode pixel structure and concomitant method
US6049324A (en) * 1997-10-30 2000-04-11 Lear Automotive Dearborn, Inc. Memory configuration for gray shade ELD using on/off drivers
US6266035B1 (en) * 1997-10-30 2001-07-24 Lear Automotive Dearborn, Inc. ELD driver with improved brightness control
US6034659A (en) * 1998-02-02 2000-03-07 Wald; Steven F. Active matrix electroluminescent grey scale display
US6498592B1 (en) 1999-02-16 2002-12-24 Sarnoff Corp. Display tile structure using organic light emitting materials
US6897855B1 (en) 1998-02-17 2005-05-24 Sarnoff Corporation Tiled electronic display structure
GB9812742D0 (en) * 1998-06-12 1998-08-12 Philips Electronics Nv Active matrix electroluminescent display devices
US6188375B1 (en) 1998-08-13 2001-02-13 Allied Signal Inc. Pixel drive circuit and method for active matrix electroluminescent displays
US6348906B1 (en) * 1998-09-03 2002-02-19 Sarnoff Corporation Line scanning circuit for a dual-mode display
US6417825B1 (en) * 1998-09-29 2002-07-09 Sarnoff Corporation Analog active matrix emissive display
US6278423B1 (en) 1998-11-24 2001-08-21 Planar Systems, Inc Active matrix electroluminescent grey scale display
US6191535B1 (en) * 1998-11-27 2001-02-20 Sanyo Electric Co., Ltd. Electroluminescence display apparatus
US6777716B1 (en) * 1999-02-12 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device and method of manufacturing therefor
US6515641B1 (en) * 1999-02-25 2003-02-04 Canon Kabushiki Kaisha Image display apparatus and method of driving image display apparatus
US6306694B1 (en) * 1999-03-12 2001-10-23 Semiconductor Energy Laboratory Co., Ltd. Process of fabricating a semiconductor device
US6512504B1 (en) 1999-04-27 2003-01-28 Semiconductor Energy Laborayory Co., Ltd. Electronic device and electronic apparatus
JP4627822B2 (en) * 1999-06-23 2011-02-09 株式会社半導体エネルギー研究所 Display device
US6777254B1 (en) 1999-07-06 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
JP4727030B2 (en) 1999-10-21 2011-07-20 株式会社半導体エネルギー研究所 Display device
KR100678700B1 (en) 1999-11-30 2007-02-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 An electric device
GB0000290D0 (en) * 2000-01-07 2000-03-01 Koninkl Philips Electronics Nv Active matrix electroluminescent display device
JP4212079B2 (en) * 2000-01-11 2009-01-21 ローム株式会社 Display device and a driving method
US7688290B2 (en) 2000-01-17 2010-03-30 Semiconductor Energy Laboratory Co., Ltd. Display system and electrical appliance
KR100566813B1 (en) * 2000-02-03 2006-04-03 엘지.필립스 엘시디 주식회사 Circuit for Electro Luminescence Cell
JP4798874B2 (en) * 2000-05-08 2011-10-19 株式会社半導体エネルギー研究所 El display device and electric instrument using the same
JP3475938B2 (en) * 2000-05-26 2003-12-10 セイコーエプソン株式会社 Method of driving an electro-optical device, a driving circuit of an electro-optical device, an electro-optical device and electronic apparatus
US6995753B2 (en) * 2000-06-06 2006-02-07 Semiconductor Energy Laboratory Co., Ltd. Display device and method of manufacturing the same
CN1251333C (en) * 2000-06-12 2006-04-12 株式会社半导体能源研究所 Luminous module and drive method for said same and optical detector
US6879110B2 (en) 2000-07-27 2005-04-12 Semiconductor Energy Laboratory Co., Ltd. Method of driving display device
US6774876B2 (en) 2000-10-02 2004-08-10 Semiconductor Energy Laboratory Co., Ltd. Self light emitting device and driving method thereof
US8339339B2 (en) * 2000-12-26 2012-12-25 Semiconductor Energy Laboratory Co., Ltd. Light emitting device, method of driving the same, and electronic device
JP4599743B2 (en) * 2001-03-30 2010-12-15 日本電気株式会社 Hold-type display device, a display, a monitor, a light valve and projector
US6809482B2 (en) 2001-06-01 2004-10-26 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of driving the same
US7283111B2 (en) * 2001-08-03 2007-10-16 Semiconductor Energy Laboratory Co., Ltd. Display device and method of driving thereof
JP3899886B2 (en) 2001-10-10 2007-03-28 株式会社日立製作所 Image display device
US7167169B2 (en) * 2001-11-20 2007-01-23 Toppoly Optoelectronics Corporation Active matrix oled voltage drive pixel circuit
JP3973471B2 (en) * 2001-12-14 2007-09-12 三洋電機株式会社 Digital driving display device
CN100409290C (en) 2001-12-14 2008-08-06 三洋电机株式会社 Digitally driven type display device
KR100870004B1 (en) * 2002-03-08 2008-11-21 삼성전자주식회사 Organic electroluminescent display and driving method thereof
JP3972359B2 (en) * 2002-06-07 2007-09-05 カシオ計算機株式会社 Display device
GB0224277D0 (en) * 2002-10-18 2002-11-27 Koninkl Philips Electronics Nv Electroluminescent display devices
KR100489802B1 (en) 2002-12-18 2005-05-16 한국전자통신연구원 Structure of high voltage device and low voltage device, and method of manufacturing the same
JP4574127B2 (en) 2003-03-26 2010-11-04 株式会社半導体エネルギー研究所 Element substrate and a light-emitting device
US20050007316A1 (en) * 2003-05-15 2005-01-13 Hajime Akimoto Image display device
JP2004361753A (en) 2003-06-05 2004-12-24 Chi Mei Electronics Corp Image display device
US7075225B2 (en) * 2003-06-27 2006-07-11 Tajul Arosh Baroky White light emitting device
US8537081B2 (en) 2003-09-17 2013-09-17 Hitachi Displays, Ltd. Display apparatus and display control method
US7310077B2 (en) * 2003-09-29 2007-12-18 Michael Gillis Kane Pixel circuit for an active matrix organic light-emitting diode display
US7633470B2 (en) 2003-09-29 2009-12-15 Michael Gillis Kane Driver circuit, as for an OLED display
JP2005275315A (en) * 2004-03-26 2005-10-06 Semiconductor Energy Lab Co Ltd Display device, driving method therefor, and electronic equipment using the same
US7502040B2 (en) * 2004-12-06 2009-03-10 Semiconductor Energy Laboratory Co., Ltd. Display device, driving method thereof and electronic appliance
US20060139265A1 (en) * 2004-12-28 2006-06-29 Semiconductor Energy Laboratory Co., Ltd. Driving method of display device
US20060158399A1 (en) 2005-01-14 2006-07-20 Semiconductor Energy Laboratory Co., Ltd. Driving method of display device
JP4782103B2 (en) 2005-02-25 2011-09-28 京セラ株式会社 Image display device
US7719526B2 (en) 2005-04-14 2010-05-18 Semiconductor Energy Laboratory Co., Ltd. Display device, and driving method and electronic apparatus of the display device
US8633919B2 (en) * 2005-04-14 2014-01-21 Semiconductor Energy Laboratory Co., Ltd. Display device, driving method of the display device, and electronic device
EP1720148A3 (en) 2005-05-02 2007-09-05 Semiconductor Energy Laboratory Co., Ltd. Display device and gray scale driving method with subframes thereof
KR101404582B1 (en) * 2006-01-20 2014-06-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Driving method of display device
US20070215883A1 (en) * 2006-03-20 2007-09-20 Dixon Michael J Electroluminescent Devices, Subassemblies for use in Making Electroluminescent Devices, and Dielectric Materials, Conductive Inks and Substrates Related Thereto
US20100117153A1 (en) * 2008-11-07 2010-05-13 Honeywell International Inc. High voltage soi cmos device and method of manufacture
JP5170027B2 (en) * 2009-08-07 2013-03-27 エプソンイメージングデバイス株式会社 Display device and electronic equipment
JP5909759B2 (en) * 2011-09-07 2016-04-27 株式会社Joled Pixel circuits, display panel, display device and electronic apparatus

Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3590156A (en) 1968-08-28 1971-06-29 Zenith Radio Corp Flat panel display system with time-modulated gray scale
US3761617A (en) 1970-06-20 1973-09-25 Matsushita Electric Ind Co Ltd Dc electroluminescent crossed-grid panel with digitally controlled gray scale
US4006383A (en) 1975-11-28 1977-02-01 Westinghouse Electric Corporation Electroluminescent display panel with enlarged active display areas
US4087792A (en) 1977-03-03 1978-05-02 Westinghouse Electric Corp. Electro-optic display system
US4114070A (en) 1977-03-22 1978-09-12 Westinghouse Electric Corp. Display panel with simplified thin film interconnect system
US4193095A (en) 1977-02-25 1980-03-11 Hitachi, Ltd. Driver system of memory type gray-scale display panel
US4482841A (en) 1982-03-02 1984-11-13 Texas Instruments Incorporated Composite dielectrics for low voltage electroluminescent displays
US4528480A (en) 1981-12-28 1985-07-09 Nippon Telegraph & Telephone AC Drive type electroluminescent display device
US4532506A (en) 1981-10-30 1985-07-30 Hitachi, Ltd. Matrix display and driving method therefor
US4554539A (en) 1982-11-08 1985-11-19 Rockwell International Corporation Driver circuit for an electroluminescent matrix-addressed display
US4602192A (en) 1983-03-31 1986-07-22 Matsushita Electric Industrial Co., Ltd. Thin film integrated device
US4613793A (en) 1984-08-06 1986-09-23 Sigmatron Nova, Inc. Light emission enhancing dielectric layer for EL panel
US4652872A (en) 1983-07-07 1987-03-24 Nec Kansai, Ltd. Matrix display panel driving system
US4736137A (en) 1986-08-01 1988-04-05 Hitachi, Ltd Matrix display device
US4797667A (en) 1985-04-30 1989-01-10 Planar Systems, Inc. Split screen electrode structure for TFEL panel
US4954747A (en) 1988-11-17 1990-09-04 Tuenge Richard T Multi-colored thin-film electroluminescent display with filter
US4958105A (en) 1988-12-09 1990-09-18 United Technologies Corporation Row driver for EL panels and the like with inductance coupling
US4962374A (en) 1985-12-17 1990-10-09 Sharp Kabushiki Kaisha Thin film el display panel drive circuit
US4963861A (en) 1986-12-22 1990-10-16 Etat Francais represente par le Ministre des Postes et Telecommunications Centre National Electroluminescent memory display having multi-phase sustaining voltages
US4975691A (en) 1987-06-16 1990-12-04 Interstate Electronics Corporation Scan inversion symmetric drive
US5003302A (en) 1984-10-17 1991-03-26 Centre National D'etudes Des Telecommunications Dual addressing transistor active matrix display screen
US5028916A (en) 1984-09-28 1991-07-02 Kabushiki Kaisha Toshiba Active matrix display device
US5063378A (en) 1989-12-22 1991-11-05 David Sarnoff Research Center, Inc. Scanned liquid crystal display with select scanner redundancy
EP0457440A2 (en) 1990-05-14 1991-11-21 Cherry Display Products Corporation Grey scale display
US5079483A (en) 1989-12-15 1992-01-07 Fuji Xerox Co., Ltd. Electroluminescent device driving circuit
US5095248A (en) 1989-11-24 1992-03-10 Fuji Xerox Co., Ltd. Electroluminescent device driving circuit
US5172032A (en) 1992-03-16 1992-12-15 Alessio David S Method of and apparatus for the energization of electroluminescent lamps
US5262766A (en) * 1990-09-19 1993-11-16 Sharp Kabushiki Kaisha Display unit having brightness control function
US5559402A (en) * 1994-08-24 1996-09-24 Hewlett-Packard Company Power circuit with energy recovery for driving an electroluminescent device
US5576601A (en) * 1991-10-11 1996-11-19 Norand Corporation Drive circuit for electroluminescent panels and the like

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5172034A (en) * 1990-03-30 1992-12-15 The Softube Corporation Wide range dimmable fluorescent lamp ballast system

Patent Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3590156A (en) 1968-08-28 1971-06-29 Zenith Radio Corp Flat panel display system with time-modulated gray scale
US3761617A (en) 1970-06-20 1973-09-25 Matsushita Electric Ind Co Ltd Dc electroluminescent crossed-grid panel with digitally controlled gray scale
US4006383A (en) 1975-11-28 1977-02-01 Westinghouse Electric Corporation Electroluminescent display panel with enlarged active display areas
US4193095A (en) 1977-02-25 1980-03-11 Hitachi, Ltd. Driver system of memory type gray-scale display panel
US4087792A (en) 1977-03-03 1978-05-02 Westinghouse Electric Corp. Electro-optic display system
US4114070A (en) 1977-03-22 1978-09-12 Westinghouse Electric Corp. Display panel with simplified thin film interconnect system
US4532506A (en) 1981-10-30 1985-07-30 Hitachi, Ltd. Matrix display and driving method therefor
US4528480A (en) 1981-12-28 1985-07-09 Nippon Telegraph & Telephone AC Drive type electroluminescent display device
US4482841A (en) 1982-03-02 1984-11-13 Texas Instruments Incorporated Composite dielectrics for low voltage electroluminescent displays
US4554539A (en) 1982-11-08 1985-11-19 Rockwell International Corporation Driver circuit for an electroluminescent matrix-addressed display
US4602192A (en) 1983-03-31 1986-07-22 Matsushita Electric Industrial Co., Ltd. Thin film integrated device
US4652872A (en) 1983-07-07 1987-03-24 Nec Kansai, Ltd. Matrix display panel driving system
US4613793A (en) 1984-08-06 1986-09-23 Sigmatron Nova, Inc. Light emission enhancing dielectric layer for EL panel
US5028916A (en) 1984-09-28 1991-07-02 Kabushiki Kaisha Toshiba Active matrix display device
US5003302A (en) 1984-10-17 1991-03-26 Centre National D'etudes Des Telecommunications Dual addressing transistor active matrix display screen
US4797667A (en) 1985-04-30 1989-01-10 Planar Systems, Inc. Split screen electrode structure for TFEL panel
US4962374A (en) 1985-12-17 1990-10-09 Sharp Kabushiki Kaisha Thin film el display panel drive circuit
US4736137A (en) 1986-08-01 1988-04-05 Hitachi, Ltd Matrix display device
US4963861A (en) 1986-12-22 1990-10-16 Etat Francais represente par le Ministre des Postes et Telecommunications Centre National Electroluminescent memory display having multi-phase sustaining voltages
US4975691A (en) 1987-06-16 1990-12-04 Interstate Electronics Corporation Scan inversion symmetric drive
US4954747A (en) 1988-11-17 1990-09-04 Tuenge Richard T Multi-colored thin-film electroluminescent display with filter
US4958105A (en) 1988-12-09 1990-09-18 United Technologies Corporation Row driver for EL panels and the like with inductance coupling
US5095248A (en) 1989-11-24 1992-03-10 Fuji Xerox Co., Ltd. Electroluminescent device driving circuit
US5079483A (en) 1989-12-15 1992-01-07 Fuji Xerox Co., Ltd. Electroluminescent device driving circuit
US5063378A (en) 1989-12-22 1991-11-05 David Sarnoff Research Center, Inc. Scanned liquid crystal display with select scanner redundancy
EP0457440A2 (en) 1990-05-14 1991-11-21 Cherry Display Products Corporation Grey scale display
US5262766A (en) * 1990-09-19 1993-11-16 Sharp Kabushiki Kaisha Display unit having brightness control function
US5576601A (en) * 1991-10-11 1996-11-19 Norand Corporation Drive circuit for electroluminescent panels and the like
US5172032A (en) 1992-03-16 1992-12-15 Alessio David S Method of and apparatus for the energization of electroluminescent lamps
US5559402A (en) * 1994-08-24 1996-09-24 Hewlett-Packard Company Power circuit with energy recovery for driving an electroluminescent device

Non-Patent Citations (8)

* Cited by examiner, † Cited by third party
Title
Channing D et al: "El Addressing Technology" US Playa Del Rey, SID, 1989, p. 54-57 XP000076837 * p. 55, right-hand column, line 1-p. 56, right-hand column, last paragraph * figure 8, 9.
European Search Report corresponding to Application No. 97200425.3-2205.
P. De Visschere, I. De Rycke, J. Doutreloigne, J. Vanfleteren, "Active Matrix CdSe TFT Adressed Electroluminescent Displays" 1988 IEEE Internation Research Conf. pp. 74-76.
Salerno et al., "5.7: Late-News Paper: Single-Crystal Silicon Transmissive AMLCD", SID 92 Digest, pp. 63-66 (1992).
Suzuki et al., "19.2: Late-News Paper: The Fabrication of TFEL Displays Driven by a a-Si TFTs", SID 92 Digest, pp. 344-347 (1992).
Vanfleteren et al., "Active Matrix CdSe TFT Addressed Electroluminescent Displays", 1988 International Display Research Conference, pp. 74-76 (1988).
Vanfleteren et al., "Design of a Prototype Active Matrix CdSe TFT Addressed EL Display", Sep. 24, 1991.
Vanfleteren et al., "Evaluation of a 64x64 CdSe TFT Addressed ACTFEL Display Demonstrator", IEEE, pp. 134-136 (1991).

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US20060273995A1 (en) * 1997-02-17 2006-12-07 Seiko Epson Corporation Display apparatus
US20060273996A1 (en) * 1997-02-17 2006-12-07 Seiko Epson Corporation Display apparatus
US20080246700A1 (en) * 1997-02-17 2008-10-09 Seiko Epson Corporation Display Apparatus
US20100066652A1 (en) * 1997-02-17 2010-03-18 Seiko Epson Corporation Display apparatus
US8154199B2 (en) 1997-02-17 2012-04-10 Seiko Epson Corporation Display apparatus
US8247967B2 (en) 1997-02-17 2012-08-21 Seiko Epson Corporation Display apparatus
US8354978B2 (en) 1997-02-17 2013-01-15 Seiko Epson Corporation Display apparatus

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DE69320956D1 (en) 1998-10-15 grant
EP0643865B1 (en) 1998-09-09 grant
WO1993024921A1 (en) 1993-12-09 application
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JPH07507403A (en) 1995-08-10 application
EP0643865A4 (en) 1995-08-30 application
EP0778556A3 (en) 2000-02-23 application
EP0778556A2 (en) 1997-06-11 application
FI945548A (en) 1994-11-25 application
FI945548A0 (en) 1994-11-25 application
JP3510248B2 (en) 2004-03-22 grant
FI945548D0 (en) grant
US5302966A (en) 1994-04-12 grant
DE69320956T2 (en) 1999-04-22 grant
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EP0778556B1 (en) 2002-11-06 grant
DE69332475T2 (en) 2003-07-10 grant

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