USRE39768E1 - VCC pump for CMOS imagers - Google Patents
VCC pump for CMOS imagers Download PDFInfo
- Publication number
- USRE39768E1 USRE39768E1 US10/283,165 US28316502A USRE39768E US RE39768 E1 USRE39768 E1 US RE39768E1 US 28316502 A US28316502 A US 28316502A US RE39768 E USRE39768 E US RE39768E
- Authority
- US
- United States
- Prior art keywords
- charge
- transistor
- voltage
- control signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003384 imaging method Methods 0.000 claims abstract description 115
- 239000000758 substrate Substances 0.000 claims description 69
- 238000009792 diffusion process Methods 0.000 claims description 62
- 238000007667 floating Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 32
- 230000004044 response Effects 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 14
- 238000009825 accumulation Methods 0.000 claims description 11
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 8
- 230000008901 benefit Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000003491 array Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 230000003750 conditioning effect Effects 0.000 description 2
- 238000013144 data compression Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 101100041125 Arabidopsis thaliana RST1 gene Proteins 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000819554 Mendis Species 0.000 description 1
- 101100443250 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) DIG1 gene Proteins 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/709—Circuitry for control of the power supply
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Definitions
- the invention relates generally to improved semiconductor imaging devices and in particular to an imaging device which can be fabricated using a standard CMOS process. Particularly, the invention relates to a CMOS imager having an array of image sensing cells and to the driving signals which operate the cells.
- CCDs charge coupled devices
- photodiode arrays charge injection devices
- hybrid focal plan arrays There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plan arrays.
- CCDs are often employed for image acquisition and enjoy a number of advantages which makes it the incumbent technology, particularly for small size imaging applications.
- CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques.
- CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays.
- CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there has been some attempts to integrate on-chip signal processing with the CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time, CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer which also results in image smear.
- CMOS imagers Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices.
- a fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
- CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
- a CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate.
- a readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor.
- the imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
- the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge.
- Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node.
- the charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor.
- the photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate.
- image lag can be eliminated by completely depleting the photodiode upon readout.
- CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., “256 ⁇ 256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453, 1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, which are herein incorporated by reference.
- CMOS imaging circuit includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate.
- CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.
- FIG. 1 shows a simplified circuit for a pixel of an exemplary CMOS imager using a photogate and having a pixel photodetector circuit 14 and a readout circuit 60 .
- FIG. 1 shows the circuitry for operation of a single pixel, that in practical use there will be an M ⁇ N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
- the photodetector circuit 14 is shown in part as a cross-sectional view of a semiconductor substrate 16 typically a p-type silicon, having a surface well of p-type material 20 .
- An optional layer 18 of p-type material may be used if desired, but is not required.
- Substrate 16 may be formed of, for example, Si, SiGe, Ge, and GaAs.
- the entire substrate 16 is p-type doped silicon substrate and may contain a surface p-well 20 (with layer 18 omitted), but many other options are possible, such as, for example p on p ⁇ substrates, p on p+ substrates, p-wells in n-type substrates or the like.
- wafer or substrate used in the description includes any semiconductor-based structure having an exposed surface in which to form the circuit structure used in the invention.
- Wafer and substrate are to be understood as including, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
- SOI silicon-on-insulator
- SOS silicon-on-sapphire
- doped and undoped semiconductors silicon-on-insulator
- epitaxial layers of silicon supported by a base semiconductor foundation and other semiconductor structures.
- previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation.
- An insulating layer 22 such as, for example, silicon dioxide is formed on the upper surface of p-well 20 .
- the p-type layer may be a p-well formed in substrate 16 .
- a photogate 24 thin enough to pass radiant energy or of a material which passes radiant energy is formed on the insulating layer 22 .
- the photogate 24 receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region 26 .
- the n+ type region 26 adjacent one side of photogate 24 , is formed in the upper surface of p-well 20 .
- a transfer gate 28 is formed on insulating layer 22 between n+ type region 26 and a second n+ type region 30 formed in p-well 20 .
- the n+ regions 26 and 30 and transfer gate 28 form a charge transfer transistor 29 which is controlled by a transfer signal TX.
- the n+ region 30 is typically called a floating diffusion region. It is also a node for passing charge accumulated thereat to the gate of a source follower transistor 36 described below.
- a reset gate 32 is also formed on insulating layer 22 adjacent and between n+ type region 30 and another n+ region 34 which is also formed in p-well 20 .
- the reset gate 32 and n+ regions 30 and 34 form a reset transistor 31 which is controlled by a reset signal RST.
- the n+ type region 34 is coupled to voltage source VDD, e.g., 5 volts.
- the transfer and reset transistor 29 , 31 are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. It should be understood that it is possible to implement a CMOS imager in an n-well in which case each of the transistors would be p-channel transistors. It should also be noted that while FIG. 1 shows the use of a transfer gate 28 and associated transistor 29 , this structure provides advantages, but is not required.
- Photodetector circuit 14 also includes two additional n-channel transistors, source follower transistor 36 and row select transistor 38 .
- Transistors 36 , 38 are coupled in series, source to drain, with the source of transistor 36 also coupled over lead 40 to voltage source VDD and the drain of transistor 38 coupled to a lead 42 .
- the drain of row select transistor 38 is connected via conductor 42 to the drains of similar row select transistors for other pixels in a given pixel row.
- a load transistor 39 is also coupled between the drain of transistor 38 and a voltage source VSS, e.g. 0 volts.
- Transistor 39 is kept on by a signal VLN applied to its gate.
- the imager includes a readout circuit 60 which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor 62 and a signal storage capacitor 64 connected to the source follower transistor 36 through row transistor 38 .
- the other side of the capacitor 64 is connected to a source voltage VSS.
- the upper side of the capacitor 64 is also connected to the gate of a p-channel output transistor 66 .
- the drain of the output transistor 66 is connected through a column select transistor 68 to a signal sample output node VOUTS and through a load transistor 70 to the voltage supply VDD.
- a signal called “signal sample and hold” (SHS) briefly turns on the S/H transistor 62 after the charge accumulated beneath the photogate electrode 24 has been transferred to the floating diffusion node 30 and from there to the source follower transistor 36 and through row select transistor 38 to line 42 , so that the capacitor 64 stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode 24 .
- SHS signal sample and hold
- the readout circuit 60 also includes a reset sample and hold (S/H) circuit including a S/H transistor 72 and a signal storage capacitor 74 connected through the S/H transistor 72 and through the row select transistor 38 to the source of the source follower transistor 36 .
- the other side of the capacitor 74 is connected to the source voltage VSS.
- the upper side of the capacitor 74 is also connected to the gate of a p-channel output transistor 76 .
- the drain of the output transistor 76 is connected through a p-channel column select transistor 78 to a reset sample output node VOUTR and through a load transistor 80 to the supply voltage VDD.
- a signal called “reset sample and hold” (SHR) briefly turns on the S/H transistor 72 immediately after the reset signal RST has caused reset transistor 31 to turn on and reset the potential of the floating diffusion node 30 , so that the capacitor 74 stores the voltage to which the floating diffusion node 30 has been reset.
- the readout circuit 60 provides correlated sampling of the potential of the floating diffusion node 30 , first of the reset charge applied to node 30 by reset transistor 31 and then of the stored charge from the photogate 24 .
- the two samplings of the diffusion node 30 charges produce respective output voltages VOUTR and VOUTS of the readout circuit 60 .
- These voltages are then subtracted (VOUTS ⁇ VOUTR) by subtractor 82 to provide an output signal terminal 81 which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor 31 which might cause pixel to pixel variations in the output signal.
- FIG. 2 illustrates a block diagram for a CMOS imager having a pixel array 200 with each pixel cell being constructed in the manner shown by element 14 of FIG. 1 .
- FIG. 4 shows a 2 ⁇ 2 portion of pixel array 200 .
- Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 200 are all turned on at the same time by a row select line, e.g., line 86 , and the pixels of each column are selectively output by a column select line, e.g., line 42 .
- a plurality of rows and column lines are provided for the entire array 200 .
- the row lines are selectively activated by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated by the column driver 260 in response to column address decoder 270 .
- a row and column address is provided for each pixel.
- the CMOS imager is operated by the control circuit 250 which controls address decoders 220 , 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210 , 260 which apply driving voltage to the drive transistors of the selected row and column lines.
- FIG. 3 shows a simplified timing diagram for the signals used to transfer charge out of photodetector circuit 14 of the FIG. 1 CMOS imager.
- the photogate signal PG is nominally set to 5V and the reset signal RST is nominally set at 2.5V.
- the process is begun at time t 0 by briefly pulsing reset voltage RST to 5V.
- the RST voltage which is applied to the gate 32 of reset transistor 31 , causes transistor 31 to turn on and the floating diffusion node 30 to charge to the VDD voltage present at n+ region 34 (less the voltage drop Vth of transistor 31 ). This resets the floating diffusion node 30 to a predetermined voltage (VDD ⁇ Vth).
- the charge on floating diffusion node 30 is applied to the gate of the source follower transistor 36 to control the current passing through transistor 38 , which has been turned on by a row select (ROW) signal, and load transistor 39 .
- This current is translated into a voltage on line 42 which is next sampled by providing a SHR signal to the S/H transistor 72 which charges capacitor 74 with the source follower transistor output voltage on line 42 representing the reset charge present at floating diffusion node 30 .
- the PG signal is next pulsed to 0 volts, causing charge to be collected in n+ region 26 .
- a transfer gate voltage TX similar to the reset pulse RST, is then applied to transfer gate 28 of transistor 29 to cause the charge in n+ region 26 to transfer to floating diffusion node 30 .
- the transfer gate voltage TX may be pulsed or held to a fixed DC potential.
- the transfer gate voltage TX must be pulsed.
- the new output voltage on line 42 generated by source follower transistor 36 current is then sampled onto capacitor 64 by enabling the sample and hold switch 62 by signal SHS.
- the column select signal is next applied to transistors 68 and 70 and the respective charges stored in capacitors 64 and 74 are subtracted in subtractor 82 to provide a pixel output signal at terminal 81 .
- CMOS imagers may dispense with the transfer gate 28 and associated transistor 29 , or retain these structures while biasing the transfer transistor 29 to an always “on” state.
- CMOS imager The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19-29 1994; Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol. 32(3), 1997; and Eric R, Fossum, “CMOS Image Sensors: Electronic Camera on a Chip,” IEDM Vol. 95 pages 17-25 (1995) as well as other publications. These references are incorporated herein by reference.
- CMOS imagers suffer from inconsistent noise effects, voltage drops and leakage across the reset transistor 31 , the row select transistor 38 and the transfer transistor 29 . These affect the dynamic range of the pixel output as well as the ability of the pixel to accurately depict an image. Moreover, due to imprecision in the fabrication process, the electrical properties of these transistors will vary from pixel to pixel causing inconsistent output for the same level of charge from pixel to pixel. Since the size of the pixel electrical signal is very small due to the collection of photons in the photo array, the signal to noise ratio of the pixel should be as high as possible and charge leakage within a pixel as low as possible. Moreover, pixel output and the leakage of charge must be as consistent as possible from pixel to pixel.
- the present invention is designed to improve variations in the reset voltage and the leakage characteristics of a CMOS imager pixel while improving the consistency of the pixel to pixel output of the pixel array and increasing the dynamic range of the pixel output. This is accomplished by driving one or more of the reset gate, transfer gate (if used) and the row select gate with one or more charge pumps.
- the charge pump provides a higher voltage than the supply voltage VDD to improve the gating operation of the reset, transfer and row select transistors.
- the charge pump increases the voltage to the reset gate so that the voltage drop across the reset transistor does not lower the VDD reset charge at floating diffusion node 30 and increases the voltage to the transfer gate to allow barrier and well lowering in its operation.
- a photogate By overdriving one or more of the gates of the reset, transfer and row select transistors with the output of a charge pump, pixel to pixel fabrication differences in electrical characteristics of these transistors can also be avoided. Moreover, if a photogate is used to acquire image charges this too may be overdriven by an output voltage from a charge pump. Since the photogate turn on voltage is typically VSS, e.g., 0 volts, a charge pump is used which drives the photogate with an even lower voltage than VSS. Additionally, the photogate may be overdriven, e.g. 6 volts, during charge collection to assure that charge is effectively collected by the device.
- FIG. 1 is a representative circuit of the CMOS imager.
- FIG. 2 is a block diagram of a CMOS active pixel sensor chip.
- FIG. 3 is a representative timing diagram for the CMOS imager.
- FIG. 4 is a representative pixel layout showing a 2 ⁇ 2 pixel layout according to one embodiment of the present invention.
- FIG. 5 is a representative circuit drawing of a charge pump that may be used with the present invention.
- FIG. 6 is an illustration of a computer system having a CMOS imager according to the present invention.
- FIG. 4 shows a portion of an active pixel array constructed according to the present invention in which respective charge pumps 300 , 301 and 302 are used to supply the gate voltages for the reset, transfer and row select transistors 31 , 29 and 38 .
- a charge pumps 303 and 304 are shown for providing a gate voltage to a photogate 24 for charge transfer and charge storage respectively.
- This figure shows a 2 ⁇ 2 array of pixels for simplification. It should be understood that the invention is directed to a M ⁇ N multiple pixel array of any size.
- Photodetectors 14 of a row of pixels are coupled via their respective row select transistors 38 to column line 42 .
- the photodetector selected by a row decoder over line 86 will provide electrical current depending upon the voltage at the gate of source follower transistor 36 supplied by floating diffusion node 30 .
- the gate of transistor 36 controls the current through load transistor 39 (not shown in FIG. 4 ) and in consequence the voltage on lead 42 .
- Signal ROW SELECT 1 on lead 86 turns row select transistor 38 on.
- the voltage controlled by the row select signal 86 is a charge pump 302 output voltage.
- Row select 86 is connected to charge pump 302 to overdrive the row select transistor, that is, the gate voltage of transistor 38 is higher than the VDD supply voltage. In a 5V VDD system, charge pump 302 will supply at least VDD+Vth volts to the gate of row select transistor 38 where Vth is the threshold voltage for transistor 38 .
- the reset signal RST 1 turns on transistor 31 which causes the floating diffusion node 30 to be reset to a potential of VDD ⁇ Vth, where Vth is the threshold voltage of the reset transistor 31 .
- the actual gate signal to transistor 31 is supplied by charge pump 300 to overdrive the gate of the reset transistor with a voltage of at least the value VDD+Vth to maintain a constant voltage reset value on node 30 at VDD.
- the photogate 24 is also supplied from a charge pump 304 , ensuring that the photogate to be overdriven to its on state to ensure that all possible collected charge for an image signal is stored in the imager substrate beneath the photogate until it is to be transferred out of the collection area.
- the photogate 24 is also supplied from a charge pump 303 in response to photogate signal PG over line 46 , ensuring that the photogate to be overdriven to its on state to ensure that all possible collected charge for an image signal is transferred from the substrate beneath the photogate to the collection area.
- the FIG. 4 circuit shows use of a transfer gate 28 and associated transistor 29 . If the CMOS imager cells uses a transfer transistor, then the transfer gate 28 voltage is also supplied from a charge pump 301 in response to transfer signal TX, once again ensuring that the transfer transistor is overdriven to its on state and eliminating the Vth voltage drop which normally occurs. The operation of the FIG. 4 circuit to acquire, transfer and output pixel charge is otherwise as previously described.
- the charge pumps 300 , 301 provide voltage to the reset gate 32 and transfer gate 28 at a potential which is greater than the supply potential VDD.
- the pumped voltage enhances the performance of the transfer and reset transistors.
- a gate voltage to the transistor In order to turn “on” the various transistors of the pixel array, a gate voltage to the transistor must exceed a source or drain voltage (depending on the type of transistor) by a threshold voltage Vth.
- the threshold voltage (Vth) may differ for each transistor of a pixel array due to manufacturing imperfections.
- the charge pumps 300 , 301 , 302 and 304 help to overcome the inconsistent on/off threshold voltages (Vth) of the transistors by overdriving the gates with voltages which ensure that they turn on or off as required, regardless of manufacturing inconsistencies. Also, the charge pump 300 increases the dynamic operating range of each pixel since the full reset voltage VDD will be applied to the floating diffusion node 30 .
- the charge pump 303 ensures that the maximum possible charges are collected in the collection region beneath the photogate.
- charge pumps 300 , 301 , 302 , 303 , 304 are shown in FIG. 4 for the entire CMOS pixel array, it should be understood that a single charge pump having multiple controlled output voltages may be used for the entire CMOS imager and for associated logic circuits. Also, individual charge pumps may be used for different portions of the imager circuit and for the associated logic. Also, while the charge pumps 300 , 301 , 302 , 303 , 304 are shown supplying voltage for the reset gate, the transfer gate, the row select gate and the photogate, it should be understood that a charge pump may be used for one or more of these gates to achieve a benefit over conventional CMOS imagers which do not use a charge pump.
- FIG. 5 shows one exemplary charge pump which may be used for one or more of charge pumps 300 , 301 , 302 , 303 and 304 .
- Charge pumps per se, are well known, such as those shown in U.S. Pat. No. 5,038,325 which is herein incorporated by reference.
- the exemplary charge pump shown in FIG. 5 , uses two clamp circuits 320 , 330 .
- An oscillator 310 provides its output to first and second capacitors 315 , 335 .
- Clamp circuits 320 , 330 are connected across the capacitors 315 , 335 .
- the oscillator 310 is a ring oscillator which can be adjusted to increase or decrease its output signal frequency.
- An output transistor 325 is connected between node 350 of capacitors 315 and a circuit output 355 node.
- An input signal SIG which might vary between VDD and VSS, is output as an elevated potential signal SIGp which may vary between VSS and VDDp where VDDp>VDD. Where the potential signal SIGp is desired to be less than the operating voltage, i.e., charge pump 303 , the output signal SIGp which may vary between VSSp and VDD where VSSp ⁇ VSS.
- Both clamp circuits 320 , 330 turn on and off at the same time, but the connection of clamp circuit 330 across capacitor 335 and in series with the output transistor has the result that the operation of the second clamp circuit 330 causes the output transistor 325 to conduct when potential at the node 350 is at a high potential.
- the rising edge of the oscillator 310 couples a high voltage through the capacitors 315 , 335 which shuts the clamps 320 , 330 off and allows the nodes 350 , 355 to go high.
- the falling edge of the output of the oscillator 310 couples a drop in potential through the capacitors 315 , 335 , at which point, the clamps 320 , 330 turns on, preventing the nodes 350 , 355 from going low.
- a decoupling capacitor 345 further cooperates with the charge pump 300 in order to provide a steady boosted output which is switched by input signal SIG.
- the charge pump 303 For operating the photogate PG, the charge pump 303 is configured to supply an output voltage VSSp where VSSp ⁇ VSS.
- the charge pump 304 For collecting charge in the photogate, the charge pump 304 is configured to supply an output voltage VPGp where VPGp is greater than input voltage VDD.
- a representative output voltages of charge pumps 300 , 301 , 302 , 304 are 6.0, 6.0 and 6.0, respectively for a 5.0 volt VDD supply and assuming that the Vth of each of these transistors is less than 1.0 volts.
- the charge pump 303 output has a representative voltage value of ⁇ 1 volt. It should be understood that the output of voltage charge pumps 300 , 301 , 302 , 303 and 304 may vary, individually, depending upon the VDD and/or VSS supply as well as the Vth of the individual transistors.
- a typical processor based system which includes a CMOS imager device according to the present invention is illustrated generally at 400 in FIG. 6.
- a processor based system is exemplary of a system having digital circuits which could include CMOS imager devices.
- Such a system could include a computer system, camera system, scanner, machine vision system, vehicle navigation system, video phone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention.
- a processor system such as a computer system, for example generally comprises a central processing unit (CPU) 444 that communicates with an input/output (I/O) device 446 over a bus 452 .
- the CMOS imager 442 also communicates with the system over bus 452 .
- the computer system 400 also includes random access memory (RAM) 448 , and, in the case of a computer system may include peripheral devices such as a floppy disk driver 454 and a compact disk (CD) ROM drive 456 and I/O devices like a keyboard and/or mouse which also communicate with CPU 444 over the bus 452 .
- CMOS imager 442 is preferably constructed as an integrated circuit which includes the voltage charge pumps 300 , 301 and 302 , as previously described with respect to FIGS. 4-7 .
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
Claims (161)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/283,165 USRE39768E1 (en) | 1998-10-14 | 2002-10-30 | VCC pump for CMOS imagers |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/172,301 US6140630A (en) | 1998-10-14 | 1998-10-14 | Vcc pump for CMOS imagers |
US10/283,165 USRE39768E1 (en) | 1998-10-14 | 2002-10-30 | VCC pump for CMOS imagers |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/172,301 Reissue US6140630A (en) | 1998-10-14 | 1998-10-14 | Vcc pump for CMOS imagers |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE39768E1 true USRE39768E1 (en) | 2007-08-14 |
Family
ID=22627121
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/172,301 Ceased US6140630A (en) | 1998-10-14 | 1998-10-14 | Vcc pump for CMOS imagers |
US10/283,165 Expired - Lifetime USRE39768E1 (en) | 1998-10-14 | 2002-10-30 | VCC pump for CMOS imagers |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/172,301 Ceased US6140630A (en) | 1998-10-14 | 1998-10-14 | Vcc pump for CMOS imagers |
Country Status (1)
Country | Link |
---|---|
US (2) | US6140630A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040252211A1 (en) * | 2003-06-16 | 2004-12-16 | Rhodes Howard E. | Pumps for CMOS imagers |
US20050280724A1 (en) * | 2003-12-03 | 2005-12-22 | Sanyo Electric Co., Ltd. | Image signal-processing device, method for processing image signal, image signal-processing program product, control device for solid image capturing element, and method for controlling solid image capturing element |
US20060017714A1 (en) * | 2004-07-20 | 2006-01-26 | Kazuya Yonemoto | Solid-state imaging apparatus and sampling circuit |
US20060285000A1 (en) * | 2003-09-10 | 2006-12-21 | Keiji Mabuchi | Semiconductor device, and control method and device for driving unit component of semiconductor device |
WO2009058467A1 (en) * | 2007-10-29 | 2009-05-07 | Fairchild Imaging, Inc. | Cmos sensor adapted for dental x-ray imaging |
Families Citing this family (153)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6879340B1 (en) | 1998-08-19 | 2005-04-12 | Micron Technology Inc. | CMOS imager with integrated non-volatile memory |
US6388242B1 (en) * | 1998-10-14 | 2002-05-14 | Photobit Corporation | Micro power micro-sized CMOS active pixel |
JP3571934B2 (en) * | 1998-10-23 | 2004-09-29 | セイコーインスツルメンツ株式会社 | Image sensor |
US6825878B1 (en) * | 1998-12-08 | 2004-11-30 | Micron Technology, Inc. | Twin P-well CMOS imager |
US6147366A (en) * | 1999-02-08 | 2000-11-14 | Intel Corporation | On chip CMOS optical element |
US6215113B1 (en) * | 1999-04-22 | 2001-04-10 | National Science Council | CMOS active pixel sensor |
US6654057B1 (en) * | 1999-06-17 | 2003-11-25 | Micron Technology, Inc. | Active pixel sensor with a diagonal active area |
TW503620B (en) * | 2000-02-04 | 2002-09-21 | Sanyo Electric Co | Drive apparatus for CCD image sensor |
US7053945B1 (en) | 2000-07-26 | 2006-05-30 | Micron Technolopgy, Inc. | Image sensor having boosted reset |
JP3750502B2 (en) * | 2000-08-03 | 2006-03-01 | ソニー株式会社 | Solid-state imaging device and camera system |
JP3667214B2 (en) | 2000-08-25 | 2005-07-06 | キヤノン株式会社 | Solid-state imaging device and driving method thereof |
US6541794B1 (en) * | 2000-08-31 | 2003-04-01 | Motorola, Inc. | Imaging device and method |
US6863667B2 (en) * | 2001-01-29 | 2005-03-08 | Intralase Corp. | Ocular fixation and stabilization device for ophthalmic surgical applications |
US20080071254A1 (en) | 2001-01-29 | 2008-03-20 | Advanced Medical Optics, Inc. | Ophthalmic interface apparatus and system and method of interfacing a surgical laser with an eye |
US6899707B2 (en) * | 2001-01-29 | 2005-05-31 | Intralase Corp. | Applanation lens and method for ophthalmic surgical applications |
US20120016349A1 (en) | 2001-01-29 | 2012-01-19 | Amo Development, Llc. | Hybrid ophthalmic interface apparatus and method of interfacing a surgical laser with an eye |
US6937278B2 (en) * | 2001-04-02 | 2005-08-30 | Micron Technology, Inc. | Row driver circuit for a sensor including a shared row-reset bus and a charge pump boosting circuit |
WO2002091736A1 (en) * | 2001-04-27 | 2002-11-14 | Honda Giken Kogyo Kabushiki Kaisha | Output correction unit of image sensor |
US20030076431A1 (en) * | 2001-10-24 | 2003-04-24 | Krymski Alexander I. | Image sensor with pixels having multiple capacitive storage elements |
EP1341377B1 (en) * | 2002-02-27 | 2018-04-11 | Canon Kabushiki Kaisha | Signal processing device for image pickup apparatus |
US6946715B2 (en) * | 2003-02-19 | 2005-09-20 | Micron Technology, Inc. | CMOS image sensor and method of fabrication |
US7858912B2 (en) * | 2002-08-16 | 2010-12-28 | The Hong Kong University Of Science And Technology | Ultra low voltage CMOS image sensor architecture |
US7471324B2 (en) * | 2002-08-28 | 2008-12-30 | Aptina Imaging Corporation | Amplifier shared between two columns in CMOS sensor |
US6919551B2 (en) * | 2002-08-29 | 2005-07-19 | Micron Technology Inc. | Differential column readout scheme for CMOS APS pixels |
US7375748B2 (en) * | 2002-08-29 | 2008-05-20 | Micron Technology, Inc. | Differential readout from pixels in CMOS sensor |
JP4281375B2 (en) * | 2003-02-19 | 2009-06-17 | ソニー株式会社 | CMOS solid-state imaging device and driving method thereof |
US6847051B2 (en) * | 2003-05-23 | 2005-01-25 | Micron Technology, Inc. | Elevated photodiode in an image sensor |
US7075049B2 (en) * | 2003-06-11 | 2006-07-11 | Micron Technology, Inc. | Dual conversion gain imagers |
US7071505B2 (en) * | 2003-06-16 | 2006-07-04 | Micron Technology, Inc. | Method and apparatus for reducing imager floating diffusion leakage |
US7009227B2 (en) * | 2003-06-16 | 2006-03-07 | Micron Technology, Inc. | Photodiode structure and image pixel structure |
US7105793B2 (en) * | 2003-07-02 | 2006-09-12 | Micron Technology, Inc. | CMOS pixels for ALC and CDS and methods of forming the same |
US7250647B2 (en) * | 2003-07-03 | 2007-07-31 | Micron Technology, Inc. | Asymmetrical transistor for imager device |
US7456885B2 (en) * | 2003-08-22 | 2008-11-25 | Micron Technology, Inc. | Per column one-bit ADC for image sensors |
US7064406B2 (en) | 2003-09-03 | 2006-06-20 | Micron Technology, Inc. | Supression of dark current in a photosensor for imaging |
US7115855B2 (en) | 2003-09-05 | 2006-10-03 | Micron Technology, Inc. | Image sensor having pinned floating diffusion diode |
US7253392B2 (en) * | 2003-09-08 | 2007-08-07 | Micron Technology, Inc. | Image sensor with photo diode gate |
US20050057680A1 (en) * | 2003-09-16 | 2005-03-17 | Agan Martin J. | Method and apparatus for controlling integration time in imagers |
US7227692B2 (en) * | 2003-10-09 | 2007-06-05 | Micron Technology, Inc | Method and apparatus for balancing color response of imagers |
US7199931B2 (en) * | 2003-10-09 | 2007-04-03 | Micron Technology, Inc. | Gapless microlens array and method of fabrication |
US7057220B2 (en) | 2003-10-09 | 2006-06-06 | Micron Technology, Inc. | Ultrashallow photodiode using indium |
US7560295B2 (en) * | 2003-10-09 | 2009-07-14 | Aptina Imaging Corporation | Methods for creating gapless inner microlenses, arrays of microlenses, and imagers having same |
US7476562B2 (en) * | 2003-10-09 | 2009-01-13 | Aptina Imaging Corporation | Gapless microlens array and method of fabrication |
US7081608B2 (en) * | 2003-10-15 | 2006-07-25 | Micron Technology, Inc. | Pixel with differential readout |
US20050145900A1 (en) * | 2004-01-05 | 2005-07-07 | Rhodes Howard E. | Charge sweep operation for reducing image lag |
US7037764B2 (en) * | 2004-02-26 | 2006-05-02 | Micron Technology, Inc. | Method of forming a contact in a pixel cell |
US7332703B2 (en) * | 2004-03-22 | 2008-02-19 | Micron Technology, Inc. | Imaging structure including a pixel with multiple signal readout circuits and methods of operation for imaging structure |
US20050243193A1 (en) * | 2004-04-30 | 2005-11-03 | Bob Gove | Suppression of row-wise noise in an imager |
US7122819B2 (en) * | 2004-05-06 | 2006-10-17 | Micron Technology, Inc. | Method and apparatus for imager die package quality testing |
US7605852B2 (en) * | 2004-05-17 | 2009-10-20 | Micron Technology, Inc. | Real-time exposure control for automatic light control |
US20050274988A1 (en) * | 2004-06-01 | 2005-12-15 | Hong Sungkwon C | Imager with reflector mirrors |
EP1605685B1 (en) * | 2004-06-05 | 2008-11-26 | STMicroelectronics (Research & Development) Limited | Image sensor with shared reset signal and row select |
TWI237998B (en) * | 2004-06-09 | 2005-08-11 | Via Tech Inc | Operation of imaging-sensing unit and imaging-sensing device with the same |
US20050274994A1 (en) * | 2004-06-14 | 2005-12-15 | Rhodes Howard E | High dielectric constant spacer for imagers |
US7535042B2 (en) * | 2004-07-01 | 2009-05-19 | Aptina Imaging Corporation | Pixel cell with a controlled output signal knee characteristic response |
US20060006915A1 (en) * | 2004-07-12 | 2006-01-12 | Hai Yan | Signal slew rate control for image sensors |
US7372493B2 (en) * | 2004-07-12 | 2008-05-13 | Micron Technology, Inc. | Column-wise clamp voltage driver for suppression of noise in an imager |
US7652703B2 (en) * | 2004-07-12 | 2010-01-26 | Micron Technology, Inc. | Dual panel pixel readout in an imager |
US7880255B2 (en) * | 2004-07-19 | 2011-02-01 | Micron Technology, Inc. | Pixel cell having a grated interface |
US7238977B2 (en) * | 2004-08-19 | 2007-07-03 | Micron Technology, Inc. | Wide dynamic range sensor having a pinned diode with multiple pinned voltages |
US7386186B2 (en) * | 2004-08-27 | 2008-06-10 | Micron Technology, Inc. | Apparatus and method for processing images |
JP2006103624A (en) * | 2004-10-08 | 2006-04-20 | Hitachi Ltd | Lid unit for fuel tank |
US20060114345A1 (en) * | 2004-12-01 | 2006-06-01 | Jiangfeng Wu | Low power programmable reset pump for CMOS imagers |
US7446807B2 (en) * | 2004-12-03 | 2008-11-04 | Micron Technology, Inc. | Imager pixel with capacitance for boosting reset voltage |
US20060152601A1 (en) * | 2005-01-13 | 2006-07-13 | Micron Technology, Inc. | Low cost digital camera with one-time programmable memory |
US7378635B2 (en) * | 2005-02-11 | 2008-05-27 | Micron Technology, Inc. | Method and apparatus for dark current and hot pixel reduction in active pixel image sensors |
US20060187329A1 (en) * | 2005-02-24 | 2006-08-24 | Micron Technology, Inc. | Clamped capacitor readout noise rejection circuit for imagers |
US7701493B2 (en) * | 2005-02-28 | 2010-04-20 | Micron Technology, Inc. | Imager row-wise noise correction |
US7297917B2 (en) * | 2005-03-24 | 2007-11-20 | Micron Technology, Inc. | Readout technique for increasing or maintaining dynamic range in image sensors |
US7718459B2 (en) * | 2005-04-15 | 2010-05-18 | Aptina Imaging Corporation | Dual conversion gain pixel using Schottky and ohmic contacts to the floating diffusion region and methods of fabrication and operation |
US7659928B2 (en) * | 2005-04-21 | 2010-02-09 | Aptina Imaging Corporation | Apparatus and method for providing anti-eclipse operation for imaging sensors |
US7851798B2 (en) | 2005-05-04 | 2010-12-14 | Micron Technology, Inc. | Method and apparatus for dark current and blooming suppression in 4T CMOS imager pixel |
US20060255381A1 (en) * | 2005-05-10 | 2006-11-16 | Micron Technology, Inc. | Pixel with gate contacts over active region and method of forming same |
US7355222B2 (en) * | 2005-05-19 | 2008-04-08 | Micron Technology, Inc. | Imaging device having a pixel cell with a transparent conductive interconnect line and the method of making the pixel cell |
US20060261385A1 (en) * | 2005-05-23 | 2006-11-23 | Micron Technology, Inc. | Phase shift transparent structures for imaging devices |
US7534982B2 (en) * | 2005-06-09 | 2009-05-19 | Micron Technology, Inc. | Reduced imager crosstalk and pixel noise using extended buried contacts |
JP2006352341A (en) * | 2005-06-14 | 2006-12-28 | Micron Technol Inc | Anti-eclipse circuit and operation method thereof |
US7639937B2 (en) * | 2005-07-08 | 2009-12-29 | Aptina Imaging Corporation | Method and apparatus for auto focusing an imaging device |
US7449736B2 (en) * | 2005-07-12 | 2008-11-11 | Micron Technology, Inc. | Pixel with transfer gate with no isolation edge |
US7271025B2 (en) * | 2005-07-12 | 2007-09-18 | Micron Technology, Inc. | Image sensor with SOI substrate |
US7432540B2 (en) * | 2005-08-01 | 2008-10-07 | Micron Technology, Inc. | Dual conversion gain gate and capacitor combination |
US7796180B2 (en) * | 2005-08-03 | 2010-09-14 | Aptina Imaging Corporation | Method for calculating circular symmetrical microlens/color filter array shift |
US20070035649A1 (en) * | 2005-08-10 | 2007-02-15 | Micron Technology, Inc. | Image pixel reset through dual conversion gain gate |
US7265328B2 (en) * | 2005-08-22 | 2007-09-04 | Micron Technology, Inc. | Method and apparatus providing an optical guide for an imager pixel having a ring of air-filled spaced slots around a photosensor |
US7453054B2 (en) * | 2005-08-23 | 2008-11-18 | Aptina Imaging Corporation | Method and apparatus for calibrating parallel readout paths in imagers |
US7808023B2 (en) * | 2005-08-24 | 2010-10-05 | Aptina Imaging Corporation | Method and apparatus providing integrated color pixel with buried sub-wavelength gratings in solid state imagers |
US7511257B2 (en) * | 2005-08-24 | 2009-03-31 | Aptina Imaging Corporation | Method and apparatus providing and optical guide in image sensor devices |
US20070045668A1 (en) * | 2005-08-26 | 2007-03-01 | Micron Technology, Inc. | Vertical anti-blooming control and cross-talk reduction for imagers |
US7315014B2 (en) * | 2005-08-30 | 2008-01-01 | Micron Technology, Inc. | Image sensors with optical trench |
US7611507B2 (en) * | 2005-10-24 | 2009-11-03 | Amo Development Llc | Disposable patient interface |
US7608875B2 (en) * | 2005-11-30 | 2009-10-27 | Aptina Imaging Corporation | Method and apparatus for blocking light to peripheral circuitry of an imager device |
US7848569B2 (en) * | 2005-12-14 | 2010-12-07 | Micron Technology, Inc. | Method and apparatus providing automatic color balancing for digital imaging systems |
US7619266B2 (en) * | 2006-01-09 | 2009-11-17 | Aptina Imaging Corporation | Image sensor with improved surface depletion |
US7675080B2 (en) * | 2006-01-10 | 2010-03-09 | Aptina Imaging Corp. | Uniform color filter arrays in a moat |
US7626626B2 (en) * | 2006-01-13 | 2009-12-01 | Micron Technology, Inc. | Method and apparatus providing pixel storage gate charge sensing for electronic stabilization in imagers |
US7612813B2 (en) * | 2006-02-03 | 2009-11-03 | Aptina Imaging Corporation | Auto exposure for digital imagers |
US7474846B2 (en) * | 2006-02-15 | 2009-01-06 | Micron Technology, Inc. | Method and apparatus of determining the best focus position of a lens |
US20070205354A1 (en) * | 2006-03-06 | 2007-09-06 | Micron Technology, Inc. | Image sensor light shield |
US7538304B2 (en) * | 2006-03-30 | 2009-05-26 | Aptina Imaging Corporation | Reducing noise in an imager by sampling signals with a plurality of capacitances connected to an output line |
US7799491B2 (en) * | 2006-04-07 | 2010-09-21 | Aptina Imaging Corp. | Color filter array and imaging device containing such color filter array and method of fabrication |
US7955764B2 (en) * | 2006-04-07 | 2011-06-07 | Micron Technology, Inc. | Methods to make sidewall light shields for color filter array |
US7605440B2 (en) * | 2006-04-07 | 2009-10-20 | Aptina Imaging Corporation | Pixel cell isolation of charge storage and floating diffusion regions using doped wells |
US7368698B2 (en) * | 2006-04-12 | 2008-05-06 | Micron Technology, Inc. | Imaging device with reduced row readout time and method of operating the same |
US7612319B2 (en) * | 2006-06-09 | 2009-11-03 | Aptina Imaging Corporation | Method and apparatus providing a microlens for an image sensor |
US7619671B2 (en) * | 2006-07-18 | 2009-11-17 | Aptina Imaging Corporation | Method, apparatus and system for charge injection suppression in active pixel sensors |
GB2441161B (en) * | 2006-08-24 | 2009-01-07 | Micron Technology Inc | Method, apparatus, and system providing power supply independent imager output driver having a constant slew rate |
US7969490B2 (en) * | 2006-08-25 | 2011-06-28 | Micron Technology, Inc. | Method, apparatus, and system providing an imager with pixels having extended dynamic range |
US8610806B2 (en) | 2006-08-28 | 2013-12-17 | Micron Technology, Inc. | Color filter array, imagers and systems having same, and methods of fabrication and use thereof |
US7755684B2 (en) * | 2006-08-29 | 2010-07-13 | Micron Technology, Inc. | Row driver circuitry for imaging devices and related method of operation |
US7514716B2 (en) * | 2006-08-29 | 2009-04-07 | Aptina Imaging Corporation | In-pixel analog memory with non-destructive read sense circuit for high dynamic range global shutter pixel operation |
US7696545B2 (en) * | 2006-08-29 | 2010-04-13 | Micron Technology, Inc. | Skimmed charge capture and charge packet removal for increased effective pixel photosensor full well capacity |
US7944485B2 (en) * | 2006-08-30 | 2011-05-17 | Micron Technology, Inc. | Method, apparatus and system for dynamic range estimation of imaged scenes |
US20080054320A1 (en) * | 2006-08-31 | 2008-03-06 | Micron Technology, Inc. | Method, apparatus and system providing suppression of noise in a digital imager |
US7965444B2 (en) * | 2006-08-31 | 2011-06-21 | Micron Technology, Inc. | Method and apparatus to improve filter characteristics of optical filters |
US7663165B2 (en) * | 2006-08-31 | 2010-02-16 | Aptina Imaging Corporation | Transparent-channel thin-film transistor-based pixels for high-performance image sensors |
US7369072B2 (en) * | 2006-08-31 | 2008-05-06 | Micron Technology, Inc. | Method and apparatus for calibrating imaging device circuits |
US7535281B2 (en) * | 2006-09-29 | 2009-05-19 | Micron Technology, Inc. | Reduced time constant charge pump and method for charging a capacitive load |
US7763913B2 (en) | 2006-12-12 | 2010-07-27 | Aptina Imaging Corporation | Imaging method, apparatus, and system providing improved imager quantum efficiency |
US20080170228A1 (en) * | 2007-01-17 | 2008-07-17 | Micron Technology, Inc. | Method and apparatus for wafer level calibration of imaging sensors |
US8101903B2 (en) | 2007-01-23 | 2012-01-24 | Micron Technology, Inc. | Method, apparatus and system providing holographic layer as micro-lens and color filter array in an imager |
US20080204580A1 (en) * | 2007-02-28 | 2008-08-28 | Micron Technology, Inc. | Method, apparatus and system providing imaging device with color filter array |
US20080239111A1 (en) * | 2007-03-26 | 2008-10-02 | Micron Technology, Inc. | Method and appratus for dark current compensation of imaging sensors |
US8502898B2 (en) * | 2007-04-23 | 2013-08-06 | Micron Technology, Inc. | Method, apparatus, and system providing a rectilinear pixel grid with radially scaled pixels |
US7768047B2 (en) * | 2007-05-10 | 2010-08-03 | Micron Technology, Inc. | Imager element, device and system with recessed transfer gate |
US7920171B2 (en) * | 2007-05-18 | 2011-04-05 | Aptina Imaging Corporation | Methods and apparatuses for vignetting correction in image signals |
US7876957B2 (en) * | 2007-05-31 | 2011-01-25 | Aptina Imaging Corporation | Methods and apparatuses that reduce noise in image signals |
US7884871B2 (en) * | 2007-06-15 | 2011-02-08 | Aptina Imaging Corporation | Images with high speed digital frame transfer and frame processing |
US7642580B2 (en) * | 2007-06-20 | 2010-01-05 | Apitina Imaging Corporation | Imager pixel structure and circuit |
US8736726B2 (en) * | 2007-06-27 | 2014-05-27 | Micron Technology, Inc. | Pixel to pixel charge copier circuit apparatus, systems, and methods |
US20090021623A1 (en) * | 2007-07-18 | 2009-01-22 | Micron Technology, Inc. | Systems, methods and devices for a CMOS imager having a pixel output clamp |
US20090040326A1 (en) * | 2007-08-09 | 2009-02-12 | Micron Technology, Inc | Methods and apparatuses for supplying current using a digital sequence |
US7964929B2 (en) * | 2007-08-23 | 2011-06-21 | Aptina Imaging Corporation | Method and apparatus providing imager pixels with shared pixel components |
US7531373B2 (en) * | 2007-09-19 | 2009-05-12 | Micron Technology, Inc. | Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry |
US7569803B2 (en) * | 2007-10-04 | 2009-08-04 | Aptina Imaging Corporation | Biasing apparatus, systems, and methods |
US7859580B2 (en) | 2007-10-16 | 2010-12-28 | Aptina Imaging Corporation | Method and apparatus for anisotropic demosaicing of image data |
US8086034B2 (en) * | 2008-02-05 | 2011-12-27 | Aptina Imaging Corporation | System and method for reducing color artifacts in digital images |
US8270713B2 (en) * | 2007-10-16 | 2012-09-18 | Aptina Imaging Corporation | Method and apparatus providing hardware-efficient demosaicing of image data |
US8131072B2 (en) * | 2007-11-26 | 2012-03-06 | Aptina Imaging Corporation | Method and apparatus for reducing image artifacts based on aperture-driven color kill with color saturation assessment |
US7881595B2 (en) * | 2007-12-21 | 2011-02-01 | Aptina Imaging Corporation | Image stabilization device and method |
US7940315B2 (en) * | 2008-01-07 | 2011-05-10 | Aptina Imaging Corporation | Method and apparatus for identification and correction of aberrant pixels in an image sensor |
US7924317B2 (en) * | 2008-03-12 | 2011-04-12 | Aptina Imaging Corporation | Method and apparatus for reducing motion blur in digital images |
US7729055B2 (en) * | 2008-03-20 | 2010-06-01 | Aptina Imaging Corporation | Method and apparatus providing concave microlenses for semiconductor imaging devices |
EP4020976A1 (en) * | 2008-04-07 | 2022-06-29 | Cmosis NV | Pixel array |
JP5243984B2 (en) * | 2009-01-30 | 2013-07-24 | 浜松ホトニクス株式会社 | Solid-state image sensor with built-in electron multiplication function |
US9131142B2 (en) | 2009-07-17 | 2015-09-08 | Nikon Corporation | Focusing device and camera |
US8093673B2 (en) | 2009-07-31 | 2012-01-10 | Aptina Imaging Corporation | Columnated backside illumination structure |
JP5274424B2 (en) | 2009-10-07 | 2013-08-28 | 本田技研工業株式会社 | Photoelectric conversion element, light receiving device, light receiving system, and distance measuring device |
JP5211007B2 (en) * | 2009-10-07 | 2013-06-12 | 本田技研工業株式会社 | Photoelectric conversion element, light receiving device, light receiving system, and distance measuring device |
JP5211008B2 (en) | 2009-10-07 | 2013-06-12 | 本田技研工業株式会社 | Photoelectric conversion element, light receiving device, light receiving system, and distance measuring device |
US8847911B2 (en) | 2011-04-05 | 2014-09-30 | Cypress Semiconductor Corporation | Circuit to provide signal to sense array |
KR102307376B1 (en) * | 2015-06-09 | 2021-10-06 | 에스케이하이닉스 주식회사 | Image sensing device and read-out method of the same |
KR102426494B1 (en) * | 2015-07-07 | 2022-07-27 | 삼성전자주식회사 | Charge pump and devices having the same |
DE102016223354B4 (en) * | 2016-11-24 | 2022-06-02 | Infineon Technologies Ag | Switching circuit arrangement, DC voltage interface and method for operating a switching circuit arrangement |
KR102573304B1 (en) * | 2018-06-27 | 2023-08-31 | 삼성전자 주식회사 | Image sensor, pixel array and operation method thereof |
Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4374700A (en) * | 1981-05-29 | 1983-02-22 | Texas Instruments Incorporated | Method of manufacturing silicide contacts for CMOS devices |
US4820936A (en) * | 1987-05-29 | 1989-04-11 | U.S. Philips Corp. | Integrated CMOS circuit comprising a substrate bias voltage generator |
US5038325A (en) * | 1990-03-26 | 1991-08-06 | Micron Technology Inc. | High efficiency charge pump circuit |
US5126692A (en) * | 1987-08-03 | 1992-06-30 | Western Digital Corporation | Variable frequency system having linear combination of charge pump and voltage controlled oscillator |
US5287393A (en) * | 1991-01-18 | 1994-02-15 | Nec Corporation | Charge transfer device equipped with charge signal detector improved in sensitivity as well as in voltage amplification |
US5319604A (en) * | 1990-05-08 | 1994-06-07 | Texas Instruments Incorporated | Circuitry and method for selectively switching negative voltages in CMOS integrated circuits |
US5323052A (en) * | 1991-11-15 | 1994-06-21 | Sharp Kabushiki Kaisha | Image pickup device with wide angular response |
US5324958A (en) * | 1991-02-19 | 1994-06-28 | Synaptics, Incorporated | Integrating imaging systgem having wide dynamic range with sample/hold circuits |
US5461425A (en) * | 1994-02-15 | 1995-10-24 | Stanford University | CMOS image sensor with pixel level A/D conversion |
US5471515A (en) * | 1994-01-28 | 1995-11-28 | California Institute Of Technology | Active pixel sensor with intra-pixel charge transfer |
US5541402A (en) * | 1994-10-17 | 1996-07-30 | At&T Corp. | Imaging active pixel device having a non-destructive read-out gate |
US5576763A (en) * | 1994-11-22 | 1996-11-19 | Lucent Technologies Inc. | Single-polysilicon CMOS active pixel |
US5612799A (en) * | 1990-11-26 | 1997-03-18 | Semiconductor Energy Laboratory Co., Inc. | Active matrix type electro-optical device |
US5614744A (en) * | 1995-08-04 | 1997-03-25 | National Semiconductor Corporation | CMOS-based, low leakage active pixel array with anti-blooming isolation |
US5625210A (en) * | 1995-04-13 | 1997-04-29 | Eastman Kodak Company | Active pixel sensor integrated with a pinned photodiode |
US5689208A (en) * | 1995-04-11 | 1997-11-18 | International Rectifier Corporation | Charge pump circuit for high side switch |
US5705846A (en) * | 1995-07-31 | 1998-01-06 | National Semiconductor Corporation | CMOS-compatible active pixel image array using vertical pnp cell |
US5708263A (en) * | 1995-12-27 | 1998-01-13 | International Business Machines Corporation | Photodetector array |
US5757045A (en) * | 1996-07-17 | 1998-05-26 | Taiwan Semiconductor Manufacturing Company Ltd. | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation |
US20030029989A1 (en) * | 1997-09-16 | 2003-02-13 | Roger Stettner | High data rate smart sensor |
-
1998
- 1998-10-14 US US09/172,301 patent/US6140630A/en not_active Ceased
-
2002
- 2002-10-30 US US10/283,165 patent/USRE39768E1/en not_active Expired - Lifetime
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4374700A (en) * | 1981-05-29 | 1983-02-22 | Texas Instruments Incorporated | Method of manufacturing silicide contacts for CMOS devices |
US4820936A (en) * | 1987-05-29 | 1989-04-11 | U.S. Philips Corp. | Integrated CMOS circuit comprising a substrate bias voltage generator |
US5126692A (en) * | 1987-08-03 | 1992-06-30 | Western Digital Corporation | Variable frequency system having linear combination of charge pump and voltage controlled oscillator |
US5038325A (en) * | 1990-03-26 | 1991-08-06 | Micron Technology Inc. | High efficiency charge pump circuit |
US5319604A (en) * | 1990-05-08 | 1994-06-07 | Texas Instruments Incorporated | Circuitry and method for selectively switching negative voltages in CMOS integrated circuits |
US5612799A (en) * | 1990-11-26 | 1997-03-18 | Semiconductor Energy Laboratory Co., Inc. | Active matrix type electro-optical device |
US5287393A (en) * | 1991-01-18 | 1994-02-15 | Nec Corporation | Charge transfer device equipped with charge signal detector improved in sensitivity as well as in voltage amplification |
US5324958A (en) * | 1991-02-19 | 1994-06-28 | Synaptics, Incorporated | Integrating imaging systgem having wide dynamic range with sample/hold circuits |
US5323052A (en) * | 1991-11-15 | 1994-06-21 | Sharp Kabushiki Kaisha | Image pickup device with wide angular response |
US5471515A (en) * | 1994-01-28 | 1995-11-28 | California Institute Of Technology | Active pixel sensor with intra-pixel charge transfer |
US5461425A (en) * | 1994-02-15 | 1995-10-24 | Stanford University | CMOS image sensor with pixel level A/D conversion |
US5541402A (en) * | 1994-10-17 | 1996-07-30 | At&T Corp. | Imaging active pixel device having a non-destructive read-out gate |
US5576763A (en) * | 1994-11-22 | 1996-11-19 | Lucent Technologies Inc. | Single-polysilicon CMOS active pixel |
US5689208A (en) * | 1995-04-11 | 1997-11-18 | International Rectifier Corporation | Charge pump circuit for high side switch |
US5625210A (en) * | 1995-04-13 | 1997-04-29 | Eastman Kodak Company | Active pixel sensor integrated with a pinned photodiode |
US5705846A (en) * | 1995-07-31 | 1998-01-06 | National Semiconductor Corporation | CMOS-compatible active pixel image array using vertical pnp cell |
US5614744A (en) * | 1995-08-04 | 1997-03-25 | National Semiconductor Corporation | CMOS-based, low leakage active pixel array with anti-blooming isolation |
US5708263A (en) * | 1995-12-27 | 1998-01-13 | International Business Machines Corporation | Photodetector array |
US5757045A (en) * | 1996-07-17 | 1998-05-26 | Taiwan Semiconductor Manufacturing Company Ltd. | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation |
US20030029989A1 (en) * | 1997-09-16 | 2003-02-13 | Roger Stettner | High data rate smart sensor |
Non-Patent Citations (24)
Title |
---|
Ahou, Z., et al., A Digital CMOS Active Pixel Image Sensor For Multimedia Applications, Proc. SPIE vol. 2894, Sep. 1996, pp. 282-288. * |
Dickinson, A. et al., A256x256 CMOS Active Pixel Image Sensor with Motion Detection, 1995 IEEE International Solid-State Circuits Conference, pp. 226-227. * |
Dickinson, A. et al., Standard CMOS Active Pixel Image Sensors for Multimedia Applications, Proceedings of Sixteenth Conference on Advanced Research in VLSI, Mar. 27-29, 1995, pp. 214-224. * |
Eid, E_S., et al., A256x256 CMOS Active Pixel Image Sensor, Proc. SPIE vol. 2415, Apr. 1995, pp. 265-275. * |
Fossum, E. CMOS Image Sensors: Electronic Camera On a Chip, 1995 IEEE, pp. 17-25. * |
Fossum, E. et al., IEDM A 37x28mm 600k-Pixel CMOS APS Dental X-Ray Camera-on-a-Chip with Self-Triggered Readout, 1998 IEEE International Solid-State Crcuits Conference, pp. 172-173. * |
Fossum, E., Architectures for focal plane image processing, Optical Engineering, vol. 28, No. 8, Aug. 1989, ppd. 865-871. * |
Fossum, E., Low Power Camera-on-a-Chip Using CMOS Active Pixel sensor Technology, 1995 IEEE, pp. 74-77. * |
Janesick, J., et al., New advancements in charge-coupled device technology-sub-electron noise and 4096x4096 pixel CCDs, Proc. SPIE vol. 1242, 1990, pp. 223-237. * |
Kemeny, S. E., et al., Update on folca-plane image processing research, Proc. SPIE vol. 1447, 1991, pp. 243-250. * |
Mendis, S. K. et al., CMOS Active Pixel Image Sensors for High Integrated Imaging Systems, IEEE Journal of Solid-State Circuits, vol. 32, No. 2, Feb. 1997, pp. 187-197. * |
Mendis, S. K., et al., A128x128 CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems, 1993 IEEE, pp. 583-586. * |
Mendis, S. K., et al., Low-Light-Level Image Sensor with On-Chip Signal Processing, Proc. SPIE vol. 1952, Nov. 1993, pp. 23-33. * |
Mendis, S. K., et al., Progressin In CMOS Active Pixel Image Sensors, Proc. Spie vol. 2172, May 1994, pp. 19-29. * |
Mendis, S., et al., CMOS Active Pixel Image Sensor, IEEE Transactions on Electron Devices, vol. 41, No. 3, Mar. 1994, pp. 452-453. * |
Nakamura, J., et al., CMOS Active Pixel Image Sensor with Simple Floating Gate Pixels, IEE Transctions on Electron Devices, vol. 42, No. 9, Sep. 1995, pp. 1693-1694. * |
Nixon, R. H., et al., 256x256 CMOS Active Pixel Sensor Cameral-on-a-Chip, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2046-2050. * |
Nixon, R. H., et al., 256x256 CMOS Active Pixel Sensor Camera-on-a-Chip, 1996 IEEE Internation Solid-Stated Circuits Conference, pp. 178-179. * |
Panicacci, R., et al., 128 Mb/s Multiport CMOS Binary Acitve-Pixel Image Sensor, 1996 IEEE International Solid-State Circuit Conference, pp. 100-101. * |
Panicaci, R., et al., Programmable multiresolution CMOS Active-Pixel Image Sensor, Proc SPIE vol. 2654, Mar. 1996, pp. 72-79. * |
Yadid-Pecht, O., et al., CMOS Active Pixel Sensor Star Tracker with Regional Electronic Shutter, IEEE Journal of Solid-State Circuits, vol. 32, No. 2, Feb. 1997, pp. 285-288. * |
Yadid-Pecht, O., et al., Wide dynamic range APS star tracker, Proc. SPIE vol. 2654, Mar. 1996, pp. 82-92. * |
Zarnowski, J., et al., Imaging options expand with CMOS technology, Laser Focus World, Jun. 1997, pp. 125-130. * |
Zhou, Z., et al., A CMOS Imager with On-Chip Variable Resolution for Light-Adaptive Imaging, 1998 IEEE International Solid-State Circuits Conference, pp. 174-175. * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040252211A1 (en) * | 2003-06-16 | 2004-12-16 | Rhodes Howard E. | Pumps for CMOS imagers |
US20060285000A1 (en) * | 2003-09-10 | 2006-12-21 | Keiji Mabuchi | Semiconductor device, and control method and device for driving unit component of semiconductor device |
US7511275B2 (en) * | 2003-09-10 | 2009-03-31 | Sony Corporation | Semiconductor device, and control method and device for driving unit component of semiconductor device |
US20050280724A1 (en) * | 2003-12-03 | 2005-12-22 | Sanyo Electric Co., Ltd. | Image signal-processing device, method for processing image signal, image signal-processing program product, control device for solid image capturing element, and method for controlling solid image capturing element |
US20060017714A1 (en) * | 2004-07-20 | 2006-01-26 | Kazuya Yonemoto | Solid-state imaging apparatus and sampling circuit |
US7408539B2 (en) * | 2004-07-20 | 2008-08-05 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging apparatus and sampling circuit |
WO2009058467A1 (en) * | 2007-10-29 | 2009-05-07 | Fairchild Imaging, Inc. | Cmos sensor adapted for dental x-ray imaging |
Also Published As
Publication number | Publication date |
---|---|
US6140630A (en) | 2000-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE39768E1 (en) | VCC pump for CMOS imagers | |
US7616245B2 (en) | Active pixel sensor with a diagonal active area | |
US7446807B2 (en) | Imager pixel with capacitance for boosting reset voltage | |
US7465602B2 (en) | Anti-blooming storage pixel | |
US6723594B2 (en) | Pixel cell with high storage capacitance for a CMOS imager | |
US6825878B1 (en) | Twin P-well CMOS imager | |
US8026969B2 (en) | Pixel for boosting pixel reset voltage | |
US6858460B2 (en) | Retrograde well structure for a CMOS imager | |
US7224009B2 (en) | Method for forming a low leakage contact in a CMOS imager | |
US6630701B1 (en) | Buried channel CMOS imager and method of forming same | |
US6740915B1 (en) | CMOS imager cell having a buried contact | |
US20100297807A1 (en) | Cmos imager having a nitride dielectric |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: APTINA IMAGING CORPORATION, CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038274/0385 Effective date: 20080926 |
|
AS | Assignment |
Owner name: MICRON TECHNOLOGY INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RHODES, HOWARD E.;REEL/FRAME:038205/0159 Effective date: 19981012 |