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USRE38918E1 - System and method for power-efficient charging and discharging of a capacitive load from a single source - Google Patents

System and method for power-efficient charging and discharging of a capacitive load from a single source Download PDF

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USRE38918E1
USRE38918E1 US09758631 US75863101A USRE38918E1 US RE38918 E1 USRE38918 E1 US RE38918E1 US 09758631 US09758631 US 09758631 US 75863101 A US75863101 A US 75863101A US RE38918 E1 USRE38918 E1 US RE38918E1
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capacitive
load
switch
system
voltage
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US09758631
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Lars G. Svensson
William C. Athas
Jeffrey G. Koller
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University of Southern California (USC)
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University of Southern California (USC)
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Abstract

A system and method for efficiently charging and discharging a capacitive load from a single voltage source. The system includes a brat switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may he common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged. In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application and Reissue application Ser. No. 08/986,327, filed Dec. 5, 1997 (now U.S. Patent No. RE37,552, issued Feb. 19, 2002 ) are both reissue applications for U.S. Pat. No. 5,473,526, issued Dec. 5,1991. This application is a continuation of U.S. Pat. No. RE37,552.

This invention was made with government support under DABT-63-92-C-0052 awarded by ARPA. The government has certain rights in the invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to electronic circuits and systems. More specifically, the present invention relates to power dissipation in electrode circuits and systems.

2. Description of the Related Art

Power dissipation of electronic circuitry is an important design consideration for many applications. Power dissipation provides a measure of the efficiency of the system. The efficiency of the system impacts the design of the power supply for the system. That is, low efficiency leads to higher costs due to the waste of energy and the need for larger power supplies.

For battery powered systems, power dissipation limits battery life. This necessitates larger batteries which increases the cost and weight of the system while limiting the applicability thereof. As an example, consider coronary pacemakers where power dissipation is a critical concern due to the difficultly of accessing the battery for replacement and the cost and inconvenience associated with the use of larger batteries.

In addition, the dissipated energy is released in the form of heat. Accordingly, systems which exhibit considerable power dissipation often require measures such as heat sinks to protect or cool system components from the heat created by the circuit. The use of heat sinks and the like adds to the cost, size and weight of the system and thereby limits the utility of same.

For the CMOS (complementary-oxide semiconductor) based system, used widely in the design of computers, digital logic circuits and the like, capacitive effects are primarily responsible for the dissipation of power. Such capacitive effects arise due to junction capacitances within semiconductor devices, intended capacitances between lines connecting the circuit to external devices and the capacitance of a load.

In accordance with conventional teachings, power dissipation is directly related to the operating frequency (f), the capacitance (C) and the square of the voltage (V2) applied to the capacitive element.

In addition to the elimination of unnecessary capacitances and the reduction of the switching frequency to the lowest value that supports the functional specification of the circuit, most prior approaches to the problem have focused on reducing the voltage applied to the capacitive elements. However, in addition to costly interfacing issues, attempts to lower the voltage of digital processors and the like have been limited by the fact that the trend is to higher processing speeds which cannot be attained at arbitrarily low operating voltages.

Thus, there is an ongoing need in the art for a system and technique for minimizing the power dissipated by a digital system.

SUMMARY OF THE INVENTION

The need in the art is addressed by the present invention which, in a most general sense, provides a system and method for efficiently charging and discharging a capacitive load from a single voltage source. The inventive system includes a first switch for selectively connecting the voltage source to the load and a second switch for selectively providing a short across the load as may be common in the art. A particularly novel aspect of the invention resides in the provision of plural capacitive elements and a switching mechanism for selectively connecting each of the capacitive elements to the load whereby the load is gradually charged or discharged.

In the illustrative embodiment, the switching mechanism includes a set of switches for selectively connecting each of the capacitive elements to the capacitive load and a switch control mechanism for selectively activating the switches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified representation of a conventional driver for a capacitive load.

FIG. 2 shows a system for charging the load capacitance by several steps and thereby reducing power dissipation.

FIG. 3 is a simplified schematic of a preferred embodiment of the circuit of the present invention for reducing the power dissipation of a capacitive load.

FIG. 4 is a diagram showing the control circuit of the driver constructed in accordance with the teachings of the present invention.

FIG. 5 is a timing diagram which illustrates the operation of the driver of the present invention.

DESCRIPTION OF THE INVENTION

Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention,

While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof.

Most of the power dissipation in digital CMOS circuits is due to repeated chug” and discharging of capacitive loads including those internal to the circuit end those associated with the output signals.

FIG. 1 is a simplified representation of a conventional driver for a capacitive load. The load CL represents the capacitance of a load and the interlead capacitance of the lines connecting the driver 10′ to the load 12′. The load 12′ is charged to the supply voltage V by connecting the load 12′ to the power rail via a first switch 14′. In practice, the switch 14′ may be a metal-oxide semiconductor field-effect transistor (MOSFET) which has a nominal “on” resistance. When the switch 14′ is closed, a charge CV passes through the resistance of the switch 14′. The voltage drop across the resistance varies from an initial value of V to a final value of zero, so the average voltage drop V′ traversed by the charge is V/2, if the capacitance is linear. The energy dissipated is:
Econv=QV1=CV (V/2)=CV2/2  [1]
A similar argument applies to the discharge process, so a complete conventional charge-discharge cycle dissipates all the energy provided by the power supply, QV=CV2.

In accordance with the present teachings, power dissipation is reduced by charging the capacitance of the load CL in several steps. This is illustrated in FIG. 2

FIG. 2 shows a system 10 for charging the load capacitance by several steps and thereby reducing power dissipation. Here, a bank of supply voltages V1 to VN are used to charge the load 12. The voltages of the supplies are evenly distributed between ground and VN so that the voltage difference between any two adjacent supplies is the same. Each of the voltages is selectively applied to the load 12 by N switches including the first switch 14 and N−1 additional switches. Between charge cycles, switch 0 is closed. To charge the load, switch 0 is opened and the supplies V1 through VN are connected to the load in succession by selectively closing the switches, that is, by momentarily closing switch 1, opening switch 1, momentarily closing switch 2 etc. To discharge the load, the supplies VN−1 through V1 are switched in in reverse order. Then switch 0 is closed connecting the output to ground.

If N steps are used, the dissipation per step is again given by the transferred charge and the average voltage drop across isle switch resistance:
Estep=QV′=(CV/N) (V/2N)=CV2/2N2   [2]
To charge the capacitance all the way to the supply voltage V, N steps are used, so the total energy dissipation is: E stepwtan = N * E step = N * CV 2 / 2 N 2 = CV 2 / 2 N = E conv / N [ 3 ]
Again, a full charge-discharge cycle will cause twice the dissipation of the charging only. Thus, according to this simplified analysis, charging by several steps reduces the energy dissipation per charge-discharge cycle and thereby the total power dissipation, by a factor of N.

The multiple supply voltages of FIG. 2 may be generated with a battery stack. For equipment to powered by batteries or when the desired voltage increment is not a multiple of the battery cell voltage, a power supply unit would seemingly have to generate these multiple supply voltage with an associated cost in expense, complexity and power dissipation.

FIG. 3 is a simplified schematic of a preferred embodiment of the circuit of the present invention for reducing the power dissipation of a capacitive load. The circuit 100 is essentially identical to that of FIG. 2 with the exception that the supplies V1−VN−1 are replaced with a corresponding number of capacitors CT 18 which will be referred to as “tank” capacitors. Each tank capacitor CT has a capacitance which is much, much larger (e.g. an order of magnitude) than the load capacitance CL. Switch operations are sequenced by a control circuit 20.

FIG. 4 is a diagram showing the control circuit 20 interconnected to plural MOSFET switches for an N=6 implementation of the driver constructed in accordance with the teachings of the present invention. In FIG. 4, the tank capacitors 18 are eliminated for simplicity. The control signals may be provided by the circuit 20 or may be supplied by a host microprocessor. The control circuit 20 may be implemented in several configurations. For example, the control circuit may be implemented with a microprocessor or with a shift register and a counter. In the alternative, a latch 22 and input and output logic circuits 14 and 26, respectively, may be used as shown in FIG. 4. The input and output loge circuits may be designed by a computer aided logic design program of which several are currently available. If a computer aided logic design program is used, the desired outputs would be specified in response to the expected input signals. The program would then design the logic circuits.

Timing signals are provided by a system clock (not shown) through the latch 22. In practice, the clock rate should be at least (N+1) times the output signal rate. In the preferred embodiment, switches 0-4 are implemented with n-channel MOSFET devices. Switches 5 and 6 are implemented with p-channel devices.

FIG. 5 is a timing diagram which illustrates the operation of the driver 100 of the present invention. In FIG. 5(a), the clock pulse are shown. The input signal is shown in FIG. 5(b). FIGS. 5(c)-(i) show the controls for switch 0-6 and FIG. 5(j) shows the output at the load CL.

The operation of the circuits of FIGS. 3 and 4 is essentially the same as that of FIG. 2. That is, in the initial standby condition switch 0 is closed and them is no charge on any of the capacitors in the system. Next, when an input pulse is to be transferred to the load, switch 0 is opened and switch 1 is closed. Since there is no charge on the load, CL nor on any of the tank capacitors CT, there will be no charge transfer through any of the switches as each is closed, in turn, momentarily. When the first switch 14 is closed, a charge is applied to the load 12.

On the trailing edge of input pulse, a discharge cycle is initiated by when the switches are momentarily closed in reverse order Thus, switch N is opened and switch N−1 is closed Then switch N−1 is opened and switch N−2 is closed and etc. On the closure of switch N−1, the associated tank capacitor will receive most of the charge on the load capacitance. Each capacitor down the line will receive a lower charge than the immediately proceeding capacitor. After switch 1 opens, switch 0 closes to complete the cycle dumping the remaining charge on the load CL to ground. Thus, over several cycles the tank capacitors will approach their steady state voltage, for example, the (N−1)th through 1st tank capacitor may have charges of say 5, 4, 3, 2 and 1 volts respectively. Than, at the beginning of the next cycle, on the closure of the first switch, the voltage on the first tank capacitor is applied to the load, then the voltage on the second capacitor is applied to the load and so on. Thus, in the example, first 1 volt is applied to the load, then 2 volts, then three volts and etc. As a result, the voltage on the load will gradually increase as shown in FIG. 5(j).

The circuits of FIG. 3 and 4 will provide the same power dissipation reduction as that of FIG. 2, but without multiply supply lines and without complicating the power supply. This is illustrated by the following analysis. Assume that each tank capacitor CT is charged to the voltage of the corresponding supply of FIG. 2 and that the load capacitance CL is discharged The load capacitance is charged by closing and opening switches 1 through N in succession. Each tank capacitor (and the power supply) delivers a charge given by:
q=CLV/N  [4]
Since the tank capacitors are much larger than the load, the tank voltages do not change significantly, so the dissipation in the switches will be the same as for the case in FIG. 2, where the supply voltages are constant. To discharge the load capacitance, switches N−1 through 0 are closed and opened in succession. During the discharge, each tank capacitor receive a charge of the same size as that delivered during charge phase, and an equally sized charge is dumped to ground via switch 0. Over the full charge-discharge cycle, only the power supply injects any charge into the circuit. No net charge is drawn from any tank capacitor, so the tank voltages do not change.

The voltages of the tank capacitor bank are self-stabilizing. To appreciate this, assume that the voltage of one of the tank capacitors is slightly higher than it should be. Then, the charge delivered by this tank capacitor during the charging of the load will be somewhat larger then that given by equation [4], since the “step” from the voltage below is now slightly larger. During the discharge phase, the step from the voltage above is slightly smaller and the charge received is therefore smaller as well. Therefore, over the full cycle, a net decrease of the charge on the storage capacitor occurs, which causes a decrease in the capacitor voltage. The initial deviance is automatically counteracted.

Even if the tank capacitor voltages differ from the “correct” values, the circuit will work logically correctly, since each charging (discharging) cycle ends by connecting the load to be supply rail (ground). Voltage deviations simply bring higher dissipation. This happens during start-up, before the tank voltages have had time to converge to the even distribution between the supply voltage and ground.

The implementation coat of a driver such as that shown in FIG. 3 is determined by the tank capacitors, the switches, the mechanism controlling the switches, and the interconnections of same. Note that all extra interconnections are local. As for the conventional case, only one connection to the power supply is needed. Also, several drivers may share the same capacitor bank and part of the control mechanism.

The problem of maintaining the appropriate voltages on the tank capacitors is obviated by the fact that the capacitor voltages will converge automatically to the desired voltages No additional circuitry is required. Only one supply line most be routed to the chip and the power supply need not be any more complicated than a conventional supply. In practice, the tank capacitors would be located off-chip.

For a CMOS implementation, the following design procedure may be followed to provide a driver configuration which exhibits minimal power dissipation.

Equation [3] indicates that dissipation decreases monotonically with increasing N. The number N cannot, however, be usefully made arbitrarily large because each step requires that a switch be turned on and off, which itself causes dissipation. Also, the energy used to drive each switch depends on the width of the device, which should be just enough to allow the charging to complete before the next step commences. Then, for a given total allowable charging time “T”, these is sat optimal number of steps and a set of optimal device sizes which lead to minimal total dissipation determined as follows.

Again, consider the circuit in FIG. 3 and same the gates of the switch devices we driven conventionally. The load is charged and discharged once; the energy needed to drive the gates of the switch devices is. E sw = ( i = 1 N C i + i = 0 N - 1 C i ) V 2 [ 5 ]
Allot each step one Nth of the total charging time T. Then:
T/N=mRiCL  [6]
Here, m is the number of RC time constants spent waiting for each charging step to complete. From equation [6], it is evident that all the switch devices should have equal on-resistance: Ri=Rsw. Decreasing the on-resistance of device i by increasing the width means increasing the gate capacitance.
RiCii  [7]
ρi is a quality measure of the switch. It varies with i, since the bulk-to-channel and gate-to-channel voltages are different for different switches. Combining equations [5], [6], and [7] yields: E sw = Nm T ( i = 1 N ρi + i = 0 N - 1 ρi ) C L V 2 [ 8 ]
Introducing {overscore (ρ)}, a weighted average of ρ, for the different switches: ρ _ = 1 2 N ( i = 1 N ρi + i = 0 N - 1 ρi ) [ 9 ]
If N is sufficiently large, {overscore (ρ)} is close to the unweighed average of ρ over the entire voltage range. Combining equations [3], [8] and [9] yields the following expression for the total energy dissipation: E tot = ( 1 N + 2 N 2 m ρ _ T ) C L V 2 [ 10 ]
The number N that minimizes Etot is given by: N opt = T 4 m ρ _ 3 [ 11 ]
The corresponding energy dissipation is: E opt = 3 2 4 m ρ _ T 3 C L V 2 [ 12 ]
It remains to select the value for m. If it is chosen too small, there will still be a significant voltage across a switch when the next switch is to close. Hence, them is an increase in the average voltage across each switch and therefore a dissipation increase (the first term in equation [10] is changed slightly). If on the other hand to is chosen unnecessarily large, time is wasted that could have been used to increase the number of steps. Thus, in general, optimization methods for the value of to vary according to the application, however, one skilled in the at will be able to select a suitable value for to using conventional teachings (e.g., a simulation program).

By using the number of stages given by equation [10], the designer coo minimize the power dissipation of the driver. The minimum is rather shallow, however, so a lower N (as would most often be dictated by practical considerations) will still give a considerable improvement over the conventional case, N=2 already gives almost 50% reduction. Once N and m have been selected, the on-resistance of each switch is given by equation [6]. The corresponding gate capacitance, and thereby the width of the device, is given by equation [7]. The values of ρ for a certain process can be found by circuit simulation or by measuring the on-resistances of test devices of known widths.

Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications applications and embodiments within the scope thereof. For example, the switches may be closed in some other sequence as may be appropriate for a given application without departing from the scope of the present invention. In addition, alternative circuit topologies for the network of tank capacitors and switches may be appropriate. The second terminal of the load may be connected to a potentially variable) voltage other than ground.

It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.

Accordingly,

Claims (80)

1. A system for efficiently charging and discharging a capacitive lad from a single voltage source of a first potential consisting of:
a first switch for selectively charging the load;
a second switch for selectively discharging the load;
plural capacitive elements; and
switch means for selectively connecting each of the capacitive elements to the capacitive load to gradually charge or discharge the capacitive load.
2. The invention of claim 1 wherein said switch means includes plural third switches connected between said capacitive elements and said load.
3. The invention of claim 2 wherein said switch means includes means for selectively activating the first, second and third switches.
4. The invention of claim 3 wherein the capacitive load has a first terminal connected to the first switch and a second terminal connected to a source of a second potential.
5. The invention of claim 4 wherein the second switch has a first terminal connected to the first terminal of the load and a second terminal connected to said source of a second potential.
6. The invention of claim 5 wherein each of the third switches has a first terminal connected to the first terminal of the load and a second terminal connected to a first terminal of an associated one of the plural capacitive elements.
7. The invention of claim 6 wherein the means for selectively activating the first, second and third switches includes a finite state machine.
8. The invention of claim 7 wherein the finite state machine is designed to receive a clock signal and an input signal and provide selective activation signals for the first, second and third switches in response thereto.
9. The invention of claim 8 wherein a second terminal of each of the plural capacitive elements is connected to said source of a second potential.
10. The invention of claim 9 wherein each of the capacitive elements has a capacitance which is at least an order of magnitude greater than the capacitance of the load.
11. A method for efficiently charging and discharging a capacitive load from a single voltage source including the steps of:
providing a flat switch for selectively connecting the voltage source to the load;
providing a second switch for selectively providing a short across the load;
providing plural capacitive elements;
providing plural third switches for selectively connecting each of the capacitive elements to the capacitive load; and
selectively activating the first, second and third switches to gradually charge or discharge the capacitive load.
12. An apparatus for driving a capacitive load, comprising:
a voltage source; and
a switch network,
wherein the switch network is operable to electrically connect the capacitive load and the voltage source to drive the load to a first voltage level,
wherein the switch network is further operable to electrically connect the capacitive load and a capacitive storage system, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, a voltage level of the capacitive storage system tends to self stabilize to a second voltage level; and
wherein the switch network is further operable to cause charge to be transferred from the capacitive storage subsystem to the capacitive load and is still further operable to cause charge to be transferred from the capacitive load to the capacitive storage subsystem.
13. An apparatus as claimed in claim 12, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element.
14. An apparatus as claimed in claim 12, wherein the capacitive storage system comprises a plurality of capacitive elements.
15. An apparatus as claimed in claim 12, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system and the capacitive load are electrically floating.
16. An apparatus as claimed in claim 12, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected in parallel.
17. An apparatus as claimed in claim 12, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected such that a first terminal of the first capacitive element is electrically connected to a first terminal of the second capacitive element and a second terminal of the first capacitive element and a second terminal of the second capacitive element are electrically connected to a common potential.
18. An apparatus as claimed in claim 12, wherein the switch network comprises a plurality of switching elements.
19. An apparatus as claimed in claim 12, wherein the switch network comprises a plurality of MOS transistors.
20. An apparatus as claimed in claim 12, wherein a capacitance of the capacitive storage system is larger than a capacitance of the capacitive load.
21. An apparatus as claimed in claim 12, wherein a capacitance of the capacitive storage system is an order of magnitude larger than a capacitance of the capacitive load.
22. An apparatus as claimed in claim 12, wherein the apparatus is a driver.
23. An apparatus as claimed in claim 12, wherein the switch network is further operable to electrically connect the capacitive load and the voltage source to drive the capacitive load to a third voltage level wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network the capacitive load settles at a second voltage level between the first and third voltage levels, and wherein during operation of the apparatus the capacitive load is first driven to the first voltage, then subsequently settles at the second voltage level and then is subsequently driven to the third voltage level.
24. An apparatus comprising:
a capacitive load;
a voltage source;
a switch network; and
a capacitive storage system,
wherein the switch network is operable to electrically connect the capacitive load and the voltage source to drive the load to a first voltage level,
wherein the switch network is further operable to electrically connect the capacitive load and the capacitive storage system, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, a voltage level of the capacitive storage system tends to self stabilize to a second voltage level, and
wherein the switch network is further operable to cause charge to be transferred from the capacitive storage subsystem to the capacitive load and is still further operable to cause charge to be transferred from the capacitive load to the capacitive storage subsystem.
25. An apparatus as claimed in claim 24, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element.
26. An apparatus as claimed in claim 24, wherein the capacitive storage system comprises a plurality of capacitive elements.
27. An apparatus as claimed in claim 24, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network the capacitive storage system and the capacitive load are electrically floating.
28. An apparatus as claimed in claim 24, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected in parallel.
29. An apparatus as claimed in claim 24, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected such that a first terminal of the first capacitive element is electrically connected to a first terminal of the second capacitive element and a second terminal of the first capacitive element and a second terminal of the second capacitive element are electrically connected to a common potential.
30. An apparatus as claimed in claim 24, wherein the switch network comprises a plurality of switching elements.
31. An apparatus as claimed in claim 24, wherein the switch network comprises a plurality of MOS transistors.
32. An apparatus as claimed in claim 24, wherein a capacitance of the capacitive storage system is larger than a capacitance of the capacitive load.
33. An apparatus as claimed in claim 24, wherein a capacitance of the capacitive storage system is an order of magnitude larger than a capacitance of the capacitive load.
34. An apparatus as claimed in claim 24, wherein the switch network is further operable to electrically connect the capacitive load and the voltage source to drive the capacitive load to a third voltage level wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive load settles at a second voltage level between the first and third voltage levels, and wherein during operation of the apparatus, the capacitive load is first driven to the first voltage, then subsequently settles at the second voltage level, and then is subsequently driven to the third voltage level.
35. An apparatus for driving a capacitive load, comprising:
a voltage source; and
a switch network,
wherein the switch network is operable to electrically connect the capacitive load and the voltage source to drive the load to a first voltage level,
wherein the switch network is further operable to electrically connect the capacitive load and a capacitive storage system, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system is electrically isolated from the voltage source, and
wherein the switch network is further operable to cause charge to be transferred from the capacitive storage subsystem to the capacitive load and is still further operable to cause charge to be transferred from the capacitive load to the capacitive storage subsystem.
36. An apparatus as claimed in claim 35, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element.
37. An apparatus as claimed in claim 35, wherein the capacitive storage system comprises a plurality of capacitive elements.
38. An apparatus as claimed in claim 35, wherein when the capacitive storage system and the capacitive load are electrical connected by the switch network, the capacitive storage system and the capacitive load are electrically floating.
39. An apparatus as claimed in claim 35, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected in parallel.
40. An apparatus as claimed in claim 35, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected such that a first terminal of the first capacitive element is electrically connected to a first terminal of the second capacitive element and a second terminal of the first capacitive element and a second terminal of the second capacitive element are electrically connected to a common potential.
41. An apparatus as claimed in claim 35, wherein the switch network comprises a plurality of switching elements.
42. An apparatus as claimed in claim 35, wherein the switch network comprises a plurality of MOS transistors.
43. An apparatus as claimed in claim 35, wherein a capacitance of the capacitive storage system is larger than a capacitance of the capacitive load.
44. An apparatus as claimed in claim 35, wherein a capacitance of the capacitive storage system is an order of magnitude larger than a capacitance of the capacitive load.
45. An apparatus as claimed in claim 35, wherein the apparatus is a driver.
46. An apparatus as claimed in claim 35, wherein the switch network is further operable to electrically connect the capacitive load and the voltage source to drive the capacitive load to a third voltage level, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive load settles at a second voltage level between the first and third voltage levels, and wherein during operation of the apparatus, the capacitive load is first driven to the first voltage, then subsequently settles at the second voltage level, and then is subsequently driven to the third voltage level.
47. An apparatus comprising:
a capacitive load;
a voltage source;
a switch network; and
a capacitive storage system,
wherein the switch network is operable to electrically connect the capacitive load and the voltage source to drive the load to a first voltage level,
wherein the switch network is further operable to electrically connect the capacitive load and the capacitive storage system, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system is electrically isolated from the voltage source, and
wherein the switch network is further operable to cause charge to be transferred from the capacitive storage subsystem to the capacitive load and is still further operable to cause charge to be transferred from the capacitive load to the capacitive storage subsystem.
48. An apparatus as claimed in claim 47, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element.
49. An apparatus as claimed in claim 47, wherein the capacitive storage system comprises a plurality of capacitive elements.
50. An apparatus as claimed in claim 47, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system and the capacitive load are electrically floating.
51. An apparatus as claimed in claim 47, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected in parallel.
52. An apparatus as claimed in claim 47, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected such that a first terminal of the first capacitive element is electrically connected to a first terminal of the second capacitive element and a second terminal of the first capacitive element and a second terminal of the second capacitive element are electrically connected to a common potential.
53. An apparatus as claimed in claim 47, wherein the switch network comprises a plurality of switching elements.
54. An apparatus as claimed in claim 47, wherein the switch network comprises a plurality of MOS transistors.
55. An apparatus as claimed in claim 47, wherein a capacitance of the capacitive storage system is larger than a capacitance of the capacitive load.
56. An apparatus as claimed in claim 47, wherein a capacitance of the capacitive storage system is an order of magnitude larger than a capacitance of the capacitive load.
57. An apparatus as claimed in claim 47, wherein the switch network is further operable to electrically connect the capacitive load and the voltage source to drive the capacitive load to a third voltage level, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive load settles at a second voltage level between the first and third voltage levels, and wherein during operation of the apparatus, the capacitive load is first driven to the first voltage, then subsequently settles at the second voltage level, and then is subsequently driven to the third voltage level.
58. An apparatus for driving a capacitive load, comprising:
a voltage source; and
a switch network,
wherein the switch network is operable to electrically connect the capacitive load and the voltage source to drive the load to a first voltage level,
wherein the switch network is further operable to electrically connect the capacitive load and a capacitive storage system, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system and the capacitive load are electrically floating, and
wherein the switch network is further operable to cause charge to be transferred from the capacitive storage subsystem to the capacitive load and is still further operable to cause charge to be transferred from the capacitive load to the capacitive storage subsystem.
59. An apparatus as claimed in claim 58, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element.
60. An apparatus as claimed in claim 58, wherein the capacitive storage system comprises a plurality of capacitive elements.
61. An apparatus as claimed in claim 58, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system and the capacitive load are electrically disconnected from the voltage source.
62. An apparatus as claimed in claim 58, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network the first and second capacitive elements are electrically connected in parallel.
63. An apparatus as claimed in claim 58, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected such that a first terminal of the first capacitive element is electrically connected to a first terminal of the second capacitive element and a second terminal of the first capacitive element and a second terminal of the second capacitive element are electrically connected to a common potential.
64. An apparatus as claimed in claim 58, wherein the switch network comprises a plurality of switching elements.
65. An apparatus as claimed in claim 58, wherein the switch network comprises a plurality of MOS transistors.
66. An apparatus as claimed in claim 58, wherein a capacitance of the capacitive storage system is larger than a capacitance of the capacitive load.
67. An apparatus as claimed in claim 58, wherein a capacitance of the capacitive storage system is an order of magnitude larger than a capacitance of the capacitive load.
68. An apparatus as claimed in claim 58, wherein the apparatus is a driver.
69. An apparatus as claimed in claim 58, wherein the switch network is further operable to electrically connect the capacitive load and the voltage source to drive the capacitive load to a third voltage level, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive load settles at a second voltage level between the first and third voltage levels, and wherein during operation of the apparatus, the capacitive load is first driven to the first voltage, then subsequently settles at the second voltage level, and then is subsequently driven to the third voltage level.
70. An apparatus comprising:
a capacitive load;
a voltage source;
a switch network; and
a capacitive storage system,
wherein the switch network is operable to electrically connect the capacitive load and the voltage source to drive the load to a first voltage level,
wherein the switch network is further operable to electrically connect the capacitive load and the capacitive storage system, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system and the capacitive load are electrically floating, and
wherein the switch network is further operable to cause charge to be transferred from the capacitive storage subsystem to the capacitive load and is still further operable to cause charge to be transferred from the capacitive load to the capacitive storage subsystem.
71. An apparatus as claimed in claim 70, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element.
72. An apparatus as claimed in claim 70, wherein the capacitive storage system comprises a plurality of capacitive elements.
73. An apparatus as claimed in claim 70, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive storage system and the capacitive load are electrically disconnected from the voltage source.
74. An apparatus as claimed in claim 70, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected in parallel.
75. An apparatus as claimed in claim 70, wherein the capacitive load comprises a first capacitive element and the capacitive storage system comprises a second capacitive element, and wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the first and second capacitive elements are electrically connected such that a first terminal of the first capacitive element is electrically connected to a first terminal of the second capacitive element and a second terminal of the first capacitive element and a second terminal of the second capacitive element are electrically connected to a common potential.
76. An apparatus as claimed in claim 70, wherein the switch network comprises a plurality of switching elements.
77. An apparatus as claimed in claim 70, wherein the switch network comprises a plurality of MOS transistors.
78. An apparatus as claimed in claim 70, wherein a capacitance of the capacitive storage system is larger than a capacitance of the capacitive load.
79. An apparatus as claimed in claim 70, wherein a capacitance of the capacitive storage system is an order of magnitude larger than a capacitance of the capacitive load.
80. An apparatus as claimed in claim 70, wherein the switch network is further operable to electrically connect the capacitive load and the voltage source to drive the capacitive load to a third voltage level, wherein when the capacitive storage system and the capacitive load are electrically connected by the switch network, the capacitive load settles at a second voltage level between the first and third voltage levels, and wherein during operation of the apparatus, the capacitive load is first driven to the first voltage, then subsequently settles at the second voltage level and then is subsequently driven to the third voltage level.
US09758631 1994-04-22 2001-01-10 System and method for power-efficient charging and discharging of a capacitive load from a single source Expired - Lifetime USRE38918E1 (en)

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US08231637 US5473526A (en) 1994-04-22 1994-04-22 System and method for power-efficient charging and discharging of a capacitive load from a single source
US08986327 USRE37552E1 (en) 1994-04-22 1997-12-05 System and method for power-efficient charging and discharging of a capacitive load from a single source
US09758631 USRE38918E1 (en) 1994-04-22 2001-01-10 System and method for power-efficient charging and discharging of a capacitive load from a single source
US11040608 USRE42066E1 (en) 1994-04-22 2005-01-21 System and method for power-efficient charging and discharging of a capacitive load from a single source

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070126289A1 (en) * 2005-12-07 2007-06-07 Chung-Fan Liu Electronic switching device with uninterruptible voltage regulating switch
US20080012843A1 (en) * 2006-06-30 2008-01-17 Sony Corporation D/a converter circuit, liquid crystal driving circuit, and liquid crystal device
US7414460B1 (en) 2006-03-31 2008-08-19 Integrated Device Technology, Inc. System and method for integrated circuit charge recycling
US9285851B2 (en) 2012-06-22 2016-03-15 Microsoft Technology Licensing, Llc Optimizing battery use for known future load
US9696782B2 (en) 2015-02-09 2017-07-04 Microsoft Technology Licensing, Llc Battery parameter-based power management for suppressing power spikes
US9748765B2 (en) 2015-02-26 2017-08-29 Microsoft Technology Licensing, Llc Load allocation for multi-battery devices
US9793570B2 (en) 2015-12-04 2017-10-17 Microsoft Technology Licensing, Llc Shared electrode battery
US9939862B2 (en) 2015-11-13 2018-04-10 Microsoft Technology Licensing, Llc Latency-based energy storage device selection

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8300489B2 (en) * 2010-01-12 2012-10-30 International Business Machines Corporation Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603898A (en) * 1969-03-14 1971-09-07 Marconi Co Ltd N-parallel-path capacitive switched filter in which only incomplete spaced portions of input signal are sampled
US3654537A (en) * 1970-04-29 1972-04-04 Westinghouse Electric Corp High efficiency power supply for charging capacitors in steps
US3836906A (en) 1972-03-02 1974-09-17 Sony Corp Digital-to-analog converter circuit
US4082430A (en) * 1971-03-30 1978-04-04 Bbc Aktiengesellschaft Brown, Boveri & Company, Ltd. Driving circuit for a matrix-addressed liquid crystal display device
US4107757A (en) 1977-06-30 1978-08-15 Senichi Masuda Pulse power source
US4109192A (en) * 1976-06-25 1978-08-22 Hughes Aircraft Company Low power reactive drive circuit for capacitive loads
US4328525A (en) * 1980-06-27 1982-05-04 International Business Machines Corporation Pulsed sine wave oscillating circuit arrangement
US4594589A (en) * 1981-08-31 1986-06-10 Sharp Kabushiki Kaisha Method and circuit for driving electroluminescent display panels with a stepwise driving voltage
US4605999A (en) * 1985-03-11 1986-08-12 At&T Bell Laboratories Self-oscillating high frequency power converter
US4707692A (en) * 1984-11-30 1987-11-17 Hewlett-Packard Company Electroluminescent display drive system
US4802739A (en) * 1985-06-07 1989-02-07 Kabushiki Kaisha Toshiba Liquid crystal display control device
US4818981A (en) * 1986-09-11 1989-04-04 Fujitsu Limited Active matrix display device and method for driving the same
US4862113A (en) * 1988-01-06 1989-08-29 International Business Machines Corporation Sinusoidal oscillator with instant start-up
US4893117A (en) * 1986-07-18 1990-01-09 Stc Plc Liquid crystal driving systems
US4920474A (en) * 1989-03-23 1990-04-24 North American Philips Corporation High frequency high voltage power supply with controlled output power
US5095223A (en) * 1990-06-13 1992-03-10 U.S. Philips Corporation Dc/dc voltage multiplier with selective charge/discharge
US5339236A (en) * 1992-03-23 1994-08-16 Nec Corporation Charge pump circuit for intermediate voltage between power supply voltage and its double voltage
US5400028A (en) 1992-10-30 1995-03-21 International Business Machines Corporation Charge summing digital to analog converter

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3594627A (en) * 1969-10-20 1971-07-20 Teledyne Inc Capacitor discharge battery charger
US5293082A (en) 1988-06-21 1994-03-08 Western Digital Corporation Output driver for reducing transient noise in integrated circuits
JPH02135419A (en) 1988-11-17 1990-05-24 Seiko Epson Corp Method for driving liquid crystal display device
NL8901033A (en) 1989-04-25 1990-11-16 Philips Nv A control circuit for at least one clock electrode of an integrated circuit.
JPH0372783A (en) 1989-08-11 1991-03-27 Sony Corp Sine wave deflection circuit
DE3930259A1 (en) 1989-09-11 1991-03-21 Thomson Brandt Gmbh Drive circuit for a liquid-crystal display
US5105288A (en) 1989-10-18 1992-04-14 Matsushita Electronics Corporation Liquid crystal display apparatus with the application of black level signal for suppressing light leakage
US5126589A (en) 1990-08-31 1992-06-30 Siemens Pacesetter, Inc. Piezoelectric driver using resonant energy transfer
US5063340A (en) 1990-10-25 1991-11-05 Motorola, Inc. Capacitive power supply having charge equalization circuit
US5150013A (en) 1991-05-06 1992-09-22 Motorola, Inc. Power converter employing a multivibrator-inverter
JP2775040B2 (en) 1991-10-29 1998-07-09 株式会社 半導体エネルギー研究所 Electro-optical display device and a driving method
US5264752A (en) 1992-06-01 1993-11-23 At&T Bell Laboratories Amplifier for driving large capacitive loads
GB9226522D0 (en) 1992-12-19 1993-02-10 Harvey Geoffrey P Power saving electronic logic circuit
US5459414A (en) 1993-05-28 1995-10-17 At&T Corp. Adiabatic dynamic logic
JPH07128639A (en) 1993-11-04 1995-05-19 Sharp Corp Display device
DE4446330B4 (en) 1993-12-24 2007-07-19 Sharp K.K. Image display device
US5510748A (en) 1994-01-18 1996-04-23 Vivid Semiconductor, Inc. Integrated circuit having different power supplies for increased output voltage range while retaining small device geometries
US5572211A (en) 1994-01-18 1996-11-05 Vivid Semiconductor, Inc. Integrated circuit for driving liquid crystal display using multi-level D/A converter
US5465054A (en) 1994-04-08 1995-11-07 Vivid Semiconductor, Inc. High voltage CMOS logic using low voltage CMOS process
US5559463A (en) 1994-04-18 1996-09-24 Lucent Technologies Inc. Low power clock circuit
US5473526A (en) 1994-04-22 1995-12-05 University Of Southern California System and method for power-efficient charging and discharging of a capacitive load from a single source
CA2151850A1 (en) 1994-07-18 1996-01-19 Thaddeus John Gabara Hot-clock adiabatic gate using multiple clock signals with different phases
US5883538A (en) 1996-11-13 1999-03-16 Micron Technology, Inc. Low-to-high voltage CMOS driver circuit for driving capacitive loads
JP3705842B2 (en) 1994-08-04 2005-10-12 株式会社ルネサステクノロジ Semiconductor device
US5528256A (en) 1994-08-16 1996-06-18 Vivid Semiconductor, Inc. Power-saving circuit and method for driving liquid crystal display
US5694445A (en) 1994-09-22 1997-12-02 Matshushita Electric Industrial Co., Ltd. Semiconductor device with means for charge recycling
JP2815311B2 (en) 1994-09-28 1998-10-27 インターナショナル・ビジネス・マシーンズ・コーポレイション Driving device and method of a liquid crystal display device
JP2795191B2 (en) 1994-10-04 1998-09-10 株式会社デンソー Drive of the El display device
US5517145A (en) 1994-10-31 1996-05-14 International Business Machines Corporation CMOS toggle flip-flop using adiabatic switching
US5506520A (en) 1995-01-11 1996-04-09 International Business Machines Corporation Energy conserving clock pulse generating circuits
US5508639A (en) 1995-01-13 1996-04-16 Texas Instruments Incorporated CMOS clock drivers with inductive coupling
US5526319A (en) 1995-01-31 1996-06-11 International Business Machines Corporation Memory with adiabatically switched bit lines
WO1996026514A1 (en) 1995-02-23 1996-08-29 Philips Electronics N.V. Picture display device
JP3031195B2 (en) 1995-02-28 2000-04-10 株式会社日立製作所 Input and output buffer circuit device
US5521538A (en) 1995-03-30 1996-05-28 At&T Corp. Adiabatic logic
US5559478A (en) 1995-07-17 1996-09-24 University Of Southern California Highly efficient, complementary, resonant pulse generation
KR0154799B1 (en) 1995-09-29 1998-12-15 김광호 Thin film transistor liquid crystal display driving circuit with quick back voltage reduced
US5604454A (en) 1995-09-29 1997-02-18 Motorola Inc. Integrated circuit with low output buffer energy consumption and related method
US5602497A (en) 1995-12-20 1997-02-11 Thomas; Steven D. Precharged adiabatic pipelined logic
US5604449A (en) 1996-01-29 1997-02-18 Vivid Semiconductor, Inc. Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes
US5892540A (en) 1996-06-13 1999-04-06 Rockwell International Corporation Low noise amplifier for passive pixel CMOS imager
US5861861A (en) 1996-06-28 1999-01-19 Microchip Technology Incorporated Microcontroller chip with integrated LCD control module and switched capacitor driver circuit
DE19634084A1 (en) 1996-08-23 1998-02-26 Philips Patentverwaltung Phase-locked loop
US5754156A (en) 1996-09-19 1998-05-19 Vivid Semiconductor, Inc. LCD driver IC with pixel inversion operation
US5818252A (en) 1996-09-19 1998-10-06 Vivid Semiconductor, Inc. Reduced output test configuration for tape automated bonding
US5838203A (en) 1996-12-06 1998-11-17 Intel Corporation Method and apparatus for generating waveforms using adiabatic circuitry
US5841299A (en) 1997-02-06 1998-11-24 Intel Corporation Method and apparatus for implementing an adiabatic logic family
US5870331A (en) 1997-09-26 1999-02-09 Advanced Micro Devices, Inc. Application-specific SRAM memory cell for low voltage, high speed operation

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3603898A (en) * 1969-03-14 1971-09-07 Marconi Co Ltd N-parallel-path capacitive switched filter in which only incomplete spaced portions of input signal are sampled
US3654537A (en) * 1970-04-29 1972-04-04 Westinghouse Electric Corp High efficiency power supply for charging capacitors in steps
US4082430A (en) * 1971-03-30 1978-04-04 Bbc Aktiengesellschaft Brown, Boveri & Company, Ltd. Driving circuit for a matrix-addressed liquid crystal display device
US3836906A (en) 1972-03-02 1974-09-17 Sony Corp Digital-to-analog converter circuit
US4109192A (en) * 1976-06-25 1978-08-22 Hughes Aircraft Company Low power reactive drive circuit for capacitive loads
US4107757A (en) 1977-06-30 1978-08-15 Senichi Masuda Pulse power source
US4328525A (en) * 1980-06-27 1982-05-04 International Business Machines Corporation Pulsed sine wave oscillating circuit arrangement
US4594589A (en) * 1981-08-31 1986-06-10 Sharp Kabushiki Kaisha Method and circuit for driving electroluminescent display panels with a stepwise driving voltage
US4707692A (en) * 1984-11-30 1987-11-17 Hewlett-Packard Company Electroluminescent display drive system
US4605999A (en) * 1985-03-11 1986-08-12 At&T Bell Laboratories Self-oscillating high frequency power converter
US4802739A (en) * 1985-06-07 1989-02-07 Kabushiki Kaisha Toshiba Liquid crystal display control device
US4893117A (en) * 1986-07-18 1990-01-09 Stc Plc Liquid crystal driving systems
US4818981A (en) * 1986-09-11 1989-04-04 Fujitsu Limited Active matrix display device and method for driving the same
US4862113A (en) * 1988-01-06 1989-08-29 International Business Machines Corporation Sinusoidal oscillator with instant start-up
US4920474A (en) * 1989-03-23 1990-04-24 North American Philips Corporation High frequency high voltage power supply with controlled output power
US5095223A (en) * 1990-06-13 1992-03-10 U.S. Philips Corporation Dc/dc voltage multiplier with selective charge/discharge
US5339236A (en) * 1992-03-23 1994-08-16 Nec Corporation Charge pump circuit for intermediate voltage between power supply voltage and its double voltage
US5400028A (en) 1992-10-30 1995-03-21 International Business Machines Corporation Charge summing digital to analog converter

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070126289A1 (en) * 2005-12-07 2007-06-07 Chung-Fan Liu Electronic switching device with uninterruptible voltage regulating switch
US7414460B1 (en) 2006-03-31 2008-08-19 Integrated Device Technology, Inc. System and method for integrated circuit charge recycling
US20080012843A1 (en) * 2006-06-30 2008-01-17 Sony Corporation D/a converter circuit, liquid crystal driving circuit, and liquid crystal device
US8400382B2 (en) * 2006-06-30 2013-03-19 Sony Corporation D/A converter circuit, liquid crystal driving circuit, and liquid crystal device
US9285851B2 (en) 2012-06-22 2016-03-15 Microsoft Technology Licensing, Llc Optimizing battery use for known future load
US9696782B2 (en) 2015-02-09 2017-07-04 Microsoft Technology Licensing, Llc Battery parameter-based power management for suppressing power spikes
US9748765B2 (en) 2015-02-26 2017-08-29 Microsoft Technology Licensing, Llc Load allocation for multi-battery devices
US9939862B2 (en) 2015-11-13 2018-04-10 Microsoft Technology Licensing, Llc Latency-based energy storage device selection
US9793570B2 (en) 2015-12-04 2017-10-17 Microsoft Technology Licensing, Llc Shared electrode battery

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