USRE36490E - Power and signal line bussing method for memory devices - Google Patents

Power and signal line bussing method for memory devices Download PDF

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Publication number
USRE36490E
USRE36490E US08/886,107 US88610797A USRE36490E US RE36490 E USRE36490 E US RE36490E US 88610797 A US88610797 A US 88610797A US RE36490 E USRE36490 E US RE36490E
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Prior art keywords
memory cell
power
iaddend
iadd
cell array
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US08/886,107
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Sang Ki Hwang
Tae Sung Jung
Kyu Hyun Choi
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Definitions

  • the present invention relates to a power and signal line bussing method for high density and high speed memory devices.
  • Chip 1 has two memory cell arrays 2 centered around peripheral circuitry 4, which comprises multiple logic circuits.
  • Power line 3a supplies power from Vcc pad to peripheral circuitry 4.
  • Power line 3a runs from Vcc pad 5, around memory cell array 2, to peripheral circuitry 4.
  • Ground line 3b electrically connects peripheral circuitry 4 with GND pad 5'.
  • Ground line 3b runs from GND pad 5', around memory cell array 2, to peripheral circuitry 4.
  • Pad signal line 3' positioned around memory cell arrays 2, supplies signals from external pad 6 to peripheral circuit 4.
  • Circuit signal line 3" also positioned around memory cell array 2, supplies signals from internal circuit 6' to peripheral circuitry 4.
  • a final disadvantage of conventional bussing arrangement arises inherently from the design.
  • a passivation layer and an insulation layer are formed above the memory cell array.
  • a final package material layer is then formed on top of the passivation layer.
  • radiation generated from the package material layer penetrates the memory cells and causes a soft (or operation) error. To prevent this soft error, am additional shield layer formed on the memory cell array is desired.
  • An object of the present invention is to provide am efficient power and signal bussing arrangement for high speed and high density memory arrays.
  • Another object of the present invention is to reduce chip noise generated in high speed memory devices without increasing chip size.
  • Still another object of the present invention is to provide a fast access time by eliminating excess path distance.
  • Yet another object is to provide an additional insulative layer above memory cells to reduce soft error.
  • power, ground and signal lines are formed directly above the memory cell array.
  • the power and ground lines are parallel and positioned in an adjacent alternating pattern.
  • FIG. 1 is a top view of a power line bussing method according to the prior art
  • FIG. 2 is a top view of a signal line bussing method according to the prior art
  • FIG. 3 is a top view of a power line bussing method according to the present invention.
  • FIG. 4 is a top view of a signal line bussing method according to the present invention.
  • FIG. 3 shows a power line bussing arrangement according to the present invention.
  • Chip 11 comprises two memory cell arrays 12 centered around peripheral circuitry 14.
  • Power lines 13a formed above memory cell arrays 12 and peripheral circuitry 14, supplies power from Vcc pad 15 to peripheral circuitry 14.
  • Ground lines 13b formed above memory cell arrays 12 and peripheral circuitry 14, connects peripheral circuitry 14 to GND pad 15'.
  • Both power lines 13a and ground lines 13b are separated parallel lines traversing end-to-end chip 11. All power lines 13a are connected to Vcc pad 15 and all ground lines 13b are connected to GND pad 15'.
  • Ground lines 13b and power lines 13a are formed in an adjacent alternating pattern such that a power line 13a is positioned adjacent to ground line 13b, which is positioned adjacent another power line 13a, and so on.
  • Vcc power is supplied through Vcc pad 15 and power lines 13 to each circuit in the peripheral circuitry 14.
  • Vcc power is supplied through Vcc pad 15 and power lines 13 to each circuit in the peripheral circuitry 14.
  • Chip 11 further comprises external pad 16 and internal circuit 16'.
  • Pad signal line 13' formed above memory cells 12, couples external pad 16 to peripheral circuitry 14.
  • Circuit signal line 13 formed above memory cells 12, couples internal circuit 16' to peripheral circuitry 14.
  • the present invention Is advantageous to high speed memory devices. According to this bussing arrangement, signals carried by pad signal line 13' and circuit signal line 13" propagate directly to, and directly from, peripheral circuitry 14. Thus, propagation time is decreased, thereby improving chip speed.
  • the present invention is also advantageous for high density memory devices. Bussing the power, ground and signal lines directly across memory cell arrays, rather than around these arrays, reduces chip size by eliminating the area around the memory cell arrays.
  • power lines 13a, ground lines 13b, and signal lines 13', 13" above memory cell arrays 12 provides an additional shield layer between memory cell arrays 12 and the package material layer. Thus, soft error is reduced.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power and signal line bussing method for high density and high speed memory devices.
2. Description of the Prior Art
A conventional power line bussing method is shown in FIG. 1. Chip 1 has two memory cell arrays 2 centered around peripheral circuitry 4, which comprises multiple logic circuits. Power line 3a supplies power from Vcc pad to peripheral circuitry 4. Power line 3a runs from Vcc pad 5, around memory cell array 2, to peripheral circuitry 4. Ground line 3b electrically connects peripheral circuitry 4 with GND pad 5'. Ground line 3b runs from GND pad 5', around memory cell array 2, to peripheral circuitry 4.
However, employing a single power line 3a to couple power to peripheral circuitry 4 does not effectively reduce noise. To best reduce noise, a power line should be coupled independently to each circuit in peripheral circuitry 4. Yet, separating power line 3a further would increase the chip size because the area around memory cell arrays 2 would need to be engaged. Thus, the bussing arrangement according to the conventional bussing method is not conductive to noise reduction nor high density packing.
A conventional signal line bussing arrangement for chip 1 is shown In FIG. 2. Pad signal line 3', positioned around memory cell arrays 2, supplies signals from external pad 6 to peripheral circuit 4. Circuit signal line 3", also positioned around memory cell array 2, supplies signals from internal circuit 6' to peripheral circuitry 4.
However, signal line bussing according to this arrangement results in large signal delays because signals from pad 6 or internal circuit 6' must propagate the extra distance required to circumvent memory cell arrays 2.
A final disadvantage of conventional bussing arrangement arises inherently from the design. During conventional packaging processes, a passivation layer and an insulation layer are formed above the memory cell array. A final package material layer is then formed on top of the passivation layer. Yet, even with the passivation and insulation layers, radiation generated from the package material layer penetrates the memory cells and causes a soft (or operation) error. To prevent this soft error, am additional shield layer formed on the memory cell array is desired.
SUMMARY OF THE INVENTION
An object of the present invention is to provide am efficient power and signal bussing arrangement for high speed and high density memory arrays.
Another object of the present invention is to reduce chip noise generated in high speed memory devices without increasing chip size.
Still another object of the present invention is to provide a fast access time by eliminating excess path distance.
Yet another object is to provide an additional insulative layer above memory cells to reduce soft error.
To achieve these objects, power, ground and signal lines are formed directly above the memory cell array. The power and ground lines are parallel and positioned in an adjacent alternating pattern.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only and are not to limit the present invention wherein:
FIG. 1 is a top view of a power line bussing method according to the prior art;
FIG. 2 is a top view of a signal line bussing method according to the prior art;
FIG. 3 is a top view of a power line bussing method according to the present invention; and
FIG. 4 is a top view of a signal line bussing method according to the present invention.
DETAILED DESCRIPTION
FIG. 3 shows a power line bussing arrangement according to the present invention. Chip 11 comprises two memory cell arrays 12 centered around peripheral circuitry 14. Power lines 13a, formed above memory cell arrays 12 and peripheral circuitry 14, supplies power from Vcc pad 15 to peripheral circuitry 14. Ground lines 13b, formed above memory cell arrays 12 and peripheral circuitry 14, connects peripheral circuitry 14 to GND pad 15'. Both power lines 13a and ground lines 13b are separated parallel lines traversing end-to-end chip 11. All power lines 13a are connected to Vcc pad 15 and all ground lines 13b are connected to GND pad 15'. Ground lines 13b and power lines 13a are formed in an adjacent alternating pattern such that a power line 13a is positioned adjacent to ground line 13b, which is positioned adjacent another power line 13a, and so on.
Accordingly, Vcc power is supplied through Vcc pad 15 and power lines 13 to each circuit in the peripheral circuitry 14. By coupling a power line independently to each circuit in peripheral circuitry 14, noise generated by these circuits is minimized.
Chip 11 further comprises external pad 16 and internal circuit 16'. Pad signal line 13', formed above memory cells 12, couples external pad 16 to peripheral circuitry 14. Circuit signal line 13", formed above memory cells 12, couples internal circuit 16' to peripheral circuitry 14.
The present invention Is advantageous to high speed memory devices. According to this bussing arrangement, signals carried by pad signal line 13' and circuit signal line 13" propagate directly to, and directly from, peripheral circuitry 14. Thus, propagation time is decreased, thereby improving chip speed.
The present invention is also advantageous for high density memory devices. Bussing the power, ground and signal lines directly across memory cell arrays, rather than around these arrays, reduces chip size by eliminating the area around the memory cell arrays.
Further, forming power lines 13a, ground lines 13b, and signal lines 13', 13" above memory cell arrays 12 provides an additional shield layer between memory cell arrays 12 and the package material layer. Thus, soft error is reduced.

Claims (4)

What is claimed is:
1. A memory device formed on a semiconductor substrate having .Iadd.peripheral .Iaddend.circuitry positioned adjacent a single memory cell array, said memory device comprising:
a plurality of power lines formed above said single memory cell array for supplying power to said .Iadd.peripheral .Iaddend.circuitry, each power line being substantially parallel to and spaced apart from every other power line; and
a plurality of ground lines formed above said single memory cell array for supplying ground potential to said .Iadd.peripheral .Iaddend.circuitry, each ground line being substantially parallel to and spaced apart from every other ground line.
2. A memory device according to claim 1, further comprising at least one signal line formed directly above said single memory cell array to carry signals to said .Iadd.peripheral .Iaddend.circuitry.
3. A method of forming power and signal lines on a memory device, said memory device being formed on a semiconductor substrate and having a single memory cell array .Iadd.and peripheral circuitry adjacent said memory cell array.Iaddend., comprising the steps of:
forming a plurality of substantially parallel power lines above said single memory cell array .Iadd.for supplying power to said peripheral circuitry.Iaddend.;
forming a plurality of substantially parallel ground lines above said single memory cell array .Iadd.for supplying ground potential to said peripheral circuitry.Iaddend.; and
forming a plurality of signal lines above said single memory cell array .Iadd.for supplying signals to said peripheral circuitry.Iaddend.. .Iadd.4. A memory device according to claim 1, wherein the plurality of parallel power lines and the plurality of parallel ground lines are positioned in an adjacent alternating pattern. .Iaddend..Iadd.5. A method of forming according to claim 3, wherein said forming steps for the plurality of parallel power lines and the plurality of parallel ground lines result in the power and ground lines being positioned in an adjacent
alternating pattern. .Iaddend..Iadd.6. A memory device according to claim 1, wherein the plurality of power lines and the plurality of ground lines form a shield layer above the memory cell array and below a package material layer to reduce soft errors. .Iaddend..Iadd.7. A memory device according to claim 2, wherein said at least one or more of the signal lines form a shield layer above the memory cell array and below a package material layer to reduce soft errors. .Iaddend..Iadd.8. A method of forming according to claim 3, further comprising a step of forming a shield layer above the memory cell and below a package material layer to reduce soft errors, said shield layer being composed of said power, ground and signal lines. .Iaddend.
US08/886,107 1988-07-21 1997-06-30 Power and signal line bussing method for memory devices Expired - Lifetime USRE36490E (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/886,107 USRE36490E (en) 1988-07-21 1997-06-30 Power and signal line bussing method for memory devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR88-9162 1988-07-21
KR1019880009162A KR910008099B1 (en) 1988-07-21 1988-07-21 Power chip and signal line busing method of memory chip
US07/330,917 US5007025A (en) 1988-07-21 1989-03-31 Power and signal line bussing method for memory devices
US08/886,107 USRE36490E (en) 1988-07-21 1997-06-30 Power and signal line bussing method for memory devices

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US07/330,917 Reissue US5007025A (en) 1988-07-21 1989-03-31 Power and signal line bussing method for memory devices

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US08/886,107 Expired - Lifetime USRE36490E (en) 1988-07-21 1997-06-30 Power and signal line bussing method for memory devices

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040042252A1 (en) * 2002-08-30 2004-03-04 Kang Hee Bok FeRAM having new signal line structure

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184321A (en) * 1988-12-06 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement
JPH0772991B2 (en) * 1988-12-06 1995-08-02 三菱電機株式会社 Semiconductor memory device
US6069814A (en) * 1989-05-26 2000-05-30 Texas Instruments Incorporated Multiple input buffers for address bits
US5195053A (en) * 1989-08-30 1993-03-16 Nec Corporation Semiconductor memory device wired to accommodate increased capacity without increasing the size of the semiconductor memory device
JPH07114259B2 (en) * 1989-10-19 1995-12-06 株式会社東芝 Semiconductor memory device
US5313432A (en) * 1990-05-23 1994-05-17 Texas Instruments Incorporated Segmented, multiple-decoder memory array and method for programming a memory array
JP2894635B2 (en) * 1990-11-30 1999-05-24 株式会社東芝 Semiconductor storage device
JP2645183B2 (en) * 1991-02-04 1997-08-25 株式会社東芝 Semiconductor integrated circuit device
JP3082323B2 (en) * 1991-07-30 2000-08-28 ソニー株式会社 Memory module
JP3280704B2 (en) * 1992-05-29 2002-05-13 株式会社東芝 Semiconductor storage device
JP3195828B2 (en) * 1992-08-31 2001-08-06 三菱電機株式会社 Semiconductor device
US5325336A (en) * 1992-09-10 1994-06-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having power line arranged in a meshed shape
JPH06140607A (en) * 1992-10-28 1994-05-20 Mitsubishi Electric Corp Semiconductor integrated circuit
KR970005691B1 (en) * 1993-09-06 1997-04-18 삼성전자주식회사 Semiconductor device having power line structure for power noise reduction
JP3354231B2 (en) * 1993-09-29 2002-12-09 三菱電機エンジニアリング株式会社 Semiconductor device
KR100258345B1 (en) * 1996-11-28 2000-06-01 윤종용 Semiconductor memory device having improved power line architecture
EP1113368A3 (en) * 1999-12-27 2001-09-26 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit with cache
US20060077002A1 (en) * 2004-10-08 2006-04-13 White Richard T Apparatus and methods for saving power and reducing noise in integrated circuits
JP2008227171A (en) * 2007-03-13 2008-09-25 Toshiba Corp Nonvolatile semiconductor memory
US10784199B2 (en) * 2019-02-20 2020-09-22 Micron Technology, Inc. Component inter-digitated VIAS and leads

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4426689A (en) * 1979-03-12 1984-01-17 International Business Machines Corporation Vertical semiconductor integrated circuit chip packaging
US4439841A (en) * 1980-06-10 1984-03-27 Fujitsu Limited Semiconductor memory devices
JPS63100769A (en) * 1986-10-17 1988-05-02 Hitachi Ltd Semiconductor memory device
US4791609A (en) * 1986-04-09 1988-12-13 Nec Corporation Semiconductor integrated circuit device
US4811288A (en) * 1985-09-25 1989-03-07 Ncr Corporation Data security device for protecting stored data
US4849943A (en) * 1986-08-27 1989-07-18 U.S. Philips Corp. Integrated memory circuit having a block selection circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4426689A (en) * 1979-03-12 1984-01-17 International Business Machines Corporation Vertical semiconductor integrated circuit chip packaging
US4439841A (en) * 1980-06-10 1984-03-27 Fujitsu Limited Semiconductor memory devices
US4811288A (en) * 1985-09-25 1989-03-07 Ncr Corporation Data security device for protecting stored data
US4791609A (en) * 1986-04-09 1988-12-13 Nec Corporation Semiconductor integrated circuit device
US4849943A (en) * 1986-08-27 1989-07-18 U.S. Philips Corp. Integrated memory circuit having a block selection circuit
JPS63100769A (en) * 1986-10-17 1988-05-02 Hitachi Ltd Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040042252A1 (en) * 2002-08-30 2004-03-04 Kang Hee Bok FeRAM having new signal line structure
US7050321B2 (en) * 2002-08-30 2006-05-23 Hynix Semiconductor Inc. FeRAM having new signal line structure

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Publication number Publication date
KR910008099B1 (en) 1991-10-07
US5007025A (en) 1991-04-09
JPH0247866A (en) 1990-02-16
JPH0810752B2 (en) 1996-01-31
KR900002317A (en) 1990-02-28

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