USRE35119E - Textured metallic compression bonding - Google Patents

Textured metallic compression bonding Download PDF

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USRE35119E
USRE35119E US07820730 US82073092A USRE35119E US RE35119 E USRE35119 E US RE35119E US 07820730 US07820730 US 07820730 US 82073092 A US82073092 A US 82073092A US RE35119 E USRE35119 E US RE35119E
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chip
pads
carrier
gold
pad
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Greg E. Blonder
Theodore A. Fulton
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AT&T Corp
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AT&T Corp
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Abstract

Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon career, and depositing the gold on the silicon dioxide layer.

Description

.Iadd.This application is a Reissue of Ser. No. 07/222,465 filed Jul. 21, 1988, U.S. Pat. No. 4,937,653. .Iaddend.

TECHNICAL FIELD

This invention relates to semiconductor integrated circuits and more particularly to schemes for interconnecting one semiconductor integrated circuit (IC) chip to another on a chip-carrier.

BACKGROUND OF THE INVENTION

An IC chip of semiconductor silicon in present-day an can contain as many as several hundred thousand or even a million transistors. Electrical access to these transistors from one or more other silicon chips is limited by the number of input/output (I/O) ports, typically in the form of metallic pads, that can be fitted on the chip and be reliably electrically connected via metallic interconnection wiring to other chips. This limit on the number of I/O ports per chip undesirably limits the circuit design versatility of an IC chip and undesirably proliferates the number of chips required in IC technology for implementing a given electrical circuit.

One of the difficulties associated with any scheme for establishing chip-to-chip interconnections is that these interconnections must be accomplished with finished chips--i.e., chips having their integrated circuitry completed--so that by the time they are ready for chip-to-chip interconnections, the chips cannot withstand temperatures much above 300° C. or so without damaging their integrated circuitry.

In a paper entitled "Wafer-Chip Assembly for Large-Scale Integration" by P. Kraynak et al published in IEEE Transactions on Electron Devices, vol. ED-15 (1968), pp. 660-663, a chip-to-chip interconnection scheme is described in which the circuit face of each chip has a plurality of smooth metallic I/O pads, typically made of gold or aluminum. Each chip is oriented circuit-face-downward so that each of these pads (hereinafter "chip pads") is located in registry with a corresponding one of a plurality of smooth metallic pads located on a top surface of a flat silicon wafer serving as a chip-carrier (hereinafter "carrier"). The top surface of the carrier is coated with an insulating layer upon which a pattern of interconnection wiring, typically of aluminum, is deposited in accordance with a desired chip-to-chip electrical interconnection pattern. The pads on the top surface of the carrier (hereinafter "carrier pads") typically are simply formed by those portions of this chip-to-chip electrical interconnection wiring on the carrier which directly underlie (in registry with) the chip pads. Relatively low resistance contact-bonding between each carrier pad and its corresponding (in registry) chip pad is achieved by forming a metallic bump or glob of suitable metal--such as gold or solder--on each carrier pad or on each chip pad, or on both, followed by bonding each carrier pad to its corresponding chip pad by means of an ultrasonic, thermo-compression, or solder-reflow bonding technique. The area of the top surface of the carrier is advantageously considerably larger than the area of a single chip. Thus more than one such chip can similarly be bonded onto a single carrier. The carrier, together with its interconnection wiring, thus serves as a chip-to-chip electrical interconnection means for the chips, as well as a thermal sink and a mechanical support member for each chip.

A problem that arises in the prior an is that the surface of the chip in general is bowed (curved) and hence not sufficiently flat to enable all metallic globs to come in contact with and be bonded to the corresponding carrier pads unless such high compressive forces be applied as to risk breaking the chip.

SUMMARY OF THE INVENTION

The foregoing problem associated with semiconductor IC chip-to-chip interconnection is mitigated in accordance with the invention by using chip pads directly bonded to carrier pads whose surfaces are rough or textured with feature sizes of the order (i.e., to within a factor of 10) of 1 micrometer, preferably feature sizes of about 1 or 2 micrometer or less. That is, for example, the textured surfaces of the carder pads have indentations or grooves or protrusions whose depths or heights, preferably as well as their widths (measured at the top of the grooves), are about 1 micrometer or less. By the term "directly bonded" is meant bonded without interposition of any material between the carrier and chip pads that are thus bonded together. The nonzero depth of the texturing alleviates the problem arising from non-flatness of the surface of the chip.

For the purpose of ease of manufacture, typically the surfaces of only the carrier pads are textured; nevertheless, the invention also includes the case in which the chip pads are textured instead of, or in addition to, the carrier pads. Thus this invention involves:

(a) a semiconductor integrated circuit chip having an integrated circuit connected to a plurality of metallic chip pads located on a major surface of the chip;

(b) a carrier upon which are located metallic interconnections having metallic carrier pads that are bonded to the chip pads, each of the carder pads, chip pads, or both having at least a portion thereof that is textured with a feature size of the order of a micrometer, preferably about one or two micrometer or less.

Both the chip pads and the carrier pads typically are made of, or are coated with, gold, so that the bonding is gold-to-gold. In preparation for and during the bonding of the carder pads to the chip pads, no external heat need be applied, so that the bonding process herein comprises that which is known in the welding art as cold-welding or cold-weld bonding, i.e., welding or bonding by means of compression at room temperature. The internal heat generated by the cold-welding typically causes a temperature rise of the chip circuitry which is insignificant. On the other hand, it should be understood that heating the carrier or chip pads to a temperature of about 300° C. or less before, during, or after welding in accordance with this invention is not precluded. Moreover, the surfaces of all carrier and pads can be pre-cleaned by exposure to short wavelength ultraviolet radiation that generates ozone; and this exposure can be performed in a vacuum chamber. followed by compression bonding in this same chamber.

If it is desired to increase the mechanical compliance of the resulting structure in response to mechanically or thermally induced stress, then in accordance with another embodiment of the invention a portion of each chip pad is separated from the bottom surface of the chip by a localized layer of an insulating material (FIG. 6) having a thickness approximately the same as that of the chip pad, and only the portion of the surface of each carrier pad underlying the layer of insulating material need be textured while the remaining portion underlying the chip pad is indented in the vertical direction and is made to be smooth. The insulating material is selected so as to have relatively little or no adhesive tendency with respect to the chip pad.

It is believed that the ability to form, by means of compression at room temperature, a sufficiently strong gold-to-gold bond between chip pad and corresponding carrier pad is attributable to a penetration through the very thin layer (about 1 nanometer) of foreign matter ordinarily coating the surfaces of the gold, by virtue of the forced sliding, squeezing and scraping of the bottom of chip pad along the sloping sides of the texturing, such as V-grooves, of the respective underlying carder pad (FIG. 3), whereby fresh clean surfaces of chip pad and carrier pad are exposed to each other for mutual physical contact. At the same time, variations of distance between chip and carrier pads can be tolerated, within limits of course, became of the extrusion of more gold from the areas of contact between the originally more closely proximate pain of chip and carrier pads, whereby the less closely proximate pairs can also make contact. However, it should be understood that the actual success of the invention does not depend upon the correctness of the foregoing theory.

BRIEF DESCRIPTION OF THE DRAWINGS

This invention together with its features and advantages may be better understood from the following detailed description when read in conjunction with the drawings in which

FIG. 1 is a side view in cross section of a semiconductor integrated circuit chip-to-chip interconnection scheme in accordance with a specific embodiment of the invention;

FIG. 2 is a somewhat enlarged side view in cross section of a portion of the scheme shown in FIG. 1 just prior to assembly by bonding;

FIG. 3 is a somewhat more enlarged side view of a portion of the scheme shown in FIG. 1;

FIG. 4 is a side view in cross section of a semiconductor integrated circuit chip-to-chip interconnection scheme just before assembly, in accordance with another specific embodiment of the invention;

FIG. 5 is top view of a position of a textured chip-carder in accordance with yet another specific embodiment of the invention;

FIG. 6 is a somewhat enlarged sideview in cross section of a portion of FIG. 1 just prior to assembly by bonding, according to another specific embodiment of the invention;

FIG. 7 is a sideview in cross section of the same portion as FIG. 6 just after assembly; and

FIG. 8 is a sideview in cross section of a semiconductor integrated circuit chip-to-chip interconnection scheme in accordance with yet another specific embodiment of the invention.

Only for the sake of clarity, none of the drawings is to scale.

DETAILED DESCRIPTION

As shown in FIG. 1, a pair of semiconductor IC chips 101 and 102 are mounted circuit-face-down on a silicon wafer carrier 10. For the purpose of electrical insulation. the top surface of this carrier 10 is coated everywhere with a relatively thin layer 15 (FIG. 3) of silicon dioxide, typically about 0.1 micrometers in thickness. Each of the chips 101 and 102 has an illustrative metallized interconnect line 23 and 33, respectively, to be interconnected to each other. This interconnection is accomplished by means of illustrative chip pads 24 and 34, bonded to carrier pads 12 and 14, respectively, in combination with chip-to-chip interconnection wiring 13 located on the top surface of the carrier 10.

Each of the chip pads 24 and 34, or at least a bottom portion of each of these pads, advantageously is made of gold, preferably formed by sputter deposition through undercut apertures in a photoresist mask. Likewise a top portion of each of the carrier pads 12 and 14 is made of gold, for gold-to-gold welding of chip pads to carrier pads.

The chip pads 24 and 34 are formed so as to make contact with portions of the corresponding interconnect lines 23 and 33, respectively, as known in the art. Each of the carrier pads 12 and 14 is the corresponding respective textured portion of the wiring 13 underlying the chip pads 24 and 34, respectively. The top surface of each of the carrier pads 12 and 14, as well as the portions of the top surface of the carrier 10 itself at areas underlying these pads, is textured as explained more fully below. It should be understood that typically more than just the two chips 101 and 102 are mounted on the carrier 10 and that typically each of the chips contain hundreds if not thousands of lines to be interconnected with lines of other chips, whereas FIG. 1 shows only one illustrative example out of many such chip-to-chip interconnections and only two of such chips out of many possible chips that are interconnected via wiring on the career 10.

As shown in FIG. 2, which is an enlarged view of a portion of FIG. 1 just prior to assembly of the chip 101 to the silicon carrier 10, the top surface of the silicon carrier 10 at areas underlying the pads is patterned, "roughened", or "textured" with rather closely packed V-shaped grooves. For example, each of the grooves measures about 1 by 1 micrometer square across the top, and the distance between centers of nearest neighboring grooves is about 3 micrometers or less. These grooves are fabricated by known photolithographic masking and anisotropic wet chemical etching techniques for silicon, such as the wet etch KOH on the (100) crystal plane of silicon whereby each of the sides of the resulting V-grooves is parallel to the (111) or to the .[.(1 11).]. (.Iadd.1 11) .Iaddend.crystal plane. Subsequently the silicon dioxide layer 15 (FIG. 3) is thermally grown upon the top surface of the silicon wafer including upon the V-grooves.

Assembly of each chip onto the carrier--i.e., compression bonding of chip pads to carrier pads--is accomplished by cleaning and aligning the chip pads with the respective corresponding carrier pads and applying a mechanical pressure (compression) of about 20 to 40 kg-force/mm2 of pad area to the chip and carrier at room temperature (with no applied heat) for a time interval of about 5 seconds, in order to press the bottom surfaces all chip pads in the chip simultaneously against the top surfaces of the respective carrier pads. Because the alignment is done at room temperature, it is ordinarily sufficient to align but two mutually diagonally situated pads, whereby all the other pads are automatically aligned. To clean the chips, before bonding them to the carrier, in particular, to clean them of photoresist, standard techniques are employed.

The resulting bonding of chip pads to carrier pads can be made stronger by applying ultrasonic waves to the pads during the compression bonding or by heating the pads with a laser beam focused on each pad after bonding. A carbon dioxide laser, which has a wavelength of about 10 micrometers (to which the silicon carrier is transparent), is useful for this purpose.

In the absence of the laser heating or the ultrasonic waves, the bonding of chips to carrier is reversible, in that one or more selected chips can be separately detached intact and removed from the carrier without damaging it simply by a mechanical pulling apart. This removability may be very advantageous in case one or more of the chips cease to function properly, in which case the improperly functioning chip(s) can be detached from the carrier simply by pulling apart such chip(s) from the carrier with an applied tensile stress of about 1 kg-force/mm2 of total pad area or more without damaging the carrier, and replacing the thus detached chip(s) with properly functioning chip(s), again by means of cold-welded compression bonding of chip and carrier pads. Alternatively, some or all functioning chips bonded to a given carrier can be detached therefrom by pulling and then bonded to another carrier having a different wiring pattern, in order to use some or all of the same chips in a different chip-to-chip electrical interconnection configuration.

As shown in FIG. 3, an enlarged portion of FIG. 2 after assembly of chip to carrier by means of the mechanical pressure described above, as the chip 101 is pressed against the carrier 10, the gold of the pad 24 is squeezed and rubs along sloping portions of the V-shaped grooves (hereinafter "V-grooves"), thereby exposing fresh gold surfaces of both the chip pad and the carder pad, so that the result is a mechanically reliable cold-welded joining room-temperature bonding of chip pads to carrier pads.

As shown in FIG. 4, bottom gold surfaces of the chip pads can be textured with a feature size of about 1 micrometer, instead of (or in addition to) texturing the top surface of the carrier pads. Such texturing of the gold surfaces of the chip pads can be accomplished by photolithographic masking and etching of the gold or by electroplating gold on nickel--a process that automatically results in a textured gold surface.

The V-grooves as viewed from the top can also take the form of nested L's instead of squares, as shown in FIG. 5, where each L-shaped groove 44 has sides that slope downward to the bottom 45 of the groove. The width of the two elongated mask openings defining each L-shaped groove is typically about 1 micrometer, and the space between nearest adjacent L's is typically about 2 micrometers, whereby the L's are on about 3 micrometer centers.

More specifically, in the FIG. 1 embodiment, each of the interconnect lines 23 and 33 is typically made of a single layer of aluminum having a thickness of about one-half to one micrometer and a width of about two micrometers or less, or it can be made in the form of a layered structure of aluminum-titanium-platinum-gold or aluminum-titanium-platinum-gold-tin-gold likewise having a total thickness of about 0.10 micrometers, and a width of about one micrometer or less, with the titanium having a thickness of about 0.05 micrometers. The thickness of each of the chip pads 24 and 34 is typically about 3 micrometers of gold or more, and its width dimensions are typically about 10 by 10 micrometers square. It should be understood, of course, that the chip (and hence carrier) pad shapes as viewed from a vertical direction can be arbitrary: squares, rectangles, circles, etc. The metallization of each carrier pad is typically a gold layer having a thickness of about 0.3 micrometers on a layer of titanium having a thickness of about 0.05 micrometers, the titanium ensuring adhesion of the gold to the underlying silicon dioxide layer 15. The wiring 13 on the carrier 10 is typically made of the same material and thickness as those of the interconnect lines 23 and 33, but everywhere (including the regions of the carrier pads 12 and 14) the wiring 13 has a width of about 10 micrometers or slightly more, i.e., substantially the same width as that of the chips pads except for perhaps an added, relatively small safety margin in the width of the carrier pad.

The space between nearest adjacent chip pads is about 10 micrometers. The distance between centers of nearest neighboring chip pads thus is as little as about 20 micrometers or less. In this way a chip having a size of 1 cm by 1 cm--a periphery of 4 cm--can have as many as 2000 pads or more, i.e., one pad deep along the entire periphery of the chip, and can have many more pads if pads are also built at interior portions of the chip in addition to the periphery thereof. Pads thus located at interior portions have advantages in that thermal conductance and hence heat-sinking of the chip to the carrier is improved in magnitude and in uniformity, and in that the parasitics associated with long conductive paths on the chip from interior to periphery can be reduced. Moreover, in view of the relatively large number of pads, either non-electrically-functional ("dummy") pads or electrically functional redundant pads can be used for increased strength of attachment, increased electrical reliability, and improved heat-sinking.

It should be understood that the interconnection wiring on the carrier at portions thereof underlying the chips but removed from the pads, as well as between chips, can be fabricated with gold or other metals--such as aluminum. The wiring on the carrier can be fabricated on one or more planes ("metallization levels") that are insulated from one another by insulating layers, for example, of silicon dioxide or phosphorous doped glass, as known in the art. Accordingly, any desired wiring pattern including cross-overs can be fabricated on the carrier as known in the art.

Backside contact (not shown) of the chip to the carrier can be made by means of a fine gold wire which is bonded, after assembly of chip carrier, by means of silver-epoxy both to the backside of the chip and to a matching, typically smooth pad on the carrier.

Another specific embodiment is illustrated in FIGS. 6 and 7, in which the same reference numerals are used for elements corresponding to those shown in FIGS. 1-3. In this embodiment (FIGS. 6 and 7) an insulating spacing layer 25 separates the bottom surface of the chip 101 from a left-hand moiety of the chip pad 24. Typically, this layer 25 is hard baked photoresist or silicon nitride 3 micrometers thick, to which adherence of the gold of the chip pad is minimal or zero. A portion 30 of the top surface of the silicon carrier 10 underlying the right-hand moiety of the spacing layer 25 is smooth and is vertically indented ("sunken") beneath the original top surface of the silicon to a depth corresponding to the bottom of the V-grooves. Vertical indenting of the portion 30 can be obtained by photolithographic masking and etching at the same time as the photolithographic masking and etching of the V-grooves.

Starting with the situation shown in FIG. 6, mechanical compression is applied followed by a slight mechanical pulling which is sufficient to produce a vertical spacing y (FIG. 7) between the top left-hand surface of the chip pad 24 and the bottom left-hand surface of the spacing layer 25, and which is sufficient to produce vertical spacing between the chip pad 24 and the sunken surface portion 30. Typically, this spacing y is about 2 micrometers. Prior to electrical utilization of the circuitry of the chip 101, the layer 25 can be removed as by an oxygen plasma treatment of the photoresist material (but not if silicon nitride) thereof, in order to have greater compliance--i.e., greater leeway or margins in case of change in bowing of the bottom surface of the chip. This structure (FIG. 7) has the added advantage of relative freedom from strains induced by unequal thermal expansion of the chip 101 and the carrier 10 in the lateral direction due to unequal temperature changes. Hence this structure promises to withstand such strains, in case they indeed occur during operation, as might cause failures of the embodiment shown in FIGS. 1-3. For greater mechanical strength, nickel plated with gold can be used as the material for chip pad 24.

FIG. 8 shows another embodiment, wherein some or all chip-to-chip interconnection is obtained through a separate chip-to-chip interconnection wiring plate 201. The plate 201 is attached to the carrier 10 by means of the interconnection plate pads 64 and 74 and typically many others (not shown) which are bonded to career pads 44 and 54 and typically many others (not shown). The bonding is achieved in the same way that, for example, the chip 101 is attached to the carrier 10 by means of chip pad 24 bonded to carrier pad 14. In this way the interconnection wiring portions 13 stemming from chips 101 and 102 are interconnected--and hence pads 24 and 34 are interconnected--through pads 64 and 174 of the interconnection plate 201 plus interconnect lines 63, 73, and perhaps others (not shown) of the plate 201.

The interconnection plate 201 can simply take the form of an IC chip having no transistors, but having only wiring (typically multi-level) arranged for electrically interconnecting the various interconnection plate pads. Each of the plate pads is constructed in the same way as an IC chip pad. Moreover, chip-to-chip electrical interconnection may be modified by mechanically pulling and removing the plate 201 and replacing it with another plate having a different pattern of interconnect lines. Also, failures in the chip-to-chip interconnection plate can be repaired by similarly removing the failed interconnection plate followed by replacement of another operative plate.

Although the invention has been described in detail with reference to specific embodiments, various modifications can be made without departing from the scope of the invention. For example, etch pits other than V-grooves in silicon can be used for texturing the surface of the carrier pads. In silicon, for example etch pits with crystallographic (111) sides on (110) oriented silicon wafer surfaces could be fabricated having vertical sidewalls rather than V-grooves. Instead of such etch pits or V-grooves which are L-shaped or are square shaped as viewed from the top, other shapes such as elongated trench V-grooves can be etched into the silicon carrier by using correspondingly shaped masking for the etching. The surface of the gold itself of the carrier pads could be directly textured (without first texturing the underlying silicon) by means of photolithographically etching the top surface of the gold carrier pads rather than the underlying silicon, or by electroplating the gold on nickel. Moreover, gold-plated nickel has mechanically stronger greater breaking strength than pure gold. This greater breaking strength is especially desirable in the embodiment of FIGS. 6-7 where, in response to the mechanical pulling, before the bonded portion can detach as is desired, there is an undesirable tendency for the central portion of the chip pad to tear or break and thus prevent re-use of chip on another carrier. Instead of grooves, texturing of a surface can be obtained by forming a multitude of pillars (columns), pyramids, or other protrusions on the surface.

Also, texturing of a surface can be accompanied anisotropically etching the entire surface to a prescribed depth except for the top of grooves which are masked against the etching. Alternatively, texturing can be achieved by selectively depositing metal only in the regions of the pads, followed by formation of grooves in the deposited metal layer. A single chip can be attached to the carrier, instead of more than one chip, simply for the purpose of mechanically and electrically stable external access.

Instead of silicon, other materials for the carrier may be used, such as glass or ceramic; and the chips themselves can be crystalline gallium arsenide instead of silicon.

Moreover the welding procedure of this invention could be done at temperature above or below room temperature--the former (but not above about 300° C.) for the purpose of stronger bonding, if desired, the latter for protecting the integrated circuitry by maintaining the temperature fairly low even in the presence of undesirable mounts of heat (if any) generated by the sliding of the chip pad surfaces along the textured carrier pad surfaces. The welding could also be done in an environment comprising a selected gas or liquid (such as for fluxing).

Finally the welding could be performed by the step of precleaning the surfaces of all pads by exposure to short ultraviolet light that generates ozone, i.e., light of wavelength equal to about 250 nanometers, followed by the step of compression bonding (cold-welding), with either or both steps being performed in a vacuum chamber.

Claims (14)

We claim:
1. In combination
(a) a semiconductor integrated circuit chip having an integrated circuit connected to a plurality of metallic chip pads located on a major surface of the chip;
(b) a carrier upon which are located metallic wiring interconnections having metallic carrier pads that are .Iadd.compression .Iaddend.bonded to the chip pads, each of .Iadd.either .Iaddend.the carrier pads.[.,.]. .Iadd.or the .Iaddend.chip pads, .[.or.]. .Iadd.but not .Iaddend.both.Iadd., .Iaddend.having at least a portion thereof that is textured .Iadd.prior to bonding .Iaddend.with indentations whose depths are.[., or protrusions whose heights are,.]. of the order of one micrometer.
2. The combination described in claim 1 in which each chip pad has a portion that is separated from the major surface of the chip by a portion of a localized layer of an insulating material, and in which each carder pad has a portion, underlying a complementary portion of the layer of insulating material, that is indented in the vertical direction and is smooth, the insulating material having relatively little or no adhesive tendency with respect to the chip pad.
3. The combination of claim 2 in which the carrier comprises a silicon wafer and in which the pads are bonded such that a tensile force of about 1 kg per mm2 or more of pad area is required to pull them apart.
4. The combination of claim 3 in which the silicon wafer has a plurality of V-grooves at each of such portions thereof underlying the carrier pads.
5. The combination of claim 2 in which surfaces of the chip pads are essentially gold.
6. The combination of claim 5 in which surfaces of the carrier pads are essentially gold and in which the chip pads are nondestructively detachable from the carrier pads by means of a mechanical pulling apart.
7. The combination of claim 1 in which the chip carrier comprises a silicon wafer which is textured at the portions thereof .[.underlying.]. .Iadd.bonded to .Iaddend.the carrier pads.
8. The combination of claim 7 in which the silicon wafer has a plurality of V-grooves at each of such portions thereof .[.underlying.]. .Iadd.bonded to .Iaddend.the carrier pads.
9. The combination of claim 1 in which areas of the carrier pads to be bonded to chip pads are essentially gold and in which the chip pads are nondestructively detachable from the carrier pads by means of a mechanical pulling apart.
10. The combination of claim .[.10.]. .Iadd.9 .Iaddend.in which the surfaces of the chip pads are essentially .[.gold.]. .Iadd.gold.Iaddend..
11. The combination of claim 1 in which surfaces of the chip pads are essentially gold.
12. The combination of claim 1 in which the indentations .[.or protrusions.]. have widths, as measured at the tops .[.of the protrusions.]. or bottoms of the indentations, of about 1 micrometer or less. .Iadd.13. In combination:
a first body having a first metallic layer located contiguous with a first surface of the first body; and
a second body having a second metallic layer being compression bonded to the second metallic layer, either the first metallic layer or the second metallic layer, but not both the first and second metallic layers, having at least a portion thereof that is textured prior to bonding with indentations whose depths are of the order of one micrometer or less. .Iaddend. .Iadd.14. The combination of claim 13 in which the second body comprises a wafer and in which the first and second metallic layers are bonded such that a tensile force of about 1 kg per mm2 or more of metallic area is required to pull them apart. .Iaddend. .Iadd.15. The combination of claim 13 in which a surface of the first metallic layer is essentially gold. .Iaddend. .Iadd.16. The combination of claim 15 in which a surface of the second metallic layer is essentially gold and in which the first metallic layer is nondestructively detachable from the second metallic layer by means of a mechanical pulling apart. .Iaddend. .Iadd.17. The combination of claim 13 in which the second body comprises a wafer which is textured at the portion thereof bonded to the second metallic layer. .Iaddend. .Iadd.18. The combination of 17 in which the wafer has a plurality of V-grooves at the portion thereof bonded to the second metallic layer. .Iaddend. .Iadd.19. The combination of claim 13 in which areas of the second metallic layer that are bonded to the first metallic layer are essentially gold, and in which the first metallic layer is nondestructively detachable from the second metallic layer by means of a
mechanical pulling apart. .Iaddend. .Iadd.20. The combination of claim 19 in which the surface of the first metallic layer is essentially gold. .Iaddend. .Iadd.21. The combination of claim 13 in which a surface of the
first metallic layer is essentially gold. .Iaddend. .Iadd.22. The combination of claim 13 in which the indentations have widths, as measured at the tops or at the bottoms of the indentations, of about 1 micrometer or less. .Iaddend.
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Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675179A (en) * 1995-01-13 1997-10-07 Vlsi Technology, Inc. Universal test die and method for fine pad pitch designs
US5798286A (en) * 1995-09-22 1998-08-25 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US5801441A (en) * 1994-07-07 1998-09-01 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US5848467A (en) * 1990-09-24 1998-12-15 Tessera, Inc. Methods of making semiconductor chip assemblies
US6133627A (en) 1990-09-24 2000-10-17 Tessera, Inc. Semiconductor chip package with center contacts
US6221750B1 (en) 1998-10-28 2001-04-24 Tessera, Inc. Fabrication of deformable leads of microelectronic elements
US6265765B1 (en) 1994-07-07 2001-07-24 Tessera, Inc. Fan-out semiconductor chip assembly
US6333207B1 (en) 1999-05-24 2001-12-25 Tessera, Inc. Peelable lead structure and method of manufacture
US6429112B1 (en) 1994-07-07 2002-08-06 Tessera, Inc. Multi-layer substrates and fabrication processes
US6448505B1 (en) * 1999-10-29 2002-09-10 Kyocera Corporation Substrate for mounting an optical component, a method for producing the same, and an optical module using the same
US6498307B2 (en) * 1998-03-11 2002-12-24 Fujitsu Limited Electronic component package, printing circuit board, and method of inspecting the printed circuit board
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6528889B1 (en) * 1998-06-30 2003-03-04 Seiko Instruments Inc. Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
US20030071346A1 (en) * 1994-07-07 2003-04-17 Tessera, Inc. Flexible lead structures and methods of making same
US6709906B2 (en) 1994-02-28 2004-03-23 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US20060148166A1 (en) * 2004-11-08 2006-07-06 Craig Gordon S Assembly comprising functional devices and method of making same
US7149422B2 (en) 2001-01-10 2006-12-12 Ip Holdings, Inc. Motion detector camera
US7214569B2 (en) * 2002-01-23 2007-05-08 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
US7260882B2 (en) 2001-05-31 2007-08-28 Alien Technology Corporation Methods for making electronic devices with small functional elements supported on a carriers
US7288432B2 (en) 1999-03-16 2007-10-30 Alien Technology Corporation Electronic devices with small functional elements supported on a carrier
US7385284B2 (en) 2004-11-22 2008-06-10 Alien Technology Corporation Transponder incorporated into an electronic device
US7452748B1 (en) 2004-11-08 2008-11-18 Alien Technology Corporation Strap assembly comprising functional block deposited therein and method of making same
US20080314627A1 (en) * 2006-04-07 2008-12-25 Murata Manufacturing Co., Ltd. Electronic component and method for manufacturing the same
US20090065910A1 (en) * 2007-07-31 2009-03-12 Mitsuhiro Hamada Semiconductor device and manufacturing method of the same
US7542301B1 (en) 2005-06-22 2009-06-02 Alien Technology Corporation Creating recessed regions in a substrate and assemblies having such recessed regions
US7551141B1 (en) 2004-11-08 2009-06-23 Alien Technology Corporation RFID strap capacitively coupled and method of making same
US7630174B2 (en) 2006-01-20 2009-12-08 Hitachi Global Storage Technologies Netherlands B.V. Suspension and prober designs for recording head testing
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US8191756B2 (en) 2004-11-04 2012-06-05 Microchips, Inc. Hermetically sealing using a cold welded tongue and groove structure
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus
USD702240S1 (en) 2012-04-13 2014-04-08 Blackberry Limited UICC apparatus
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
US8959760B2 (en) 2007-09-20 2015-02-24 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same

Families Citing this family (137)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4937653A (en) * 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US5585282A (en) * 1991-06-04 1996-12-17 Micron Technology, Inc. Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor
US6340894B1 (en) 1991-06-04 2002-01-22 Micron Technology, Inc. Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect
US5559444A (en) * 1991-06-04 1996-09-24 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5716218A (en) * 1991-06-04 1998-02-10 Micron Technology, Inc. Process for manufacturing an interconnect for testing a semiconductor die
US5686317A (en) * 1991-06-04 1997-11-11 Micron Technology, Inc. Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die
US5640762A (en) 1988-09-30 1997-06-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US6219908B1 (en) 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US6828812B2 (en) * 1991-06-04 2004-12-07 Micron Technology, Inc. Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections
US5946553A (en) * 1991-06-04 1999-08-31 Micron Technology, Inc. Process for manufacturing a semiconductor package with bi-substrate die
US5169745A (en) * 1989-09-12 1992-12-08 Ricoh Company, Ltd. Optical information recording medium
CA2034703A1 (en) * 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
US5124281A (en) * 1990-08-27 1992-06-23 At&T Bell Laboratories Method of fabricating a photonics module comprising a spherical lens
NL9001982A (en) * 1990-09-10 1992-04-01 Koninkl Philips Electronics Nv An interconnection structure.
JP3137375B2 (en) * 1990-09-20 2001-02-19 株式会社東芝 Pressure-contact type semiconductor device
US7198969B1 (en) * 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US20010030370A1 (en) * 1990-09-24 2001-10-18 Khandros Igor Y. Microelectronic assembly having encapsulated wire bonding leads
US5214844A (en) * 1990-12-17 1993-06-01 Nchip, Inc. Method of assembling integrated circuits to a silicon board
US5274270A (en) * 1990-12-17 1993-12-28 Nchip, Inc. Multichip module having SiO2 insulating layer
US5134539A (en) * 1990-12-17 1992-07-28 Nchip, Inc. Multichip module having integral decoupling capacitor
US5262674A (en) * 1991-02-04 1993-11-16 Motorola, Inc. Chip carrier for an integrated circuit assembly
US5495179A (en) * 1991-06-04 1996-02-27 Micron Technology, Inc. Carrier having interchangeable substrate used for testing of semiconductor dies
US5519332A (en) * 1991-06-04 1996-05-21 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
US5541525A (en) * 1991-06-04 1996-07-30 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
US6094058A (en) * 1991-06-04 2000-07-25 Micron Technology, Inc. Temporary semiconductor package having dense array external contacts
US5578934A (en) * 1991-06-04 1996-11-26 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5815000A (en) * 1991-06-04 1998-09-29 Micron Technology, Inc. Method for testing semiconductor dice with conventionally sized temporary packages
JP2839795B2 (en) * 1991-08-09 1998-12-16 シャープ株式会社 Semiconductor device
US5578526A (en) * 1992-03-06 1996-11-26 Micron Technology, Inc. Method for forming a multi chip module (MCM)
EP0577333B1 (en) * 1992-06-29 1999-11-10 AT&T Corp. Temporary connections for fast electrical access to electronic devices
US5323035A (en) * 1992-10-13 1994-06-21 Glenn Leedy Interconnection structure for integrated circuits and method for making same
US20050062492A1 (en) * 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
US5371654A (en) * 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
JPH06188385A (en) * 1992-10-22 1994-07-08 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5291572A (en) * 1993-01-14 1994-03-01 At&T Bell Laboratories Article comprising compression bonded parts
US5545589A (en) * 1993-01-28 1996-08-13 Matsushita Electric Industrial Co., Ltd. Method of forming a bump having a rugged side, a semiconductor device having the bump, and a method of mounting a semiconductor unit and a semiconductor device
US5461333A (en) * 1993-03-15 1995-10-24 At&T Ipm Corp. Multi-chip modules having chip-to-chip interconnections with reduced signal voltage level and swing
US6414506B2 (en) 1993-09-03 2002-07-02 Micron Technology, Inc. Interconnect for testing semiconductor dice having raised bond pads
US5326428A (en) 1993-09-03 1994-07-05 Micron Semiconductor, Inc. Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
US5483741A (en) * 1993-09-03 1996-01-16 Micron Technology, Inc. Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
US5677203A (en) * 1993-12-15 1997-10-14 Chip Supply, Inc. Method for providing known good bare semiconductor die
US5478779A (en) 1994-03-07 1995-12-26 Micron Technology, Inc. Electrically conductive projections and semiconductor processing method of forming same
US5632631A (en) * 1994-06-07 1997-05-27 Tessera, Inc. Microelectronic contacts with asperities and methods of making same
US5615824A (en) * 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
US6848173B2 (en) * 1994-07-07 2005-02-01 Tessera, Inc. Microelectric packages having deformed bonded leads and methods therefor
US6117694A (en) * 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5830782A (en) * 1994-07-07 1998-11-03 Tessera, Inc. Microelectronic element bonding with deformation of leads in rows
US6361959B1 (en) 1994-07-07 2002-03-26 Tessera, Inc. Microelectronic unit forming methods and materials
US5795194A (en) 1995-09-29 1998-08-18 Berg Technology, Inc. Electrical connector with V-grooves
KR100202998B1 (en) * 1995-12-02 1999-06-15 남재우 Wafer probe card having a micro-tip and manufacturing method thereof
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules
US6006739A (en) * 1996-11-12 1999-12-28 Micron Technology, Inc. Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
US6493934B2 (en) 1996-11-12 2002-12-17 Salman Akram Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
US6250192B1 (en) 1996-11-12 2001-06-26 Micron Technology, Inc. Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
US6037786A (en) * 1996-12-13 2000-03-14 International Business Machines Corporation Testing integrated circuit chips
EP0954420B1 (en) * 1996-12-19 2003-03-12 TELEFONAKTIEBOLAGET L M ERICSSON (publ) Method for making elastic bumps
US6016060A (en) * 1997-03-25 2000-01-18 Micron Technology, Inc. Method, apparatus and system for testing bumped semiconductor components
US5962921A (en) 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
JP3704883B2 (en) * 1997-05-01 2005-10-12 コニカミノルタホールディングス株式会社 The organic electroluminescent device and a manufacturing method thereof
US5931685A (en) * 1997-06-02 1999-08-03 Micron Technology, Inc. Interconnect for making temporary electrical connections with bumped semiconductor components
US6040702A (en) 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US6396291B1 (en) 1999-04-23 2002-05-28 Micron Technology, Inc. Method for testing semiconductor components
US6072326A (en) * 1997-08-22 2000-06-06 Micron Technology, Inc. System for testing semiconductor components
US5977642A (en) 1997-08-25 1999-11-02 International Business Machines Corporation Dendrite interconnect for planarization and method for producing same
JPH11214450A (en) * 1997-11-18 1999-08-06 Matsushita Electric Ind Co Ltd Electronic part mounting body, electronic apparatus using the same and method for manufacturing electronic part mounting body
US6028436A (en) 1997-12-02 2000-02-22 Micron Technology, Inc. Method for forming coaxial silicon interconnects
US6441315B1 (en) 1998-11-10 2002-08-27 Formfactor, Inc. Contact structures with blades having a wiping motion
US6980017B1 (en) 1999-03-10 2005-12-27 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6222280B1 (en) 1999-03-22 2001-04-24 Micron Technology, Inc. Test interconnect for semiconductor components having bumped and planar contacts
US6437591B1 (en) 1999-03-25 2002-08-20 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6285203B1 (en) 1999-06-14 2001-09-04 Micron Technology, Inc. Test system having alignment member for aligning semiconductor components
US6556030B1 (en) * 1999-09-01 2003-04-29 Micron Technology, Inc. Method of forming an electrical contact
US6297562B1 (en) * 1999-09-20 2001-10-02 Telefonaktieboalget Lm Ericsson (Publ) Semiconductive chip having a bond pad located on an active device
US6759858B2 (en) * 1999-10-20 2004-07-06 Intel Corporation Integrated circuit test probe having ridge contact
EP1278612B1 (en) * 2000-03-10 2010-02-24 Chippac, Inc. Flip chip Interconnection structure and method of obtaining the same
DE10014300A1 (en) * 2000-03-23 2001-10-04 Infineon Technologies Ag Semiconductor device and process for its preparation
US6350632B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with ball bond connection joint
US6511865B1 (en) 2000-09-20 2003-01-28 Charles W. C. Lin Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly
US6350386B1 (en) 2000-09-20 2002-02-26 Charles W. C. Lin Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly
US6448108B1 (en) 2000-10-02 2002-09-10 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6544813B1 (en) 2000-10-02 2003-04-08 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6537851B1 (en) 2000-10-13 2003-03-25 Bridge Semiconductor Corporation Method of connecting a bumped compliant conductive trace to a semiconductor chip
US7262082B1 (en) 2000-10-13 2007-08-28 Bridge Semiconductor Corporation Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture
US6949408B1 (en) 2000-10-13 2005-09-27 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
US7094676B1 (en) 2000-10-13 2006-08-22 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal pillar
US6908788B1 (en) 2000-10-13 2005-06-21 Bridge Semiconductor Corporation Method of connecting a conductive trace to a semiconductor chip using a metal base
US7425759B1 (en) 2003-11-20 2008-09-16 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal and filler
US6673710B1 (en) 2000-10-13 2004-01-06 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip
US6576539B1 (en) 2000-10-13 2003-06-10 Charles W.C. Lin Semiconductor chip assembly with interlocked conductive trace
US6699780B1 (en) 2000-10-13 2004-03-02 Bridge Semiconductor Corporation Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching
US6876072B1 (en) 2000-10-13 2005-04-05 Bridge Semiconductor Corporation Semiconductor chip assembly with chip in substrate cavity
US6492252B1 (en) 2000-10-13 2002-12-10 Bridge Semiconductor Corporation Method of connecting a bumped conductive trace to a semiconductor chip
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
US7132741B1 (en) 2000-10-13 2006-11-07 Bridge Semiconductor Corporation Semiconductor chip assembly with carved bumped terminal
US7993983B1 (en) 2003-11-17 2011-08-09 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with chip and encapsulant grinding
US7446419B1 (en) 2004-11-10 2008-11-04 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar of stacked metal balls
US7538415B1 (en) 2003-11-20 2009-05-26 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal, filler and insulative base
US6576493B1 (en) 2000-10-13 2003-06-10 Bridge Semiconductor Corporation Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps
US6440835B1 (en) 2000-10-13 2002-08-27 Charles W. C. Lin Method of connecting a conductive trace to a semiconductor chip
US7071089B1 (en) 2000-10-13 2006-07-04 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a carved bumped terminal
US7264991B1 (en) 2000-10-13 2007-09-04 Bridge Semiconductor Corporation Method of connecting a conductive trace to a semiconductor chip using conductive adhesive
US6667229B1 (en) 2000-10-13 2003-12-23 Bridge Semiconductor Corporation Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
US6800506B1 (en) 2000-10-13 2004-10-05 Bridge Semiconductor Corporation Method of making a bumped terminal in a laminated structure for a semiconductor chip assembly
US6809414B1 (en) 2000-10-13 2004-10-26 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped conductive trace
US6548393B1 (en) 2000-10-13 2003-04-15 Charles W. C. Lin Semiconductor chip assembly with hardened connection joint
US7414319B2 (en) * 2000-10-13 2008-08-19 Bridge Semiconductor Corporation Semiconductor chip assembly with metal containment wall and solder terminal
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US7129113B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture
US7319265B1 (en) 2000-10-13 2008-01-15 Bridge Semiconductor Corporation Semiconductor chip assembly with precision-formed metal pillar
US7190080B1 (en) 2000-10-13 2007-03-13 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal pillar
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US7075186B1 (en) 2000-10-13 2006-07-11 Bridge Semiconductor Corporation Semiconductor chip assembly with interlocked contact terminal
US6444489B1 (en) 2000-12-15 2002-09-03 Charles W. C. Lin Semiconductor chip assembly with bumped molded substrate
JP2002222832A (en) * 2001-01-29 2002-08-09 Nec Corp Semiconductor device and packaging method of semiconductor element
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
US6707684B1 (en) 2001-04-02 2004-03-16 Advanced Micro Devices, Inc. Method and apparatus for direct connection between two integrated circuits via a connector
US20020185121A1 (en) * 2001-06-06 2002-12-12 Farnworth Warren M. Group encapsulated dicing chuck
US20030113947A1 (en) * 2001-12-19 2003-06-19 Vandentop Gilroy J. Electrical/optical integration scheme using direct copper bonding
US20040105244A1 (en) * 2002-08-06 2004-06-03 Ilyas Mohammed Lead assemblies with offset portions and microelectronic assemblies with leads having offset portions
JP4036786B2 (en) * 2003-04-24 2008-01-23 シャープ株式会社 Electronic component mounting method
US7811863B1 (en) 2006-10-26 2010-10-12 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment
DE102005049235B4 (en) * 2004-10-20 2009-07-09 Panasonic Corp., Kadoma of the same switch and method of manufacturing
ES2359919T3 (en) 2006-03-16 2011-05-30 Eles Semiconductor Equipment S.P.A. Interconnection of electronic devices with high drivers.
US7704107B1 (en) * 2006-05-09 2010-04-27 Randall Mark Desmond Conductive coil connector for reconfigurable electrical circuit element
DE102006028719B4 (en) * 2006-06-20 2008-05-08 Infineon Technologies Ag A semiconductor device with semiconductor chip stack and connecting elements and methods for manufacturing the semiconductor device
WO2008020391A3 (en) * 2006-08-17 2008-06-19 Nxp Bv Reducing stress between a substrate and a projecting electrode on the substrate
WO2008071576A3 (en) * 2006-12-11 2008-08-28 Continental Automotive Gmbh Circuit arrangement and method for producing a circuit arrangement
US7494843B1 (en) 2006-12-26 2009-02-24 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding
FR2928033B1 (en) * 2008-02-22 2010-07-30 Commissariat Energie Atomique connection component provided with hollow inserts.
US20120146247A1 (en) * 2010-10-04 2012-06-14 Itzhak Pomerantz Pre-treatment of memory cards for binding glue and other curable fluids
WO2012045201A1 (en) * 2010-10-04 2012-04-12 Sandisk Semiconductor (Shanghai) Co., Ltd. Pre-treatment of memory cards for ink jet printing
JP2012124452A (en) * 2010-12-06 2012-06-28 Samsung Electro-Mechanics Co Ltd Printed substrate and manufacturing method of the same
US20130288070A1 (en) * 2012-04-27 2013-10-31 Analog Devices, Inc. Method for Creating Asperities in Metal for Metal-to-Metal Bonding

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB877674A (en) * 1959-09-30 1961-09-20 Gerhard Muller Improvements in or relating to co-operating electrical contacts engageable by relative sliding displacement
US3349296A (en) * 1961-10-31 1967-10-24 Siemens Ag Electronic semiconductor device
US4104676A (en) * 1975-12-15 1978-08-01 Siemens Aktiengesellschaft Semiconductor device with pressure electrical contacts having irregular surfaces
DE2816328A1 (en) * 1977-04-15 1978-10-19 Ibm Releasable electrical connector system - is formed by growing layers of dendritic crystals on metal surface and dendrites interlock to give good contact
JPS54145476A (en) * 1978-05-06 1979-11-13 Toshiba Corp Package for semiconductor
GB1568464A (en) * 1977-04-15 1980-05-29 Ibm Electrical contacts
US4263702A (en) * 1979-05-18 1981-04-28 The United States Of America As Represented By The Secretary Of The Army Method of making a quartz resonator
JPS60186042A (en) * 1984-03-05 1985-09-21 Ngk Spark Plug Co Ltd Ceramic package
JPS60194545A (en) * 1984-03-16 1985-10-03 Hitachi Ltd Semiconductor device and manufacture thereof
JPS61172362A (en) * 1985-01-28 1986-08-04 Seiko Epson Corp Bonding electrode structure
US4670770A (en) * 1984-02-21 1987-06-02 American Telephone And Telegraph Company Integrated circuit chip-and-substrate assembly
US4695870A (en) * 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
US4748483A (en) * 1979-07-03 1988-05-31 Higratherm Electric Gmbh Mechanical pressure Schottky contact array
US4881118A (en) * 1988-02-22 1989-11-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4937653A (en) * 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US5124281A (en) * 1990-08-27 1992-06-23 At&T Bell Laboratories Method of fabricating a photonics module comprising a spherical lens

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB877674A (en) * 1959-09-30 1961-09-20 Gerhard Muller Improvements in or relating to co-operating electrical contacts engageable by relative sliding displacement
US3349296A (en) * 1961-10-31 1967-10-24 Siemens Ag Electronic semiconductor device
US4104676A (en) * 1975-12-15 1978-08-01 Siemens Aktiengesellschaft Semiconductor device with pressure electrical contacts having irregular surfaces
DE2816328A1 (en) * 1977-04-15 1978-10-19 Ibm Releasable electrical connector system - is formed by growing layers of dendritic crystals on metal surface and dendrites interlock to give good contact
GB1568464A (en) * 1977-04-15 1980-05-29 Ibm Electrical contacts
JPS54145476A (en) * 1978-05-06 1979-11-13 Toshiba Corp Package for semiconductor
US4263702A (en) * 1979-05-18 1981-04-28 The United States Of America As Represented By The Secretary Of The Army Method of making a quartz resonator
US4748483A (en) * 1979-07-03 1988-05-31 Higratherm Electric Gmbh Mechanical pressure Schottky contact array
US4670770A (en) * 1984-02-21 1987-06-02 American Telephone And Telegraph Company Integrated circuit chip-and-substrate assembly
JPS60186042A (en) * 1984-03-05 1985-09-21 Ngk Spark Plug Co Ltd Ceramic package
JPS60194545A (en) * 1984-03-16 1985-10-03 Hitachi Ltd Semiconductor device and manufacture thereof
JPS61172362A (en) * 1985-01-28 1986-08-04 Seiko Epson Corp Bonding electrode structure
US4695870A (en) * 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
US4881118A (en) * 1988-02-22 1989-11-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4937653A (en) * 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US5124281A (en) * 1990-08-27 1992-06-23 At&T Bell Laboratories Method of fabricating a photonics module comprising a spherical lens

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
G. A. Kennedy, Welding Technology, p. 15 (1974). *
P. Kraynak, "Wafer-Chip Assembly for Large-Scale Integration", IEEE Transactions on Electron Devices, vol. ED-15, pp. 660-663 (1968).
P. Kraynak, Wafer Chip Assembly for Large Scale Integration , IEEE Transactions on Electron Devices, vol. ED 15, pp. 660 663 (1968). *
R. F. Tylecote, The Solid Phase Welding of Metals, pp. 189 193 (1968). *
R. F. Tylecote, The Solid Phase Welding of Metals, pp. 189-193 (1968).

Cited By (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6133627A (en) 1990-09-24 2000-10-17 Tessera, Inc. Semiconductor chip package with center contacts
US6372527B1 (en) 1990-09-24 2002-04-16 Tessera, Inc. Methods of making semiconductor chip assemblies
US6465893B1 (en) 1990-09-24 2002-10-15 Tessera, Inc. Stacked chip assembly
US5848467A (en) * 1990-09-24 1998-12-15 Tessera, Inc. Methods of making semiconductor chip assemblies
US5950304A (en) 1990-09-24 1999-09-14 Tessera, Inc. Methods of making semiconductor chip assemblies
US6433419B2 (en) 1990-09-24 2002-08-13 Tessera, Inc. Face-up semiconductor chip assemblies
US6709906B2 (en) 1994-02-28 2004-03-23 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5801441A (en) * 1994-07-07 1998-09-01 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US6635553B1 (en) 1994-07-07 2003-10-21 Iessera, Inc. Microelectronic assemblies with multiple leads
US20030071346A1 (en) * 1994-07-07 2003-04-17 Tessera, Inc. Flexible lead structures and methods of making same
US7166914B2 (en) 1994-07-07 2007-01-23 Tessera, Inc. Semiconductor package with heat sink
US6429112B1 (en) 1994-07-07 2002-08-06 Tessera, Inc. Multi-layer substrates and fabrication processes
US6265765B1 (en) 1994-07-07 2001-07-24 Tessera, Inc. Fan-out semiconductor chip assembly
US6965158B2 (en) 1994-07-07 2005-11-15 Tessera, Inc. Multi-layer substrates and fabrication processes
US5675179A (en) * 1995-01-13 1997-10-07 Vlsi Technology, Inc. Universal test die and method for fine pad pitch designs
US5798286A (en) * 1995-09-22 1998-08-25 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US6365436B1 (en) 1995-09-22 2002-04-02 Tessera, Inc. Connecting multiple microelectronic elements with lead deformation
US6727718B2 (en) 1998-03-11 2004-04-27 Fujistu Limited Electronic component package, printed circuit board, and method of inspecting the printed circuit board
US6498307B2 (en) * 1998-03-11 2002-12-24 Fujitsu Limited Electronic component package, printing circuit board, and method of inspecting the printed circuit board
US6528889B1 (en) * 1998-06-30 2003-03-04 Seiko Instruments Inc. Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
US20010009305A1 (en) * 1998-10-28 2001-07-26 Joseph Fjelstad Microelectronic elements with deformable leads
US6221750B1 (en) 1998-10-28 2001-04-24 Tessera, Inc. Fabrication of deformable leads of microelectronic elements
US6906422B2 (en) 1998-10-28 2005-06-14 Tessera, Inc. Microelectronic elements with deformable leads
US7425467B2 (en) 1999-03-16 2008-09-16 Alien Technology Corporation Web process interconnect in electronic assemblies
US20080036087A1 (en) * 1999-03-16 2008-02-14 Jacobsen Jeffrey J Web process interconnect in electronic assemblies
US7288432B2 (en) 1999-03-16 2007-10-30 Alien Technology Corporation Electronic devices with small functional elements supported on a carrier
US6333207B1 (en) 1999-05-24 2001-12-25 Tessera, Inc. Peelable lead structure and method of manufacture
US6448505B1 (en) * 1999-10-29 2002-09-10 Kyocera Corporation Substrate for mounting an optical component, a method for producing the same, and an optical module using the same
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6906408B2 (en) 2000-07-12 2005-06-14 Micron Technology, Inc. Assemblies and packages including die-to-die connections
US6984544B2 (en) 2000-07-12 2006-01-10 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US7149422B2 (en) 2001-01-10 2006-12-12 Ip Holdings, Inc. Motion detector camera
US7260882B2 (en) 2001-05-31 2007-08-28 Alien Technology Corporation Methods for making electronic devices with small functional elements supported on a carriers
US8516683B2 (en) 2001-05-31 2013-08-27 Alien Technology Corporation Methods of making a radio frequency identification (RFID) tags
US7559131B2 (en) 2001-05-31 2009-07-14 Alien Technology Corporation Method of making a radio frequency identification (RFID) tag
US7214569B2 (en) * 2002-01-23 2007-05-08 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US8912907B2 (en) 2003-03-24 2014-12-16 Alien Technology, Llc RFID tags and processes for producing RFID tags
US7868766B2 (en) 2003-03-24 2011-01-11 Alien Technology Corporation RFID tags and processes for producing RFID tags
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
US9418328B2 (en) 2003-03-24 2016-08-16 Ruizhang Technology Limited Company RFID tags and processes for producing RFID tags
US7489248B2 (en) 2003-03-24 2009-02-10 Alien Technology Corporation RFID tags and processes for producing RFID tags
US8350703B2 (en) 2003-03-24 2013-01-08 Alien Technology Corporation RFID tags and processes for producing RFID tags
US8191756B2 (en) 2004-11-04 2012-06-05 Microchips, Inc. Hermetically sealing using a cold welded tongue and groove structure
US9796583B2 (en) 2004-11-04 2017-10-24 Microchips Biotech, Inc. Compression and cold weld sealing method for an electrical via connection
US7551141B1 (en) 2004-11-08 2009-06-23 Alien Technology Corporation RFID strap capacitively coupled and method of making same
US7967204B2 (en) 2004-11-08 2011-06-28 Alien Technology Corporation Assembly comprising a functional device and a resonator and method of making same
US7615479B1 (en) 2004-11-08 2009-11-10 Alien Technology Corporation Assembly comprising functional block deposited therein
US7452748B1 (en) 2004-11-08 2008-11-18 Alien Technology Corporation Strap assembly comprising functional block deposited therein and method of making same
US7500610B1 (en) 2004-11-08 2009-03-10 Alien Technology Corporation Assembly comprising a functional device and a resonator and method of making same
US7353598B2 (en) 2004-11-08 2008-04-08 Alien Technology Corporation Assembly comprising functional devices and method of making same
US20060148166A1 (en) * 2004-11-08 2006-07-06 Craig Gordon S Assembly comprising functional devices and method of making same
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US7385284B2 (en) 2004-11-22 2008-06-10 Alien Technology Corporation Transponder incorporated into an electronic device
US8471709B2 (en) 2004-11-22 2013-06-25 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US9070063B2 (en) 2004-11-22 2015-06-30 Ruizhang Technology Limited Company Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US7542301B1 (en) 2005-06-22 2009-06-02 Alien Technology Corporation Creating recessed regions in a substrate and assemblies having such recessed regions
US7630174B2 (en) 2006-01-20 2009-12-08 Hitachi Global Storage Technologies Netherlands B.V. Suspension and prober designs for recording head testing
US20080314627A1 (en) * 2006-04-07 2008-12-25 Murata Manufacturing Co., Ltd. Electronic component and method for manufacturing the same
US7839003B2 (en) * 2007-07-31 2010-11-23 Panasonic Corporation Semiconductor device including a coupling conductor having a concave and convex
US20090065910A1 (en) * 2007-07-31 2009-03-12 Mitsuhiro Hamada Semiconductor device and manufacturing method of the same
US8959760B2 (en) 2007-09-20 2015-02-24 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same
US9060459B2 (en) 2007-09-20 2015-06-16 Ibiden Co., Ltd. Printed wiring board and method for manufacturing same
US8649820B2 (en) 2011-11-07 2014-02-11 Blackberry Limited Universal integrated circuit card apparatus and related methods
USD702240S1 (en) 2012-04-13 2014-04-08 Blackberry Limited UICC apparatus
USD703208S1 (en) 2012-04-13 2014-04-22 Blackberry Limited UICC apparatus
US8936199B2 (en) 2012-04-13 2015-01-20 Blackberry Limited UICC apparatus and related methods
USD702241S1 (en) 2012-04-23 2014-04-08 Blackberry Limited UICC apparatus
USD701864S1 (en) * 2012-04-23 2014-04-01 Blackberry Limited UICC apparatus

Also Published As

Publication number Publication date Type
JP1853074C (en) grant
EP0352020B1 (en) 1994-10-12 grant
JPH0267742A (en) 1990-03-07 application
DE68918775T2 (en) 1995-02-16 grant
EP0352020A3 (en) 1991-07-17 application
JPH0574224B2 (en) 1993-10-18 grant
US4937653A (en) 1990-06-26 grant
DE68918775D1 (en) 1994-11-17 grant
EP0352020A2 (en) 1990-01-24 application

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