USRE34269E - Semiconductor integrated circuit packages - Google Patents

Semiconductor integrated circuit packages Download PDF

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Publication number
USRE34269E
USRE34269E US07/837,573 US83757392A USRE34269E US RE34269 E USRE34269 E US RE34269E US 83757392 A US83757392 A US 83757392A US RE34269 E USRE34269 E US RE34269E
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United States
Prior art keywords
paddle
absorbing member
integrated circuit
deformation absorbing
semiconductor integrated
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Expired - Lifetime
Application number
US07/837,573
Inventor
Harold W. Moyer
Harry R. Scholz
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Nokia Bell Labs
Agere Systems LLC
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AT&T Bell Laboratories Inc
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Priority claimed from US06/934,062 external-priority patent/US4803540A/en
Application filed by AT&T Bell Laboratories Inc filed Critical AT&T Bell Laboratories Inc
Priority to US07/837,573 priority Critical patent/USRE34269E/en
Application granted granted Critical
Publication of USRE34269E publication Critical patent/USRE34269E/en
Assigned to CHASE MANHATTAN BANK, AS ADMINISTRATIVE AGENT, THE reassignment CHASE MANHATTAN BANK, AS ADMINISTRATIVE AGENT, THE CONDITIONAL ASSIGNMENT OF AND SECURITY INTEREST IN PATENT RIGHTS Assignors: AGERE SYSTEMS GUARDIAN CORP. (DE CORPORATION)
Assigned to AGERE SYSTEMS GUARDIAN CORP. reassignment AGERE SYSTEMS GUARDIAN CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LUCENT TECHNOLOGIES INC.
Assigned to AGERE SYSTEMS GUARDIAN CORP. reassignment AGERE SYSTEMS GUARDIAN CORP. TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Assignors: JPMORGAN CHASE BANK (F/K/A THE CHASE MANHATTAN BANK)
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • This invention relates generally to packages for semiconductor integrated circuits.
  • An essential part of semiconductor integrated circuit manufacture resides in the placing of the integrated circuit chip into a package so that the chip can be conveniently contacted electrically as well as mounted in a physically secure manner.
  • the chip itself is mounted on a lead frame which has a plurality of fingers for electrical connections and a paddle for physical support.
  • the paddle is connected physically to an external mounting frame by paddle support arms. Electrical contacts are made through wires bonded to the fingers and to the paddle.
  • the package could be assembled using a lead frame in which the paddle remains in the same plane as do the fingers, it has often been found desirable to assemble a package using a lead frame in which the paddle has been depressed, i.e., made lower, with respect to the external mounting frame and fingers. It has been found that this configuration reduces the number of edge shorts between the electrical contact wires and the chip. It also allows a balanced flow condition during molding.
  • the depressed positioning will necessarily lead to a physical deformation of the paddle support arms during the forming process because the lead frame is initially a flat metal piece. The deformation will generally be in the form of a necking down, i.e., a constriction of paddle support arms in the transverse axial direction.
  • a semiconductor integrated circuit package which as a semiconductor integrated circuit chip and a lead frame, on which said chip is mounted, having a plurality of fingers, a paddle and a plurality of paddle support arms with the paddle support arms having a deformation absorbing member.
  • the lead frame is formed so that the paddle is in a depressed position with respect to the external mounting frame .Iadd.and to at least a portion of the fingers. .Iaddend.
  • the deformation absorbing member is designed to maintain the desired mechanical characteristics after forming. It may also retain the desired electrical characteristics if the arms are used for electrical connections.
  • the deformation absorbing member is an annular member which contracts in a direction transverse to the load direction.
  • the deformation absorbing member is a T bar.
  • the paddle is supported by the paddle support arms which terminate in a T before contacting the external mounting frame.
  • the legs of the T. perpendicular to the paddle support arm axis, are designed to deflect and absorb the deformation that results from the metal forming process of depressing the paddle.
  • the deformation absorbing member localizes the deformation which occurs during the mounting step producing the deformation.
  • FIG. 1 is a side view of a package according to the invention
  • FIG. 2 is a top view of an embodiment of this invention.
  • FIG. 3 is a top view of another embodiment of this invention.
  • FIGS. 4 and 5 illustrate still other embodiments of this invention.
  • FIG. 6 illustrates the embodiment shown in FIG. 5 along line A-A'.
  • FIG. 1 A side view of an exemplary integrated circuit package is depicted in FIG. 1. Depicted are semiconductor chip 1 which is mounted on paddle 3 by means of epoxy material 5. Paddle 3 is part of the lead frame which also has a plurality of fingers 7 and paddle support arms 9 for physical support. The fingers 7 are connected to the external mounting frame 13. There are electrical connections 15 between the chip and the fingers 7. As can be seen, the paddle 3 is positioned lower than the external mounting frame 13 because the paddle support arms have been deformed. .Iadd.It can also be seen that the paddle is positioned lower than the lead frame fingers; i.e., it is depressed with respect to at least a portion of the lead frame fingers.
  • the paddle support arms are bent to accommodate the vertical mismatch and each has a deformation absorbing member which localizes the deformation to the vicinity of that member.
  • FIG. 2 is a top view of the single site depicted in FIG. 1 of a typical lead frame. Depicted are a lead frame site comprising an external mounting frame 13, a paddle 3, a plurality of fingers 7, and a plurality of paddle support arms 9 extending from the paddle. Each paddle support arm has a deformation absorbing member 11. For reasons of clarity, not all fingers are depicted.
  • the deformation absorbing member 11 comprises an annular member, i.e., a member with expanded dimensions in the direction perpendicular to the major axis of the paddle support arm.
  • the annular member is depicted as being circular although other shapes, e.g., oval, can be used.
  • the deformation absorbing member constricts in the direction perpendicular to the axis of motion.
  • the desired electrical and physical characteristics are maintained after the forming operation as the paddle support arm does not form a necked down region.
  • the deformation absorbing member compensate for the axial motion along the paddle support arm. Further steps required for packaging need not be desired in detail as they are well known to those skilled in the art.
  • FIG. 3 illustrates another embodiment of a paddle support arm 11 having a deformation absorbing member which comprises a T bar with the two ends of the T mounted to the external mounting frame .Iadd.and to at least a portion of the fingers.Iaddend..
  • the paddle support arms move radially inward causing the ends of the T to deflect about the mounting axis in the direction shown by the arrows.
  • FIGS. 4 and 5 Other embodiments are contemplated, and two embodiments are depicted in FIGS. 4 and 5.
  • the deformation absorbing member comprises an S bend while in FIG. 5 it comprises a wrinkle.
  • FIG. 6 shows the wrinkle along line A-A' in FIG. 5.

Abstract

A lead frame for mounting a semiconductor chip in an integrated circuit package incorporates a deformation absorbing member as an integral part of the paddle support arm so that the initial, desired physical and electrical characteristics are unaltered after a forming operation such as paddle downsetting.

Description

.Iadd.This application is a continuation of application Ser. No. 07/635,362, filed on Feb. 6, 1991, now abandoned, which is a reissue of Moyer 6-4, Ser. No. 06/934,062, filed on Nov. 24, 1986, U.S. Pat. No. 4,803,540. .Iaddend.
TECHNICAL FIELD
This invention relates generally to packages for semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
An essential part of semiconductor integrated circuit manufacture resides in the placing of the integrated circuit chip into a package so that the chip can be conveniently contacted electrically as well as mounted in a physically secure manner. The chip itself is mounted on a lead frame which has a plurality of fingers for electrical connections and a paddle for physical support. The paddle is connected physically to an external mounting frame by paddle support arms. Electrical contacts are made through wires bonded to the fingers and to the paddle.
Although the package could be assembled using a lead frame in which the paddle remains in the same plane as do the fingers, it has often been found desirable to assemble a package using a lead frame in which the paddle has been depressed, i.e., made lower, with respect to the external mounting frame and fingers. It has been found that this configuration reduces the number of edge shorts between the electrical contact wires and the chip. It also allows a balanced flow condition during molding. As will be readily appreciated by those skilled in the art, the depressed positioning will necessarily lead to a physical deformation of the paddle support arms during the forming process because the lead frame is initially a flat metal piece. The deformation will generally be in the form of a necking down, i.e., a constriction of paddle support arms in the transverse axial direction.
As feature sizes in integrated circuits continue to decrease and the scale of integration continues to increase, package designers must make more interconnects in an amount of space that is, at best, equal to that previously available. The only expedient way this may be accomplished is to decrease the width of the fingers and paddle support arms to permit placement of more fingers in either the same or a smaller area. Consequently, the combined effect of the constriction and decreased feature size may lead to problems such as loss of physical integrity and distortion of the paddle support arms. If these arms are also used for electrical connections, there may be undesirable changes in the electrical characteristics as well.
SUMMARY OF THE INVENTION
A semiconductor integrated circuit package is described which as a semiconductor integrated circuit chip and a lead frame, on which said chip is mounted, having a plurality of fingers, a paddle and a plurality of paddle support arms with the paddle support arms having a deformation absorbing member. The lead frame is formed so that the paddle is in a depressed position with respect to the external mounting frame .Iadd.and to at least a portion of the fingers. .Iaddend.The deformation absorbing member is designed to maintain the desired mechanical characteristics after forming. It may also retain the desired electrical characteristics if the arms are used for electrical connections. In one embodiment, the deformation absorbing member is an annular member which contracts in a direction transverse to the load direction. In another embodiment, the deformation absorbing member is a T bar. The paddle is supported by the paddle support arms which terminate in a T before contacting the external mounting frame. The legs of the T. perpendicular to the paddle support arm axis, are designed to deflect and absorb the deformation that results from the metal forming process of depressing the paddle. In all embodiments, the deformation absorbing member localizes the deformation which occurs during the mounting step producing the deformation.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a side view of a package according to the invention;
FIG. 2 is a top view of an embodiment of this invention; and
FIG. 3 is a top view of another embodiment of this invention;
FIGS. 4 and 5 illustrate still other embodiments of this invention; and
FIG. 6 illustrates the embodiment shown in FIG. 5 along line A-A'.
For reasons of clarity, the elements of the devices depicted are not drawn to scale.
DETAILED DESCRIPTION
A side view of an exemplary integrated circuit package is depicted in FIG. 1. Depicted are semiconductor chip 1 which is mounted on paddle 3 by means of epoxy material 5. Paddle 3 is part of the lead frame which also has a plurality of fingers 7 and paddle support arms 9 for physical support. The fingers 7 are connected to the external mounting frame 13. There are electrical connections 15 between the chip and the fingers 7. As can be seen, the paddle 3 is positioned lower than the external mounting frame 13 because the paddle support arms have been deformed. .Iadd.It can also be seen that the paddle is positioned lower than the lead frame fingers; i.e., it is depressed with respect to at least a portion of the lead frame fingers. .Iaddend.This arrangement is desirable because it facilitates making, e.g., the electrical connections as previously discussed. The paddle support arms are bent to accommodate the vertical mismatch and each has a deformation absorbing member which localizes the deformation to the vicinity of that member.
FIG. 2 is a top view of the single site depicted in FIG. 1 of a typical lead frame. Depicted are a lead frame site comprising an external mounting frame 13, a paddle 3, a plurality of fingers 7, and a plurality of paddle support arms 9 extending from the paddle. Each paddle support arm has a deformation absorbing member 11. For reasons of clarity, not all fingers are depicted. In the embodiment depicted in FIG. 2, the deformation absorbing member 11 comprises an annular member, i.e., a member with expanded dimensions in the direction perpendicular to the major axis of the paddle support arm. The annular member is depicted as being circular although other shapes, e.g., oval, can be used.
During the forming operation, i.e., as the paddle is depressed with respect to the external mounting frame, .Iadd.and to at least a portion of the lead frame fingers, .Iaddend.the deformation absorbing member constricts in the direction perpendicular to the axis of motion. However, due to the size and shape of the deformation absorbing member, the desired electrical and physical characteristics are maintained after the forming operation as the paddle support arm does not form a necked down region. Thus, it is essential that the deformation absorbing member compensate for the axial motion along the paddle support arm. Further steps required for packaging need not be desired in detail as they are well known to those skilled in the art.
FIG. 3 illustrates another embodiment of a paddle support arm 11 having a deformation absorbing member which comprises a T bar with the two ends of the T mounted to the external mounting frame .Iadd.and to at least a portion of the fingers.Iaddend.. During the forming operation, the paddle support arms move radially inward causing the ends of the T to deflect about the mounting axis in the direction shown by the arrows.
Other embodiments are contemplated, and two embodiments are depicted in FIGS. 4 and 5. In FIG. 4 the deformation absorbing member comprises an S bend while in FIG. 5 it comprises a wrinkle. FIG. 6 shows the wrinkle along line A-A' in FIG. 5.

Claims (6)

What is claimed is:
1. A semiconductor integrated circuit package comprising: a semiconductor integrated circuit chip; a lead frame, said lead frame having a paddle on which said chip is mounted and paddle support arms; and an external mounting frame having a plurality of fingers, electrical connections from said chip to said fingers, said paddle being connected to said external mounting frame by said paddle support arms CHARACTERIZED IN THAT said paddle support arms comprise a deformation absorbing member, said paddle being depressed with respect to said external mounting frame, said deformation absorbing member localizing deformation during paddle downsetting and maintaining desired physical characteristics.
2. A package as recited in claim 1 in which said deformation absorbing member comprises a T bar.
3. A package as recited in claim 1 in which said deformation absorbing member comprises an S bend member.
4. A package as recited in claim 1 in which said deformation absorbing member comprises an annular member.
5. A package as recited in claim 1 in which said deformation absorbing member comprises a wrinkle member. .Iadd.
6. A semiconductor integrated circuit package comprising:
a semiconductor integrated circuit chip;
a paddle on which said chip is mounted;
a plurality of paddle support arms, said paddle being connected to said paddle support arms;
a plurality of fingers;
electrical connections from said chip to said fingers;
CHARACTERIZED IN THAT said paddle support arms comprise a deformation absorbing member, said paddle being depressed with respect to at least a portion of said fingers, said deformation absorbing member localizing deformation during paddle downsetting and maintaining desired physical characteristics. .Iaddend. .Iadd.7. A semiconductor integrated circuit package as recited in claim 6 in which deformation absorbing member comprises a T bar. .Iaddend. .Iadd.8. A semiconductor integrated circuit package as recited in claim 6 in which deformation absorbing member comprises an S bend member. .Iaddend. .Iadd.9. A semiconductor integrated circuit package as recited in claim 6 in which deformation absorbing member comprises an annular member. .Iaddend. .Iadd.10. A semiconductor integrated circuit package as recited in claim 6 in which deformation absorbing member comprises a wrinkle member. .Iaddend.
US07/837,573 1986-11-24 1992-02-18 Semiconductor integrated circuit packages Expired - Lifetime USRE34269E (en)

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Application Number Priority Date Filing Date Title
US07/837,573 USRE34269E (en) 1986-11-24 1992-02-18 Semiconductor integrated circuit packages

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US06/934,062 US4803540A (en) 1986-11-24 1986-11-24 Semiconductor integrated circuit packages
US65336291A 1991-02-06 1991-02-06
US07/837,573 USRE34269E (en) 1986-11-24 1992-02-18 Semiconductor integrated circuit packages

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Application Number Title Priority Date Filing Date
US06/934,062 Reissue US4803540A (en) 1986-11-24 1986-11-24 Semiconductor integrated circuit packages
US65336291A Continuation 1986-11-24 1991-02-06

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5212573A (en) * 1975-07-21 1977-01-31 Hitachi Ltd Reed frame
GB2027990A (en) * 1978-08-02 1980-02-27 Hitachi Ltd Lead-frame for a semiconductor device
JPS5648163A (en) * 1979-09-28 1981-05-01 Hitachi Ltd Lead frame
US4289922A (en) * 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame
JPS5766655A (en) * 1980-10-09 1982-04-22 Mitsubishi Electric Corp Lead frame for semiconductor device
JPS57118658A (en) * 1981-12-07 1982-07-23 Hitachi Ltd Lead frame
US4477827A (en) * 1981-02-02 1984-10-16 Northern Telecom Limited Lead frame for leaded semiconductor chip carriers

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5212573A (en) * 1975-07-21 1977-01-31 Hitachi Ltd Reed frame
GB2027990A (en) * 1978-08-02 1980-02-27 Hitachi Ltd Lead-frame for a semiconductor device
US4289922A (en) * 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame
JPS5648163A (en) * 1979-09-28 1981-05-01 Hitachi Ltd Lead frame
JPS5766655A (en) * 1980-10-09 1982-04-22 Mitsubishi Electric Corp Lead frame for semiconductor device
US4477827A (en) * 1981-02-02 1984-10-16 Northern Telecom Limited Lead frame for leaded semiconductor chip carriers
JPS57118658A (en) * 1981-12-07 1982-07-23 Hitachi Ltd Lead frame

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Effective date: 20020930