USRE33461E - Generation and diagnostic verification of complex timing cycles - Google Patents
Generation and diagnostic verification of complex timing cycles Download PDFInfo
- Publication number
- USRE33461E USRE33461E US07/353,414 US35341489A USRE33461E US RE33461 E USRE33461 E US RE33461E US 35341489 A US35341489 A US 35341489A US RE33461 E USRE33461 E US RE33461E
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- US
- United States
- Prior art keywords
- timing
- memory
- bits
- clock
- memory means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
Definitions
- Timing circuitry The generation of complex multiple timing cycles for digital logic systems commonly requires extensive complex logic circuitry.
- the verification of the operation of the timing circuitry in the past has imposed additional complexity on the design requirements of the system and has not provided a high level of confidence verification.
- PROM programmable read-only memory
- a buffer and logic circuit is also included in the system. This is a group of buffers, combinational logic and sequential logic circuits which receive timing inputs from the PROM and timing and control inputs from other sources in the system. The buffer and logic circuit acts on these various inputs to produce a selected one of the several possible complex timing cycles.
- This system consisting of the PROM and the buffer and logic circuit, has two modes of operation, a Normal mode for normal system operation and a Verify mode for timing cycle verification.
- a free running clock is coupled to an address counter, which successively selects a row in the PROM, which upon selection outputs the stored information in that row to the buffer and logic section.
- the address counter operates in a cyclic manner on a continuous basis, and the PROM is read out from the starting to the ending address of the PROM section which is employed for the particular timing mode that is selected.
- the Verify mode the free running clock is disconnected and replaced with a host computer controlled clock which is stepped pulse by pulse so that the address counter steps through the rows of the PROM at a rate controlled directly by the host computer.
- Verification of programs stored in programmable read-only memory is generally achieved through the use of diagnostic software routines which utilize a checksum operation.
- the present invention utilizes a PROM which has several sections, each of which stores timing information for a different selectable mode. In normal operation this timing information is only used to generate complex timing cycles, and it is not required to be accessible to the host computer.
- the host computer, or an independent control section switches the timing circuit at a rate which allows the adder to provide a checksum for each row of the PROM, which is added to the checksum provided by all of the preceding rows.
- the digital checksum that is achieved is compared with a stored checksum which is known to be correct for the selected complex timing cycle.
- the present invention is thereby capable of providing diagnostic verification with a high level of confidence, for several different complex timing cycles that may be generated for timing the data processing system.
- the timing generation may be used with a mass memory controller to ensure that the required timing cycles occur in the correct sequences and with the correct intervals.
- FIGURE is a block diagram illustration of a system for diagnostic verification of multiple complex timing cycles.
- a complex timing cycle generator is shown in the FIGURE.
- a control 12 which is a hardware unit provides a timing clock and various timing controls to the remainder of the timing cycle generator.
- a Normal mode command is received on line 31 from the host computer by the control, it causes the output of the master clock 14 to be coupled to the timing clock output of control 12.
- Clock signals are coupled on the line 15 from clock 14 to an address counter 16 which operates over a range of addresses as determined by the timing control outputs of control 12.
- the counter may be reset and cycled over again, or it may be halted by command from the host processor on line 33 when a sufficient number of cycles of the timing generator have been completed.
- a programmable read-only memory (PROM) 18 contains the timing information for at least two timing modes which may be generated by the timing generator.
- the address counter applies output bits, via lines 19, to PROM, the output of which is supplied as raw timing signals (16 bits) on the lines 20 to a buffer and logic circuit 22, in a sequential manner from the first accessed address to the last accessed address which is associated with the selected timing cycle.
- a HOST command on line 31 to the control causes the address counter 16 to cycle in a repeated pattern to create complex timing cycles of a selected pattern on the lines 20 until a HALT command is supplied to the control 12 on line 33.
- a different section of the PROM 18 is selected by control 12. Repetitive cycling of the address counter will then cause a different group of stored bits in the PROM to be supplied on the timing lines 28.
- the control 12 will provide timing control signals from the lines 35 to the gates 42 as required to inhibit any error or status flag signals which otherwise might appear on the lines 23 during Normal mode operation and would interfere with the Verify routine.
- inhibit signals may be provided on the lines 35 to prevent the error or status flags that are supplied on the line 23 via gates 42 to the lines 37 from affecting the diagnostic procedure; and also to disable some of the refined timing lines 28, via gates 40, to preclude the possibility of altering the data stored in the mass memory.
- the timing clock output from control 12 is operated in a stepped mode so that the address counter 16 steps through each of its possible selection address outputs at a rate which allows the adder 26 to sequentially receive and add the outputs on all of the lines 24 that are associated with one count of the address counter 16 before the next count is produced.
- the adder 26 then accumulates a checksum count for all of the accessed memory locations of the PROM for the selected timing cycle under the control of the address counter 16.
- the checksum output of the adder 26 on the line 39 is a test sum which is compared by the comparator 32 to a stored checksum supplied on line 41 from the checksum storage memory 30 for the timing cycle that is selected.
- control 12 supplies a timing control to the address counter 16, the buffer and logic circuitry 22, the adder 26, the comparator 32, and the checksum storage memory 30 so that these components have their appropriate elements selected in accordance with the timing cycle selected by the control 12. If the checksum stored and the sum in the adder 26 are found to be equal by the comparator 32 a Pass signal will be produced by the comparator on the line 43. If they are not equal a Fail comparison signal will be issued indicating the failure of the timing system for the particular cycle that was selected. Each of the individual timing cycles that are capable of being selected by the system may thus be individually verified by the timing generator and verifier of the disclosed embodiment.
- sixteen output lines 20 are shown from the PROM 18.
- the lines 24 and 28 are shown as being greater in number to lines 20 but this is a function of the buffer and logic circuit 22.
- the buffer and logic circuit 22 may be implemented as required to produce various combinations of the signals from the lines 20 and from the timing control, so that it is not necessary for the number of output lines 24 to bear any fixed relationship to the number of input lines 20.
- the adder 26, comparator 32 and checksum storage 30 may be provided by dedicated hardware or by the host processor along with associated software.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/353,414 USRE33461E (en) | 1985-10-16 | 1989-05-18 | Generation and diagnostic verification of complex timing cycles |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/787,853 US4726025A (en) | 1985-10-16 | 1985-10-16 | Generation and diagnostic verification of complex timing cycles |
US07/353,414 USRE33461E (en) | 1985-10-16 | 1989-05-18 | Generation and diagnostic verification of complex timing cycles |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/787,853 Reissue US4726025A (en) | 1985-10-16 | 1985-10-16 | Generation and diagnostic verification of complex timing cycles |
Publications (1)
Publication Number | Publication Date |
---|---|
USRE33461E true USRE33461E (en) | 1990-11-27 |
Family
ID=26997928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/353,414 Expired - Lifetime USRE33461E (en) | 1985-10-16 | 1989-05-18 | Generation and diagnostic verification of complex timing cycles |
Country Status (1)
Country | Link |
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US (1) | USRE33461E (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5704033A (en) * | 1994-10-07 | 1997-12-30 | Lg Semicon Co., Ltd. | Apparatus and method for testing a program memory for a one-chip microcomputer |
US6728649B2 (en) | 2002-02-01 | 2004-04-27 | Adtran, Inc. | Method and apparatus for removing digital glitches |
US6834356B1 (en) | 2000-02-15 | 2004-12-21 | International Business Machines Corporation | Functional clock generation controlled by JTAG extensions |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3806717A (en) * | 1972-12-21 | 1974-04-23 | Gte Automatic Electric Lab Inc | Method and means for simultaneously testing counter check circuits |
US3838264A (en) * | 1970-11-25 | 1974-09-24 | P Maker | Apparatus for, and method of, checking the contents of a computer store |
US3899665A (en) * | 1974-01-18 | 1975-08-12 | Gte Automatic Electric Lab Inc | Timing error detection circuit |
US4084262A (en) * | 1976-05-28 | 1978-04-11 | Westinghouse Electric Corporation | Digital monitor having memory readout by the monitored system |
US4319355A (en) * | 1979-12-28 | 1982-03-09 | Compagnia Internationale Pour L'informatique | Method of and apparatus for testing a memory matrix control character |
US4326290A (en) * | 1979-10-16 | 1982-04-20 | Burroughs Corporation | Means and methods for monitoring the storage states of a memory and other storage devices in a digital data processor |
US4385385A (en) * | 1980-01-09 | 1983-05-24 | Compagnie Industrie le des Telecommunications Cit-Alcatel | Circuit for monitoring a digital signal generator |
US4528665A (en) * | 1983-05-04 | 1985-07-09 | Sperry Corporation | Gray code counter with error detector in a memory system |
US4531213A (en) * | 1982-03-03 | 1985-07-23 | Sperry Corporation | Memory through checking system with comparison of data word parity before and after ECC processing |
-
1989
- 1989-05-18 US US07/353,414 patent/USRE33461E/en not_active Expired - Lifetime
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3838264A (en) * | 1970-11-25 | 1974-09-24 | P Maker | Apparatus for, and method of, checking the contents of a computer store |
US3806717A (en) * | 1972-12-21 | 1974-04-23 | Gte Automatic Electric Lab Inc | Method and means for simultaneously testing counter check circuits |
US3899665A (en) * | 1974-01-18 | 1975-08-12 | Gte Automatic Electric Lab Inc | Timing error detection circuit |
US4084262A (en) * | 1976-05-28 | 1978-04-11 | Westinghouse Electric Corporation | Digital monitor having memory readout by the monitored system |
US4326290A (en) * | 1979-10-16 | 1982-04-20 | Burroughs Corporation | Means and methods for monitoring the storage states of a memory and other storage devices in a digital data processor |
US4319355A (en) * | 1979-12-28 | 1982-03-09 | Compagnia Internationale Pour L'informatique | Method of and apparatus for testing a memory matrix control character |
US4385385A (en) * | 1980-01-09 | 1983-05-24 | Compagnie Industrie le des Telecommunications Cit-Alcatel | Circuit for monitoring a digital signal generator |
US4531213A (en) * | 1982-03-03 | 1985-07-23 | Sperry Corporation | Memory through checking system with comparison of data word parity before and after ECC processing |
US4528665A (en) * | 1983-05-04 | 1985-07-09 | Sperry Corporation | Gray code counter with error detector in a memory system |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5704033A (en) * | 1994-10-07 | 1997-12-30 | Lg Semicon Co., Ltd. | Apparatus and method for testing a program memory for a one-chip microcomputer |
US6834356B1 (en) | 2000-02-15 | 2004-12-21 | International Business Machines Corporation | Functional clock generation controlled by JTAG extensions |
US6728649B2 (en) | 2002-02-01 | 2004-04-27 | Adtran, Inc. | Method and apparatus for removing digital glitches |
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