USRE30187E  Plural channel error correcting apparatus and methods  Google Patents
Plural channel error correcting apparatus and methods Download PDFInfo
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 USRE30187E USRE30187E US05771042 US77104277A USRE30187E US RE30187 E USRE30187 E US RE30187E US 05771042 US05771042 US 05771042 US 77104277 A US77104277 A US 77104277A US RE30187 E USRE30187 E US RE30187E
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 G11—INFORMATION STORAGE
 G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
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Abstract
Description
REFERENCE TO OTHER .[.PATENTS.]. .Iadd.PATENT DOCUMENTS .Iaddend.
This is a continuationinpart of Ser. No. 306,975, filed Nov. 15, 1972, now abandoned.
Hinz, Jr. U.S. Pat. No. 3,639,900 shows using pointers for error correction purpose and a readback system which may employ the present invention. .Iadd.
U.S. Pat. No. 3,508,194 shows construction of a modulo two adder usable in the present invention. .Iaddend.
This invention relates to an error correction system for a multichannel parallel information handling system and, more particularly, to plural channel error correction using signal quality pointers and correcting signals from fewer than such plurality of channels without such quality pointers.
In data handling systems, information is encoded for error detection and correction purposes by adding redundant bits to the data message in such a way that the total message can be decoded with an economical apparatus to faithfully supply the original information even when plural first errors occur in such message. Parallel data arrangements, that is, arrangements where the information is contained in parallel bytes arranged within a block of data, are used in computers and are well known, especially in multichannel recording apparatus. U.S. Pat. No. 3,629,824, filed Feb. 12, 1970, discloses encoding and decoding apparatus in which the redundant or check bits are associated with the data in a crossbyte or crosstrack direction. This patent sets forth a code capable of correcting one or more errors within one byte of data having a given number of bits. The data is divided into a plurality of fixedsized signal sets each consisting of k bytes of data (each byte having b bits), plus two check bytes, each of b bits. The decoder recovers the data without error when not more than a single byte of the received message is in error no matter how many bits may be in error in the single byte. Copending U.S. application, Ser. No. 99,490, filed Dec. 18, 1970, and now U.S. Pat. No. 3,697,948, utilizes the aboveidentified code, but extends the capabilities thereof by combining therewith pointer signals which extend the error correcting capability of the arrangement to two bytes in error regardless of the number of bits in error in each byte. These systems require two channels for the two additional check bytes needed for error correction, respectively. As the density of the information along the tracks or channels has increased, a faster, more reliable, simpler, but powerful, error correcting scheme is required which utilizes only one additional track for check bits.
In onehalf inch magnetic tape systems, it is highly desirable that tape be readable in both directions of transport. Usually, the tape is recorded only when transported in a first direction, arbitrarily defined as forward. A tape recorder should read in the forward and backward directions. When this fact is coupled with error detection and correction requirements, it is apparent that error codes should be operable for both directions of data transfer. Since the bit sequences are unalike in such transfers, many error detection and correction schemes require the data be accumulated before performing the error functions. For controlling costs and enhancing data throughput, it is desirable to perform error encoding and syndrome generation during readback on a serial basisthat is, perform calculations concurrently with data transfer rather than wait for all data transfers to be completed.
Accordingly, it is a main object of the present invention to provide error correcting systems and methods in which information signals are encoded in the crosstrack (vertical) direction as well as the tracklength (horizontal) direction and decoded so that the error correction is selectively applied along a selected track or channel.
It is another object of the present invention to provide plural channel error correction which requires only one channel for check bits in a parallel multichannel information system.
It is a further object of the present invention to provide error correction which utilizes a minimum redundancy to obtain correction of signals from plural tracks in error with signal quality pointers and at least one such track in error without such signal quality pointers.
It is a main feature to provide orthogonally symmetrical error detection and correction. Another feature is to employ plural independent error codes with interaction means simultaneously using both code redundancies to effect one error correction action with a capability equal to the sum of the error correction code individual capabilities.
Briefly, the invention contemplates error correcting apparatus for simultaneously correcting plural channels in error in a parallel channel information system wherein the information signals are encoded for error correction purposes in a cross channel (byte or vertical) direction as well as in the channel or horizontal direction. The encoded information signals are decoded so as to provide error correction in the channel direction in any single channel in error or in a number of channels in error which are indicated as being in error. Error correction apparatus is constructed in accordance with a matrix for both vertical and horizontal directions having a selected orthogonal symmetry. This symmetry is chosen to enable check bit generation along one dimension and correction along an orthogonal dimension.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawing.
FIG. 1 is a schematic representation showing eight data channels or tracks and a parity track, such as found on onehalf inch tape.
FIG. 2 is a schematic topological representation of the data format on the tracks in the system showing the check bits along the vertical or crosstrack direction and the vertical parity bits on the separate independent track or channel.
FIG. 3 is a schematic representation of the layout of the bytes of data in the crosstrack direction for a 9track tape system.
FIG. 4 shows the parity check matrix H for encoding of the data in the crosstrack direction.
FIG. 5 is a schematic representation of the 9track system showing the data arranged in the longitudinal or tracklength direction.
FIG. 6 shows the parity check matrix H for decoding and error correction in the tracklength direction.
FIG. 7 is a block diagram of the encoder.
FIG. 8 is a schematic representation showing the shift register mechanization for the encoding of the information.
FIG. 9 is a schematic diagram of the byte parity generator shown in block form in FIG. 7.
FIG. 10 is a schematic block diagram of the decoder and error corrector.
FIG. 11 is a schematic block diagram showing a feedback shift register for decoding.
FIG. 11a is a schematic block diagram showing the T^{7} multiplier of FIG. 11 and the T^{7} matrix indicating the various connections of the multiplier.
FIG. 12 is a schematic block diagram showing the shift register SR3 for decoding.
FIG. 13 is a schematic block diagram showing the details of the N indicator shown in FIG. 10.
FIG. 14 is a diagram showing the layout of the FIGS. 14a, 14b, and 14c which form the error track parameters generator.
FIG. 14a is a schematic block diagram showing the details of the generation of the I indicators.
FIG. 14b is a schematic block diagram showing the i parameter as a binary number.
FIG. 14c is a schematic block diagram showing the generation of the ji indicators.
FIG. 15 is a schematic diagram showing the error pattern generator of FIG. 10.
FIG. 15a is a schematic block diagram of the M_{3} multiplier and the M_{3} matrix indicating the connections of the multiplier.
FIG. 16 is a schematic block diagram of the ring counter shown in block form in FIG. 10.
FIG. 17 is a schematic block diagram of the code pointer generator shown in block form in FIG. 10.
FIG. 18 is a schematic block diagram showing the error corrector block of FIG. 10 in more detail.
In operation, information in the system is fed in parallel form to an error correction residue encoder wherein check and parity bits are sequentially generated for information signal sets referred to as bytes. These parity and check bit signals are supplied with the information signals such that the information signals can be error corrected. The present invention, via its orthogonal symmetry, enables calculation of check bits and syndromes using signals grouped in a socalled vertical direction and employs signals derived from such calculated signals to correct signals aligned in an orthogonal or socalled horizontal dimension. The invention also permits socalled backward error correction capability.
The standard way of recording binary data on onehalf inch tapes is a 9track format diagrammatically shown in FIG. 1. One of the tracks P or track 8 is reserved to record "parity" over the other eight tracks, one parity bit for one byte recorded with one bit in each of the eight tracks. Such parity bit is known as the vertical redundancy check (VRC) bit as set forth in U.S. Pats. Nos. 3,508,194, 3,508,195, and 3,508,196. Each byte consisting of eight information bits and the parity bit is simultaneously recorded with one bit in each of the nine tracks and is read back and reassembled as bytes in accordance with Floros U.S. Pat. No. Re. 25,527. This data format has evolved over many years of wide use of magnetic record tapes. To correct one track in error, the socalled CRC system referred to above points to the track in error to enable error correction based on parity. This system only allowed correction of one track in one block of recorded signals. The present invention enables correction of all tracks provided no more than two tracks are in error at a given instant. Modifications of the invention may alter the number of correctable tracks in error.
In designing new products, compatibility with the existing recorded tapes is one of the prime considerations in order that the tapes recorded on different machines can be freely interchanged. Bit density in the direction of motion of the tape in much greater than track density. Because of selfclocking aspects in reproducing recorded signals, one errorcausing phenomenon results in the following signals in the same track to be in error, referred to as a burst of errors. Such errors are mainly caused by defects in the magnetic media and separation of tape from transducer resulting in a loss of synchronization or skew information in the readback circuits. The erroneous tracks are often indicated by loss of signals in the read amplifiers or change in phase between a clocking signal and the readback signal. This invention enables correction of these types of errors simultaneously occurring in plural channels.
In the invention, the error correcting signal set topology for recorded or transmitted code words is in the geometric or time form of a block or rectangle conceptually with two orthogonal sides having check and parity bits, as shown in FIG. 2. The byte vectors are enumerated from C, the check byte, through B_{7}, the first data byte. The track vectors are enumerated Z_{0} through P. Those bits represented by the small rectangles, lying within the heavy line box, form an orthogonally symmetrical signal set portion; while track vector P lies outside such portion, but is used therewith to enable multiple track corrections with optimal redundancy. The orthogonally symmetrical portion enables interrelationship of check byte C with any data bit 01 . . . 77 by calculations performed on a byte serial basis (B_{1} . . . B_{7} or B_{7} . . . B_{1}), on a track serial basis (Z_{0} . . . Z_{7} or Z_{7} . . . Z_{0}), or simultaneously; i.e., in the latter, all data bits are buffered and an array calculator ascertains byte C. In applying the principle of orthogonal symmetry to error correction apparatus and method in a preferred mode, the orthogonal symmetrical redundancy or check byte C is generated in a byte serial calculation, the error syndromes on a byte serial basis, and the error pattern on a track basis. The error pattern calculation may include consideration of the parity check portion P.
The track correction is obtained by correcting the clusters of errors along the tracks in error. It is well known that the error correcting codes for symbols from GF(2^{b})b is a positive integer and GF means Galois Fieldthe Galois Field of 2^{b} elements, can be used for corrections of clusters of badjacent binary symbols. In the badjacent codes, each check symbol in GF(2^{b}) is replaced by b binary check digits; and each information symbol in GF(2^{b}), likewise, is replaced by b binary information digits. In such known systems, the encoding and decoding operations are performed on these bit clusters of b binary digits; thus obtaining badjacent correction corresponding to the correction of a symbol in GF(2^{b}). Applying such error detecting and correcting systems to multitrack digital recorders requires the selection of bit clusters along the respective tracks. This arrangement is selected because of the abovementioned error mode in such recorders. As a result, all data signals in one group of signals being error detected and corrected must be accumulated and stored before any error control activity is initiated.
Because of orthogonal symmetry, this invention avoids this restriction of symbols in GF(2^{b}) being in such trackoriented clusters of b binary digits of information or check bits. Accordingly, the code words are not describable in terms of the symbols in GF(2^{b}). An advantage of avoiding symbols from GF(2^{b}) is that binary check bits are no longer required to be track clustered for representation of the check symbols in GF(2^{b}). Instead, each binary check bit is independently placed in the message. This property is advantageously used in the present invention to mix the binary check digits and the information digits in correctable orthogonally symmetrical clusters. Mixing the information and check bits as described also allows enhanced error correction in a tape system which is compatible with abovementioned existing tape systems. More specifically, in a preferred form of the invention, doubletrack correction is provided wherein only one separate track is reserved solely for check bits rather than two tracks, as required in the known prior art using the Galois Field approach. A single track correction may be provided when the parity track is dispensed with; and a single track pointer locates the track in error, i.e., there are but eight tracks used rather than nine. The disclosed apparatus is directly usable for such an operation by continuously activating the laterdescribed j=8 signal from FIG. 14c and always making the parity vector P=0. This action makes the parity track 8 appear to always be in error; hence, with one of the data tracks 07 being in error, the apparatus corrects that single track in the same manner that track i is corrected for the laterdescribed correction of two tracks in error, one of which is the parity track 8.
It will be appreciated by those skilled in the art that this invention can be applied to diverse information signal handling systems of varying capacities. The invention will, therefore, be described in terms of the known 9track magnetic tape recording system, such as taught by Hinz, Jr., supra.
The present invention employs orthogonal symmetry in check bit residue generation and utilization for enabling generation of such check bits by sequentially analyzing each byte of data, one bit to a channel, and then correcting several bits along each channel using the bytegenerated residue. To accomplish this end, the underlying parity check matrices for the byteoriented or vertical residue generation establish an identical databittocheckbit relationship as that established when the check bits are calculated either in the horizontal or track direction. The identicalness required in such databittocheckbit relationship is described later with joint reference to FIGS. 4 and 6. Such identicalness requires an orthogonally symmetrical operation, both in error check bit generation and utilization apparatus.
The term orthogonal symmetry pertains to the information and check bits independent of the vertical parity bits. As will become apparent, such orthogonal symmetry enables the check bits generated based upon the byte information signals B_{1} . . . B_{7} to correct along the track vectors Z_{0} . . . Z_{7} (independent of parity for one track and with parity for two tracks; i.e., one of the tracks in error is parity track 8 indicated by the laterdescribed j=8 signal). This feature arises from relating the generated check bits to the information bits by using the following two equations as a basis for generating and using the check bits, respectively. For correct information and check bits:
T.sup.0 C+T.sup.1 B.sub.1 +T.sub.2 B.sub.2 +T.sup.3 B.sub.3 +T.sup.4 B.sub.4 +T.sup.5 B.sub.5 +T.sup.6 B.sub.6 +T.sup.7 B.sub.7 .[.+0.]..Iadd.=0 .Iaddend. (A)
T.sup.0 Z.sub.0 +T.sup.1 Z.sub.1 +T.sup.2 Z.sub.2 +T.sup.3 Z.sub.3 +T.sup.4 Z.sub.4 +T.sup.5 Z.sub.5 +T.sup.6 Z.sub.6 +T.sup.7 Z.sub.7 .[.+0.]..Iadd.=0 .Iaddend. (B)
In the above two equations, B's are the information bytes across tracks 07; C is the check bit byte across tracks 07; Z's are the signals along tracks 07, respectively, within a given signal set, viz, in track 0, bit 0, of B_{1} . . . B_{7}, C, etc.; and the T's are matrix multipliers selected to accomplish such orthogonal symmetry and as set forth later.
The above two equations show that the serial matrix multiplication and modulo 2's summation of the terms equal the modulo 2 sums of matrix multiplication using the same matrices but multiplying with the information signals and single check bit signal value along the indicated tracks. With this equality, check byte C is generated based upon the bytes B_{0} . . . B_{7} ; while error correction is achievable along the tracks Z_{0} . . . Z_{7}.
In a best mode, the number of bytes B_{0} . . . B_{7}, plus C, equals the number of bits along each track Z_{0} . . . Z_{7} contained in such bytes. This yields a square arrayin 9track tape, an 8×8 bit array exhibiting the abovedefined orthogonal symmetry (see FIG. 2). The following discussion is directed at a particular application of the invention using parity bits in the ninth track P, no limitation thereto intended. Instead of parity, a cyclically generated parity bit field may be used. For error correction, the parity and check bit fields are interrelated in a novel manner as later described.
In a preferred and best mode form, the code words of the code of the present invention, mathematically, have rectangular or block format of vertical dimension n_{1} and horizontal dimension n_{2}, where n_{1} is greater than n_{2} as seen in FIG. 2. n_{1} and n_{2} are expressed in information bits, not geometric distances. Dimension n_{1} is across the plurality of channels. Therefore, according to the invention, a group of datarepresenting signals in a multichannel signal transfer system has a length in number of data bits along each and every channel less than the number of channels and greater than one. Usually, a number of datarepresenting signals greater than the number of channels is transferred in a given signal transfer operation. Accordingly, each such signal transfer consists of a plurality of such lengths of data bits and associated check bits are hereinafter described.
Remembering the orthogonal symmetry concept and that an additional channel is used for an ancillary parity check field, such n_{1} and n_{2} dimensions readily adapt as a format in multichannel record tapes. To obtain the optimal orthogonal symmetry in channels Z_{0} . . . Z_{7}, with but one additional parity track, n_{1} is one greater than n_{2}. If it is desired to provide additional error locating power, additional parity channels may be added, for example, using a Hamming code, to increase the correction power of the present invention. However, for optimum utilization of redundancy, n_{1} is one greater than n_{2}. Also, the inventive orthogonal symmetry for error correction codes may be applied without additional parity or other coding, but obtaining a lesser correcting power, unless additional orthogonally symmetrical redundancy is added.
The check bits are orthogonally located in the message block rectangle (nothing to do with the orthogonal symmetry referred to above). In 9track tape, the parity track is along the center of the tape; hence, the vertical check bits are central of dimension n_{1}, splitting the n_{1} extending check bits into two portions on the tape, as at P. From an error detection and correction view, within the concepts of the broader aspects of the independent placement of check bits, the arrangements are identical. The check bits along the shorter horizontal dimension n_{2} are parity check bits over the coordinate lines along the n_{1} dimension, corresponding to presentday parity track. In existing tape systems, the vertical redundancy check (VRC) or vertical parity bits are on a separate tape track called the parity track P (track 8). The remaining check bits along dimension n_{1} are based upon information bits in selected positions along the tracks or channels, as later set forth. For twotrack correction, the redundancy or number of check bits is minimized when n_{2} is the largest for a given n_{1}, i.e., n_{2} =n_{1} 1. This arrangement is the most square data field, hence, based on geometry, the fewest number of check bits per data bit. One system for the special case of n_{1} =9 for the standard 9track onehalf inch tape application will be discussed. Other arrangements may be employed, as will be set forth. The code for other values of n can be constructed in a similar manner.
The data format for a preferred form of the code of the present invention, herein identified as an optimal rectangular code (ORC), for 9track tapes is diagrammatically shown in FIG. 3. Each independent error correcting signal set has seven bytes of information respectively and arbitrarily denoted by B_{1}, B_{2}, B_{3}, B_{4}, B_{5}, B_{6}, and B_{7}. The reverse order of bytes may be used, and the check byte C may be placed anywhere in the signal set, as will be elaborated upon later. C denotes an orthogonally symmetrical crosstrack check byte computed from serially presented information bytes B_{1} . . . B_{7}. As used in the underlying mathematics, each of the information bytes, individually denoted by B_{1} (i=17) and the check byte C, are 8digit column vectors (vertical multibit elements in matrix arithmetic): ##EQU1## wherein B_{i} (0) is bit 0 of byte B_{i} and C(0) is bit 0 of byte C, etc. The vector P is the conventional VRC (vertical redundance check) represented similarly by an 8digit column vector in which bit component P(0) is the even parity bit of the byte C and the component even P(i) is the parity bit of byte B_{i} ; i=1, 2 . . . 7.
P(0)=C(0)⊕C(1) . . . ⊕C(7) (1E)
and
P(i)=B.sub.i (0)⊕B.sub.i (1) . . . ⊕B.sub.i (7) (2E)
For odd parity:
P(0)=C(0)⊕C(1)⊕ . . . ⊕C(7) (10)
and
P(i)=B.sub.i (0)⊕B.sub.i (1)⊕ . . . ⊕B.sub.i (7)(2E)
For odd parity:
P(0)=C(0)⊕C(1)⊕ . . . ⊕C(7) (10)
and
P(i)=B.sub.i (0)⊕B.sub.i (1)⊕ . . . ⊕B.sub.i (7)(20)
for
i=1,2 . . . 7
where ⊕ denotes modulo 2 sum; P(0), P(i) is the modulo 2 sum; and P(0) and P(i) is the complement of the modulo 2 sum.
The check byte C is computed from the information bytes B_{1}, B_{2}, . . . B_{7} using the following matrix equation:
C=TB.sub.1 ⊕T.sup.2 B.sub.2 ⊕T.sup.3 B.sub.3 ⊕ . . . ⊕T.sup.7 B.sub.7 (3a)
where T is the companion matrix of an irreducible binary polynominal g(x) of degree 8 and T^{i} represents the i^{th} power of the matrix T. Let g(x) be given by:
g(x)=g.sub.0 +g.sub.1 x+g.sub.2 x.sup.2 + . . . g.sub.7 x.sup.7 +g.sub.8 x.sup.8 (3b)
where:
g.sub.0 =g.sub.8 =1
and g_{1} is either zero or one for i=1, 2, . . . 7.
The generalized companion matrix T of the polynomial g(x) degree 8 is defined as: ##EQU2## The check byte C can be generated by means of a feedback shift register, ExclusiveOR circuit array, programmed machine (preferably microcoded), and the like. A shift register implementation is described as the most economical for a given data rate. For lower data rates, a programmed machine is more economical, while for higher data rates, ExclusiveOR circuit arrays may be required. The above equations define the rules for encoding the message. These rules can be specified by the conventional means of a parity check matrix H. For this purpose, we characterize the matrices T^{i} in terms of the elememts of the Galois Field GF(2^{8}).
Let α be the element of the GF(2^{8}) representing the residue class (x) modulo g(x)an α occurs for each column of matrix T in (4a). Referring to (3a), g(x) is made equal to zero. To obtain reside classes, modulo g(x), the most significant term g_{8} x^{8} is made equal to the sum of the other terms. In any calculation, when term g_{8} x^{8} appears, the other terms are substituted for such most significant term. In practice, such action is accomplished in a linear feedback shift register and the like. Multiplication in GF(2^{8}) is defined by the polynomial multiplication of the residue classes modulo g(x). Hence, the element α^{i} for any i represents the residue class (x^{i}) modulo g(x). Therefore, any element α^{i} can be expressed as an 8digit column vector of the binary coefficients of the polynomial x^{i} modulo g(x). For example, for g(x)=1+x^{3} +x^{4} +x^{5} +x^{8}, the α^{i} 's are respectively represented by the column vectors as described below and relate to the matrices T as shown in FIGS. 4 and 6.
Matrices for an error correction apparatus consist of α column vectors; T^{0} =α^{0} . . . α^{7} ; T^{1} =α^{1} . . . α^{8}, etc. (FIGS. 4 and 6). Hence, a set of α column vectors is selected to constitute the matrices T^{0} . . . T^{n} for establishing error code generating and error detecting and correcting apparatus. For orthogonal symmetry, the α column vectors are established as later described with respect to FIGS. 4 and 6. In one preferred apparatus, there are 15 unique α column vectors corresponding to an 8bit redundancy or check byte. In this particular apparatus, the column vectors α^{0} . . . α^{7} have but one term equal to 1, i.e., α^{1} has a 1 in the i^{th} position, corresponding to the check bit position as follows: ##EQU3## where the 0, 1 columns represent a column vector. Each bit has its own equation; otherwise, simultaneous equations rather than separate equations.
For one code exhibiting orthogonal symmetry, as later explained, one set of α^{8} . . . α^{17} is: ##EQU4##
The selected α column vectors constituting the matrices T are:
T.sup.0 =α.sup.0 . . . α.sup.7
T.sup.1 =α.sup.1 . . . α.sup.8
T.sup.2 =α.sup.2 . . . α.sup.9
T.sup.3 =α.sup.3 . . . α.sup.10
T.sup.4 =α.sup.4 . . . α.sup.11
T.sup.5 =α.sup.5 . . . α.sup.12
T.sup.6 =α.sup.6 . . . α.sup.13
T.sup.7 =α.sup.7 . . . α.sup.14
hence, yielding eight unique matrices as shown in FIGS. 4 and 6. The column vectors α^{15} and α^{16} are not used.
The aboveselected column vectors α^{0} . . . α^{14} place check byte C as byte 0 in the error correcting signal set, see FIG. 3; and the relationship between the data bytes B_{1} . . . B_{7}, C and α column vectors as shown in FIGS. 4 and 6. Any T^{i} can replace T^{0} in the first byte position, each selection altering the mathematical placement of check byte C with respect to the data bytes and also altering the participation of a given data bit in the check byte redundancy. The illustrated check byte C placement is effected by selecting the first or leftmost α column vector of T^{n} =T^{0}, where n is the cycle length of g(x). To place check byte C in second position (byte B_{1} position), such first α column vector in T^{n1} is α^{n1} yielding the following T matrices:
T.sup.n1 =T.sup.14 =[α.sup.14,α.sup.0, α.sup.1 . . . α.sup. 6 ]
T.sup.n =T.sup.0 =[α.sup.0 . . . α.sup.7 ]
T.sup.1 =[α.sup.1 . . . α.sup.8 ]
T.sup.2 =[α.sup.2 . . . α.sup.9 ]
T.sup.3 =[α.sup.3 . . . α.sup.10 ]
T.sup.4 =[α.sup.4 . . . α.sup.11 ]
T.sup.5 =[α.sup.5 . . . α.sup.12 ]
T.sup.6 =[α.sup.6 . . . α.sup.13 ]
where α^{15} =α^{0}.
In general, to put check byte C (first) in byte position "k"(k=07), the matrix T^{nk} is selected as the first matrix while maintaining orthogonal symmetry. In a sequence of error correcting signal sets, the byte C placement may process.
The above αcolumnvectortomatrixT relationships yield a separate and independent EXCLUSIVEOR equation for each of the eight check bits in check byte C. Such selection reduces hardware complexity, hence, is desirable from a cost view. Such separate and independent equations are not necessary. Check byte C can be associated with the data bits by other than the identity matrix I_{d} ; this selection may result in interaction between the check bits yielding simultaneous interdependent equations rather than independent equations for each check bit. That is, a given check bit equation may include a second check bit along with a set of data bits in its EXCLUSIVEOR equation.
An example of such an arrangement using α^{2} . . . α^{16} set forth above is:
______________________________________Matrix α's Byte______________________________________T.sup.2 = α.sup.1 . . . α.sup.9 CT.sup.3 = α.sup.3 . . . α.sup.10 1T.sup.4 = α.sup.4 . . . α.sup.11 2T.sup.5 = α.sup.5 . . . α.sup.12 3T.sup.6 = α.sup.6 . . . α.sup.13 4T.sup.7 = α.sup.7 . . . α.sup.14 5T.sup.8 = α.sup.8 . . . α.sup.15 6T.sup.9 = α.sup.9 . . . α.sup.16 7______________________________________
Since α^{8} and α^{9} column vectors have more than a single "1", interaction among the check bits results. The mathematical placement of check byte C can be altered as previously alluded to. Orthogonal symmetry is maintainable. For all of the above matrices, the column vectors or field elements α^{i} are a cyclic subgroup with cycle length n where 8≦n<2^{8} and n is the exponent of g(x) (n=15 in the illustrated preferred apparatus). Using the above notation, the companion matrix T for any matrix as set forth in (4) can be written as:
T=[α.sup.1 α.sup.2 α.sup.3 . . . α.sup.8 ](5)
In (4a ), α is the leftmost column vector, α^{2} the one to the immediate right, etc., and α^{8} is the rightmost column vector. Any 8digit column vector: ##EQU5## wherein (0) . . . (7) correspond to bits from g_{0}. . . g_{7}, respectively. This column vector represents the residue class {β(0)+β(1)x+ . . . +β(7)x^{7} }modulo g(x) and hence is an element of GF(2^{8}). It can be shown that the matrix multiplication Tβ corresponds to the multiplication of the field elements α and β. In particular:
T α.sup.i =α.sup.i+1 (6a)
Using equations (5) and (6a), we can write:
T.sup.2 =T[α.sup.1 α.sup.2 . . . α.sup.8 ](6b)
=[Tα.sup.1 Tα.sup.2 . . . Tα.sup.8 ]=[α.sup.2 α.sup.3 . . . α.sup.9 ] (6c)
and in general for any positive integer i:
T.sup.i =[α.sup.i α.sup.i+1 . . .α.sup.i+7 ](7)
If cycle length n of a cyclic subgroup is the exponent of the polynomial g(x), then T^{n} is the identity matrix I_{d}, also written as T^{0}. "d" is the degree of such identity matrix. One property of such an exponent n is that it is the least positive number for which:
T.sup.n =T.sup.0 =I.sub.d
One parity check matrix H can be constructed using equations (1), (2), (3a), and (7) and as presented in FIG. 4.
It will be appreciated that α^{i} (for any integer) is an 8digit binary column vector. All the other blank spaces in the H matrix are 0's. The upper row represents the parity relation (EXCLUSIVEOR equation) between parity vector P and bytes C, B_{1} B_{7}, each "1" signifying terms in the parity equations. The parity 1_{d} matrix on the righthand portion of the upper row shows that each parity bit in the P vector is parity on the bytes C, B_{1} . . . B_{7}, respectively. In the lower row, the box under byte C is the identity matrix I_{d} showing the relationship between check byte C with bytes B_{1} . . . B_{7}. Under B_{1} is matrix T^{1}, B_{2} is T^{2}, etc. Element α^{9} under B_{2} is α^{8} under B_{1} shifted (multiplied) by T one place in a linear feedback shift register. Later, numerical examples will more fully illustrate T^{0} . . . T^{7}. One arbitrary relationship of CB_{7} to tape signals is shown in FIG. 3. The actual binary values of check byte C are determined by EXCLUSIVEOR relationship of B_{1} B_{7} and T^{1} T^{7}.
Before showing identicalness (orthogonal symmetry) between the matrices of FIGS. 4 and 6, error modes and data manipulations for error control are discussed.
The most common errors in tapes are burst errors in a given track. A burst error affects every track byte in a fixed bit position i where i is the lowest number of the track in error, 07. The parity track P is not included in the matrix multiplication. The respective collections of eight bits, C(i), B_{1} (i), . . . B_{7} (i), in such tracks are denoted by Z_{i}, such as Z_{0}, Z_{1}, z_{2}, Z_{3}, Z_{4}, Z_{5}, Z_{6}, Z_{7}, shown in FIG. 6. The 8bit row or horizontal vector Z_{i} is located in track i and hence consists of the bits C(i), B_{1} (i), B_{2} (i), . . . B_{7} (i) of the bytes C, B_{1}, B_{2}, . . . B_{7}, respectively. In order to facilitate error correction for burst errors along the horizontal or track direction, the parity check error correcting equations are expressed in terms of the Z_{i} and P horizontal vectors rather than as vertical vectors used in the residue calculation. This can be done be rearranging the columns (CB_{7}) of the parity check matrix of FIG. 4 to correspond to the Z_{i} vectors (track vectors) shown in FIG. 6. Such a partitioned matrix corresponding to a vector Z_{i} has the form:
[I.sub.8 /α.sup.i α.sup.1+1 . . . α.sup.1+7 ]
where I_{8} is the identity matrix degree 8. The parity check equations written from the H matrix of FIG. 6 are:
Z.sub.0 ⊕Z.sub.1 ⊕Z.sub.2 ⊕Z.sub.3 ⊕Z.sub.4 ⊕Z.sub.5 ⊕Z.sub.6 ⊕Z.sub.7 ⊕P=φ (8)
and:
T.sup.0 Z.sub.0 ⊕T.sup.1 Z.sub.1 ⊕T.sup.2 Z.sub.2 ⊕T.sub.3 Z.sub.3 ⊕T.sup.4 Z.sub.4 ⊕T.sup.5 Z.sub.5 ⊕T.sup.6 Z.sub.6 ⊕T.sup.7 Z.sub.7 =φ (9)
where 0 is an 8digit columnvector with all zeroes.
FIGS. 4 and 6 show two parity check matrices for the FIG. 2 illustrated signal set. The FIG. 4 check matrix is byte oriented, while the FIG. 6 check matrix is track oriented. It will be shown that for each data bit in B_{1} . . . B_{7} there is a given relationship to C; the same relationship exists for the same data bit when calculations are track oriented as shown in FIG. 6. This is orthogonal symmetry.
Take any data bit from FIG. 2 and examine same in both FIGS. 4 and 6; the identicalness of its relationship to the error correcting redundancy becomes apparent. Bit 54 (B_{4} (5)) in FIG. 4 is in byte B_{4} at bit position 5. In matrix T^{4}, the fifth column vector is α^{8}. Vector α^{8} (fifth column from left in T^{4}) relates bit 5 to C. In FIG. 6, bit 54 is Z_{5} (4). This bit is in the column for α^{8} (fourth column from left in T^{5}) and relates to C in the same manner as in FIG. 4 check matrix. A complete examination will show the above analysis for all data bits.
The above orthogonally symmetrical relationship is also established by noting the relationship of the α column vectors in FIGS. 4 and 6. In FIG. 4, byte B_{2} has its bits associated with check byte C via α^{2} . . . α^{9}, respectively. FIG. 6, byte B_{2} is associated with the third row of 1's from the top in the upper portion, i.e., the third bit position of each track vector Z_{0} . . . Z_{7}. Accordingly, in FIG. 6, the third α column vector in each matrix T^{0} . . . T^{7} is similarly associated with byte B_{2}, which yields α^{2} . . . α^{9}, respectively, in T^{0} . . . T^{7}. The conclusion is that each data bit in B_{2} relates to check byte C in the same manner whether parity check matrix H of FIG. 4 or 6 (byte or track oriented) is used. Such is orthogonal symmetry. The same analysis follows for all bits in B_{1} . . . B_{7} with respect to C.
A corollary is that each bit in byte C is related to a set of bits in an identical manner by both check matrices. Take bit 2C. In FIG. 4, bit C(2) relates to α^{2} in I_{d} :
C(2)=B.sub.1 (1)⊕B.sub.2 (0)⊕B.sub.3 (7)⊕B.sub.4 (6)⊕B.sub.5 (5)⊕B.sub.6 (4)⊕B.sub.7 (3)⊕B.sub.6 (7)⊕B.sub.7 (6)⊕B.sub.7 (7);
noting that bit 0 is in Z_{0}, 1 in Z_{1}, etc. In the FIG. 1 notation:
C(2)=11⊕02⊕73⊕64⊕55⊕46⊕37⊕76⊕67⊕77
For g(x)=1+x^{3} +x^{4} +x^{5} +x^{6} only; α^{2}, α^{10}, α^{13}, and α^{14} contain a 1 in the third (bit 2) position.
In FIG. 6, C(2) is aligned with T^{2}, not I_{d} (T^{0}):
C(2)=Z.sub.0 (2)⊕Z.sub.1 (1)⊕Z.sub.3 (7)⊕Z.sub.4 (6)⊕Z.sub.5 (5)⊕Z.sub.6 (4)⊕Z.sub.7 (3)⊕Z.sub.6 (7)⊕Z.sub.7 (6)⊕Z.sub.7 (7).
Since C is byte 0, the first bit in each track Z is in B_{1}, etc., as noted at the righthand margin of FIG. 6. In the FIG. 2 notation:
C(2)=02⊕11⊕37⊕46⊕55⊕64⊕73⊕67⊕76⊕77.
Since, in modulo 2 addition, the order of terms does not alter the answer, the checkbittodatabit relationships are orthogonally symmetrical for check bit C(2). Such symmetry for C(0) is shown in FIG. 2 as the hatched bit signals; i.e.,:
C(0)=0C⊕71⊕62⊕53⊕44⊕35⊕26⊕17⊕74⊕65⊕56⊕47⊕75⊕66.
In a similar manner, C(1) symmetry is shown below using the FIG. 3 geometry and the corresponding α column vectors.
______________________________________ 01      *              27      36      45      54   57   63   66 67  72   75 76 77______________________________________ where * is the check bit.
The line of symmetry is between upper left and lower right corners of the array, also as shown in FIG. 2. Using the same geometry, such symmetry is shown for all check bits.
______________________________________For C(2):   02       11       *               37       46       55       64   67    73   76 77For C(3):    03       12     17  21     26  *     35       44       53   57   62    66 67  71    75 76 For C(4):     04       13    17   22    26 16  31    35 36  *    44 45  47    53 54  56 57   62 63  65 66   71 72  74 75  For C(5):      45       34   17    23   26 27   32   35 36 37  41   44 45 46 47 *   53 54 55 56    62 63 64 65    71 72 73 74   77For C(6):       06       15       24   27    33   36 37   42   45 46 47  51   54 55 56 57 *   63 64 65 66    72 73 74 75  For C(7):        07       16       25       34   37    43   46 47   52   55 56 57  61   64 65 66 67 *   73 74 75 76 ______________________________________
From the above charts, it is seen that each check bit * is in a diagonal line of bits mathematically orthogonal to the line of symmetry and that all data bits are either in such line or in parallel lines all to one side (below, as shown) of the line including the check bit. For C(0) the transverse diagonal is the single check bit.
Examination of the above charts shows that shifting the matrices T^{0} T^{7} and hence shifting byte C from the lefthand column to other columns changes the bit pattern geometry, hence, changes the relationship between error mode and the error correction.
Based upon the above discussion and FIGS. 4 and 6, the following two fundamental theorems are promulgated.
Any error pattern in any one vector along the horizontal dimension (along a record track from the Z_{1} vectors) is detectable and correctabale.
Proof
A syndrome generated from any single track error pattern is a 16digit binary vector formed by the linear combination of the columns of the H matrix (FIG. 6) corresponding to the digit positions in error. Let S_{1} and S_{2} denote the two parts of the syndrome corresponding to the upper and lower eight rows of the FIG. 6 H matrix, respectively. Assuming only one vector is in error, S_{1} uniquely determines the data error pattern e. ##EQU6## wherein e_{1} is the error pattern; e(0) . . . e(7) are the error patterns for bytes 07. S_{1} is the same as the error pattern developed in prior onehalf inch tape recorders using the abovereferenced VRC systems. S_{2} is formed by the linear combination:
S.sub.2 =e(0)·α.sup.i ⊕e(1)·α.sup.i+1 ⊕ . . . e(7)·α.sup.i+7 (10)
if vector Z_{i}, i=0 . . . 7, is in error; S_{2} =0 if P is in error (S_{2} only relates to Z_{0} Z_{7}, not P).
Equation (10) can be written in terms of the algebra of GF(2^{8}) elements:
for i=07: S.sub.2 =α.sup.i ·e
for i=8: S.sub.2 =0
The theorem also shows that track i is not ambiguous by showing that for any track j not in error, i is unique. Let j denote a horizontal vector not in error (track not in error). That is, for j≠i, we have 0≠α^{i} ≠α^{j}. Also, e_{1} ≠. Hence, S_{2} uniquely determines i to rigorously identify the erroneous horizontal vector.
Theorem 2:
Any error patterns in any identified two vectors along the horizontal dimension (tracks) are correctable (note that tracks in error are detected or identified by operation of pointer apparatus independent the error correction apparatus). The two tracks in error are separately indicated, for example, by pointers in accordance with Hinz, Jr., supra. Such pointers indicate lowquality signal processing; hence, the probability of error is much greater than in those tracks without such pointers.
Proof:
Let e_{1} and e_{2} respectively denote two error patterns, respectively, for two tracks in error, herein identified as tracks i and j, respectively. Again, taking the linear combination of the corresponding columns of the FIG. 6 H matrix, we have:
for all cases: S.sub.1 =e.sub.1 ⊕e.sub.2 (11)
for j≠8: S.sub.2 =α.sup.i ·e.sub.1 ⊕α.sup.j ·e.sub.2 (12a)
for j=8: S.sub.2 =α.sup.i ·e.sub.1 (12b)
For j≠i, equations (11) and (12a) are independent equations in GF(2^{8}) yielding a unique solution. The error patterns are thus uniquely determined as:
for j≠8: e.sub.2 =(S.sub.1 ⊕α.sup.i S.sub.2)/(α.sup.0 ⊕α.sup.j1)
j=8: e.sub.2 2 =S.sub.1 ⊕α.sup.1 S.sub.2
for all cases: e.sub.1 =S.sub.1 ⊕e.sub.2
The multiplication and inverse of the vectors are the field operations in GF(2^{8}).
The coded message can be generated using any irreducible binary polynomial g(x). For the preferred tape embodiment, Table 1 gives the irreducible polynomials of degree 8 with their exponents. Choice of g(x) of degree 8 from this set could be arbitrary; however, for tape recorders, there is an advantage in choosing a selfreciprocal polynomial or one with a lower value of exponent. Such a choice facilitates error correction during backward read as desired for digital tape recorders. In Table 1, polynomial numbers 8 and 16 are selfreciprocal and have the lowest value of exponent. Reciprocal polynomial g(x)=x^{8} ·g(1/x) is also irreducible and has the same exponent as g(x).
Table 1______________________________________Irreducible Polynomials of Degree 8Polynomial Coefficients of the Polynomial ExponentNo. g.sub.0 g.sub.1 g.sub.2 g.sub.3 g.sub.4 g.sub.5 g.sub.6 g.sub.7 g.sub.8 g______________________________________1 1 0 0 0 1 1 1 0 1 2552 1 0 1 1 1 0 1 1 1 853 1 1 1 1 1 0 0 1 1 514 1 0 1 1 0 1 1 1 1 2555 1 1 0 1 1 1 1 0 1 856 1 1 1 1 0 0 1 1 1 2557 1 0 0 1 0 1 0 1 1 2558 1 1 1 0 1 0 1 1 1 179 1 0 1 1 0 0 1 0 1 25510 1 1 0 0 0 1 0 1 1 8511 1 0 1 1 0 0 0 1 1 25512 1 0 0 0 1 1 0 1 1 5113 1 0 0 1 1 1 1 1 1 25514 1 0 1 0 1 1 1 1 1 25515 1 1 1 0 0 0 0 1 1 25516 1 0 0 1 1 1 0 0 1 17______________________________________
The above irreducible polynomials, having an exponent value of 255 are primitive polynomials. When such primitive polynomials are selected, any one of the 255 α column vectors may be chosen for practicing the present invention. In the other nonprimitive polynomials, a number of α column vectors up to the exponent value may be used.
a. Encoding (Generations of check bit and parity check residues)From the prior theoretical description, check byte C is computed from the information bytes B_{1}, B_{2}, B_{3}, . . . B_{7} and the companion matrix, such as the one selected above, according to equation (3a). Such encoding is accomplished by means of linear feedback shift register 10 shown in FIGS. 7 and 8.
Shift register 10 contains eight binary storage elements or stages (0) . . . (7), one for each data track 07, with appropriate feedback connection 24 and modulo 2 summing networks 26 intermediate the binary storage elements. Under a timing control signal, the shift register synchronously shifts the contents of one stage to the next stage while simultaneously receiving a new input and feeding back as explained for FIG. 8. Shift register devices of this type are widely known and, given the feedback connections made in accordance with polynomial g(x), are easily constructed from available logic hardware in many different ways. Referring to FIG. 8, input data bytes B_{0} B_{7} are sequentially supplied to the shift register with the B_{7} byte being entered first. All bits 07 of each byte are simultaneously applied to modulo 2 summers 26 at the outputs of stages 07, respectively, of shift register 10. That is, each bit 0 of bytes B_{7} to B_{1} are sequentially applied to the modulo 2 summer 26 receiving the output of stage 0, etc. Therefore, at the input to each modulo 2 adder 26, there is the respective bit of each byte. Each of the modulo 2 adders 26 receive signals from feedback 24 and the indicated shift register stage. The output from each adder element 26 goes to the next shift register stage so that the contents are successively shifted from stage to stage through the entire shift register. The feedback connections are determined by the binary coefficients g_{0},g_{1}, . . . g_{7} of the polynomial g(x) where:
g(x)=1+g_{1} x+g_{2} x^{2} +g_{3} x^{3} +g_{4} x^{4} +g_{5} x^{5} +g_{6} x^{6} +g_{7} x^{7} +x^{8} A "one" coefficient (g_{i} =1) in the equation represents a closed or completed connection and a "zero" coefficient (g_{i} =0) represents an open or no connection. When g(x)=1+x^{3} +x^{4} +x^{5} +x^{8}, the feedback connections corresponding to g_{3} =g_{4} =g_{5} =1 or x^{3}, x^{4}, x^{5} are completed; the remaining are open or no connection as indicated in FIG. 8, respectively, by solid and dashed lines. At the end of seven cycles, each stage of the shift register contains one bit of vector C. With respect to equation (3a), each shifting operation corresponds to multiplying the shift register byte content vector by a companion matrix T; two shifts is a multiplication by T^{2}, etc. Input connections are such that the entering vector is premultiplied by the matrix T. Initially, this shift register 10, called SR1, contains all 0's. The information bytes B_{7}, B_{6}, B_{5}, B_{4}, B_{3}, B_{2}, and B_{1} are successively shifted into SR1 in that order. Thus at the end of seven shifts, SR1 contains the column vector:
TB.sub.1 ⊕T.sup.2 B.sub.2 ⊕T.sup.3 B.sub.3 ⊕ . . . ⊕T.sup.7 B.sub.7,
the check byte C. C is then gated out. The byte or vertical parity of B_{7}, B_{6}, . . . B_{1}, and C is computed as in previous systems and as diagrammatically shown in FIG. 9. The column vector or check byte C is calculated on a bytebybyte (vertical serial) basis, while correction is on a track (Z_{i}) or horizontal basis.Remember, the databittocheckbit relationship has an orthogonal symmetry to enable such transverse operations.
Check byte C contains the check bits resulting from implementing equation (3a) and is respectively associated with the information or data signals in a particular track or channel. Also, the parity bit signals for the crosstrack or vertical information signals are located in a separate track P.
b. Decoding (Error syndrome generation)Let Z_{0}, Z_{1}, Z_{2}, Z_{3}, Z_{4}, Z_{5}, Z_{6}, Z_{7}, and P denote the received signals of tracks 0P and corresponding to the original signals for each track Z_{0}, Z_{1}, . . . Z_{7}, and P, respectively, and hereinafter termed received track signals (see FIG. 5). It will be appreciated that some received signals may contain errors. The syndrome S_{1}, S_{2} can be generated by processing the received signals according to the checking rules expressed in track or horizontaloriented equations (8) and (9). The two received signal syndrome vectors S_{1} and S_{2} are:
S.sub.1 =Z.sub.0 ⊕Z.sub.1 ⊕Z.sub.2 ⊕Z.sub.3 ⊕Z.sub.4 ⊕Z.sub.5 ⊕Z.sub.6 ⊕Z.sub.7 ⊕P (13)
S.sub.2 =T.sup.0 Z.sub.0 ⊕T.sup.1 Z.sub.1 ⊕T.sup.2 Z.sub.2 ⊕T.sup.3 Z.sub.3 ⊕T.sup.4 Z.sub.4 ⊕T.sup.5 Z.sub. 5 ⊕T.sup.6 Z.sub.6 ⊕T.sup.7 Z.sub.7 (14a)
Calculation of S_{2} is based on track or horizontal vectors rather than byte or vertical vectors by transforming the FIG. 4 matrix to the illustrated FIG. 6 form. That is, syndrome generation is done by means for decoding the H matrix shown in FIG. 6. The transformation of the H matrices is important in that the syndrome S_{1}, S_{2} and eventual error patterns, e_{1}, e_{2}, are obtained by using the serial operable decoding H matrix so that the eventual error correction can be done on the Z horizontal vectors which are along the tape tracks, respectively. Furthermore, it allows serial encoding/decoding processes by means of crosstrack bytes (vertical) which require minimum buffering of the information signals, hence, reduce cost of implementation. Thus, the transformation of the H matrices saves considerable time and effort in encoding while providing correction of the several tracks in error.
According to this invention, S_{2} is obtained from the received byte vectors C, B_{1}, B_{2}, B_{3}, B_{4}, B_{5}, B_{6}, B_{7} using the equation:
S.sub.2 =C⊕T.sup.1 B.sub.1 ⊕T.sup.2 B.sub.2 ⊕T.sup.3 B.sub.3 ⊕T.sup.4 B.sub.4 ⊕T.sup.5 B.sub.5 ⊕T.sup.6 B.sub.6 ⊕T.sup.7 B.sub.7 (14b)
S_{2} can be generated using a circuit similar to that used in encoding, i.e., forward shifting B_{7} . . . C. However, a backward shifting register C to B_{7} saves decoding time in the error correction process and, accordingly, a method of generating S_{2} using a backward shifting register is preferred. For this purpose the syndrome equation is rewritten as:
S.sub.2 =T.sup.7 [T.sup.7 C]⊕T.sup.6 [T.sup.7 B.sub.1 ]⊕T.sup.5 [T.sup.7 B.sub.2 ]⊕ . . . ⊕[T.sup.7 B.sub.7 ] (14c)
wherein the negative exponents of each matrix T indicate backward shifting. The feedback connections are made according to g(x) Table 1); however, the shifting operation is backwards and corresponds to multiplying the shift register content vector by the matrix T^{1}, the inverse of the matrix T. The entering vector is premultiplied by the matrix T^{7} using a network of EXCLUSIVEOR gates (FIG. 11a). The backward shift register (SR2) is shown in FIG. 11. For backward shifting, the received bytes C, B_{1}, B_{2}, B_{3}, B_{4}, B_{5}, B_{6}, B_{7} are successively shifted into SR2 in that order.
In a practical embodiment, equation (14b) represents operation in a socalled forward direction wherein the byte order is B_{7}, B_{6}, B_{5}, B_{4}, B_{3}, B_{2}, B_{1}, C; while (14c) represents operation in a socalled backward direction wherein the byte order is C, B_{1}, B_{2}, B_{3}, B_{4}, B_{5}, B_{6}, B_{7}.
S_{i} is computed using an EXCLUSIVEOR network 46 feeding a shift register SR3 shown in FIG. 12.
c. Generation of Error Patterns (e_{1}, e_{2})If the received data is error free, then the check equations will be satisfied and the syndromes S_{1} and S_{2} will both be zero. A nonzero S_{1} or S_{2} indicates that the received data signals are not correct. In accordance with the error correction capability of the code, we assume that S_{1} =S_{2} =0 indicates no error and S_{1} or S_{2} ≠0 indicates one or two tracks in error (one or two horizontal burst errors). These erroneous tracks are designated by track numbers i (first and lower numbered track in error) and j (second and higher numbered track in error) and are identified by signal quality pointer signals Q_{i} and Q_{j} in the form of logical "1" for low quality, i.e., possible error conditions in tracks i and j, respectively. For convenience, it is arbitrarily required that i≦j where 0≦i≦7 and 0≦j≦8. The code is capable of determining the error patterns e_{1} and e_{2} (e_{2} =0 if i=J) corresponding to the tracks i and j, respectively.
The quality pointer signals are derived from the system in which the error correction is taking place. Of course, there are various means of generating "pointer" signals such as is set forth in Hinz, Jr., supra. In this application, the quality of the record/readback operations on a realtime basis is used as quality pointers to possible error conditions. The error correction apparatus also generates error pointers, hereinafter termed "code pointers".
The syndromes S_{1}, S_{2} generated from the encoded data bytes 07 and check byte C are functions of the errors therein. Such errors are represented by error patterns e_{1} and e_{2}, respectively, for track signal vectors Z_{i} and Z_{j} respectively from tracks i and j (when i=j, e_{2} =0, there is only one track in error). The received track signals Z_{i} =Z_{i}⊕ e_{1} and Z_{j} =Z_{j}⊕ e_{2}. The error correction in tracks i and j is accomplished by EXCLUSIVEOR'ing the error patterns with the received track singals in error to reconstruct correct track signals. From equations (8), (9), (13), and (14a), S_{1} and S_{2} have the algebraic equivalents:
S.sub.1 =e.sub.1 ⊕e.sub.2
for i≠j≠8:
S.sub.2 =T.sup.i e.sub.1 ⊕T.sup.j e.sub.2
for j=8; j=i:
S.sub.2 =T.sup.i e.sub.1
S_{2} =0 and j=8 or j=i indicates absence of any errors in the information tracks 07; hence, no data corrections are needed. Solving for e_{2} we get:
e.sub.2 =M.sub.ji [S.sub.1 ⊕T.sup.i S.sub.2 ] (15)
where:
for j≠i≠8:
M.sub.ji =[I.sub.d +T.sup.ji ].sup.1 (16a)
for j=i or j=8:
M.sub.ji =I.sub.d (16b)
wherein I_{d} is an identity matrix; M_{ji} is a matrix obtained from T^{ji} for ji=1, 2, 3, 4, 5, 6, 7.
Equation (15) can be realized in the following manner: T^{i} S_{2} is obtained by backward shifting SR2 i times with S_{2} as initial content. FIG. 15 shows the circuit which takes S_{1}, T^{i} S_{2}, and the number ji as input and computes e_{2}. The blocks M_{ji} for ji=1, 2, 3, 4, 5, 6, 7 are networks (FIG. 15) consisting of EXCLUSIVEOR gates realizing the matrices M_{ji} of equation (16a) as later set forth for one shift register implementation.
When only one track is in error (the case with i=j and e_{2} =0), the error correction apparatus generates its own code track in error pointer. Since the code pointer is rigorous, the quality pointers are ignored. The single track code pointer can be generated by solving equation (15) for the index (track) i with e_{2} =0 and ji=0, i.e., find i such that:
e.sub.2 =M.sub.0 (S.sub.1 ⊕T.sup.i S.sub.2)=0 (17)
This is done by counting the number of shifting operations (matrix multiplications) of SR2 (with S_{2} as initial content) while examining the output e_{2} of the circuit of FIG. 15 for e_{2} =0 or S_{1} =T^{i} S_{2} (from 17). If e_{2} does not equal zero after a maximum of seven shifts (ji≠1, 2, 3, 4, 5, 6, or 7) and also S_{2} ≠0, then there are two or more tracks in error. When S_{2} =0 and e_{2} ≠0, this indicates errors in the parity track 8 only.
d. Correction of Tracks in ErrorUsing the error pattern e_{2} and the syndrome S_{1}, the erroneous track signals Z_{i} and Z_{j} can now be corrected to produce the corrected track signals Z_{i} and Z_{j} as follows:
Z.sub.i =Z.sub.i ⊕S.sub.1 ⊕e.sub.2 (18)
Z.sub.j =.sub.Zj ⊕e.sub.2 (19)
Referring to FIG. 7, there is shown a block diagram of an encoder for the system. We will describe encoding for one set of input data bytes B_{17}, it being understood the encoding operation is repeated many times during recording one record block of signals. The encoder generates check byte C from the input serially received data or information bytes B_{1}, B_{2}, B_{3}, . . . B_{7} according to equation (3a) and also attaches a parity bit to each 8bit byte B_{1}, B_{2}, . . . B_{7} and C, yielding eight bytes of nine bits each for recording. The input data bytes are fed into data distributor 12 under control of a timing control signal. Data bytes B_{7}, B_{6}, B_{5}, . . . B_{1} go to linear feedback shift register SR1 10 from data distributor 12 in that order. The matrix multiplications as described in encoding are performed. From these data bytes, shift register SR1 10 serially generates check byte C. This check byte is then appended to the data bytes at the output of AND circuit 20. Simultaneous with the generation of the check byte C, the parity bit for each of the input data bytes B_{7}, B_{6}, etc., are generated; then the parity bit for check byte C is generated. The input data bytes B_{7}, B_{6}, . . . B_{1} are serially fed in that order to byte parity generator 14 via cable 13.
To sequence encoder operation for each set of input data bytes, at the start time of the encoder, t_{0}, binary counter 16 is preloaded to the value 7 and counts down in synchronism with the timing control signal to generate times t_{7} . . . t_{1}, respectively, for B_{17}. These timing control signals synchronously operate shift register 10 (SR1), and data distributor 12. When count 0 is reached, shift register 10 is inhibited from further shifting; while the contents of the shift register are supplied through AND circuit 20 after a unit timing cycle delay in delay 18. The details of the shift register SR1 for computing the check byte C are shown in FIG. 8. The feedback connections 24 are determined by the binary coefficients g_{1} . . . g_{7} of the selected polynomial g(x). The "1" coefficient implies a closed connection (solid lines), and the "0" coefficient implies an open connection (dashed lines). After shifting operations, each stage of the shift register SR1 contains one digit of vector C. The shifting operation corresponds to multiplying the shift register content vector by the companion matrix T (see FIG. 4). Input connections are such that the entering vector is premultiplied by matrix T. Such premultiplication consists of connecting the inputs B_{i} (0) to the input of one stage of the shift register and the successive B_{i} inputs to the next higher order stage i+1. This connection is an effective one shift or a multiply by Ta premultiply. Initially, of course, shift register SR1 contains all 0's or other reference value.
The byte parity generator 14 is shown in FIG. 9. B_{i} byte data bits (0) . . . (7) feed through the arrangement as well as being inputted to modulo 2 adder circuit 22, whose output represents the parity P.sub.(i) or P(C) of each input data byte. Accordingly, the output of the byte parity generator 14 is an 8bit data byte or check byte plus the appropriate parity bit. The encoded message is fed in the present example to a multitrack recorder.
After the message has been encoded and recorded, reproduced signals from the recorded tape (not shown) are transmitted in 9bit record byte serial form to decoder (FIG. 10). The readback byte sequence can be forward B_{7} . . . C or backward C . . . B_{7}. The decoding system is controlled by a timing control signal via binary control counter 60. At the beginning of each set of readback bytes, a start pulse (not shown) sets control counter 60 to its eighth state, signifying start decode time t_{0} (control counter counts once for each data byte). Generation of such a start pulse can be done in the same way presentday digital readback circuits generate a start read pulse, such as in Floros, supra. Each timing control signal may be such start read pulse with control counter 60 having a count of 8. In this regard, control 60 not only sequences the decoder, but also indicates the format of the readback bytes. Synchronization of such a format counter is shown by Irwin in U.S. Pat. No. 3,641,534.
The received message bytes B_{1}, B_{2}, B_{3}, B_{4}, B_{5}, B_{6}, B_{7} and C in either order are serially collected and deskewed in frame buffer 40 (Floros U.S. Pat. No. Re. 25,527). The corresponding signal quality pointers Q_{0}, Q_{1}, Q_{2}, . . . Q_{7}, and Q_{8} are inputted to N indicator 74 or may be deskewed along with the received message bytes.
In response to the quality pointer signals, N indicator 74 generates signals N_{1} and N_{3} respectively indicating less than two and more than two tracks in error. Both N_{1} and N_{3} signals are logical 0 when exactly two track quality pointers have value 1 indicating two tracks having low quality signals. The two pointers Q, in that case, are passed on uninhibited by N indicator 74 through OR circuit 76 to the error track parameters generator 54. Signal N_{3} =1 denotes a multitrack error indicating an uncorrectable error status. Signal N_{1} =1 indicates only one track in error. If the code pointer points to a track different than one pointed to by a single quality pointer, then such two pointers can be combined. This latter practice is dangerous as to data integrity and should be avoided unless a comprehensive error detection system is employed in conjunction with the present error correction apparatus. For example, the system of U.S. Pat. No. 3,508,196 may be so used.
The FIG. 10 decoder first computes the syndromes S_{1} and S_{2} serially by received bytes in shift registers SR3 and SR2, as later described with respect to FIGS. 11 and 12. The read or received encoded message bytes C, B_{1}, B_{2}, B_{3}, B_{4}, B_{5}, B_{6}, B_{7} are applied to the shift registers SR3 and SR2 in that order. As each 8bit byte (excludes parity) of the input or readback message is received at the shift registers SR3 and SR2, the registers are synchronously shifted by means of the timing control signal. Forwardbackward operations are described with respect to FIG. 11.
Binary control counter 60 zero count indicates all bytes C . . . B_{7} have been received. At this time, SR3 (FIG. 12) contains parity signals calculated based on received bytes. EXCLUSIVEOR's 42 combine the calculated parity signals with the received parity tracks signals B_{7} (8) . . . C(8) generating vertical syndrome vector S_{1} ready to be gated to error pattern generator 45 (FIG. 15). SR2 contains S_{2} which is further processed to produce T^{i} S_{2} after i shifts.
For an errorfree condition P=P yielding S_{1} =0; hence, no error indicating signals travel through AND's 65 to error pattern generator 45. Similarly, SR2 becomes all zeroes, as will become apparent, at the end of the checking calculation. With S_{2} =0, no error indicating signals are supplied to error pattern generator 45. As a result, code pointer generator 72 supplies no code pointer, allowing the received correct data signals to flow through error corrector 42 (FIG. 18) unchanged.
The case of less than two tracks in error indicated by the pointers Q is processed as follows. In this case, the N indicator produces the N_{1} signal as a logical 1 and inhibits the external Q pointer from going to the OR gate 76. Instead, the system proceeds to generate code pointers Q' by means of the ring counter 70 and code pointer generator 72. FIG. 10 apparatus solves equation (17):
e.sub.2 =M.sub.0 (S.sub.1 ⊕T.sup.i S.sub.2)=0
Track i is identified by shifting S_{2} i times (e_{2} =0). The ring counter 70 starts with a count 0 signal from counter 60. Simultaneously, the count 0 signal from counter 60 stops SR3 and, in conjunction with signal N_{1} through OR gate 102 and AND gate 101, opens the gates 64 and 65. At this time, the syndromes S_{1} and T^{0} S_{2} (i.e., S_{2}) appear at the output of gates 65 and 64, respectively. The timing control shifts the ring counter 70 and SR2 in synchronism each time increasing the count value in ring counter 70 and multiplying the contents of SR2 by T^{1}. Thus, successively, the count increases as 0, 1, 2, . . . and the contents of SR2 become T^{0} S_{2}, T^{1} S_{2}, T^{2} S_{2}, . . . Thus, in synchronism with the timing control signal, the output of the gate 64 changes successively as T^{0} S_{2}, T^{1} S_{2}, T^{2} S_{2}, . . . .
Of course, the presence of the N_{1} signal as a logical 1 produces the ji=0 pointer coming from the error parameter generator 54. This signal opens the direct path (of matrix M_{0} =Identity) in the error pattern generator 45. As a consequence, the output e_{2} of the error pattern generator 45 becomes successively S_{1} ⊕T^{0} S_{2}, S_{1} ⊕T^{1} S_{2}, S_{1} ⊕T^{2} S_{2}, etc., in synchronism with the timing signal. This signal e_{2} is inhibited from reaching the error corrector 42 in the gate 103 by the N_{1} signal. The e_{2} signal, however, is fed to the code pointer generator 72. The code pointer generator 72 continually checks for e_{2} =0. When that occurs, i.e., when e_{2} =S_{1} ⊕T^{8} S_{2} =0(S_{1} =T^{i} S_{2}) at the i^{th} timing control signal (i<8), the code pointer generator 72 produces the stop counter signal S which stops the ring counter 70 and the shift register SR2 by means of the AND gate 68. The ring counter count R, at this time, has value i and is indicated by signal r_{i}. This is passed on as code pointer Q' by means of the signals e_{2} =0 and N_{1} with logical I in the code pointer generator 72. The code pointer Q' is fed through the OR gate 76 to the error track parameters generator 54. If the ring counter 70 reaches count 8 before the code pointer generator 72 finds e_{2} with value 0, then the r_{8} signal from count R of ring counter 70 produces a stop counter S signal and stops any further action in SR2 and ring counter 20. The signal S_{2} =0 is generated by the error pattern generator 45 continually and is provided to the code pointer generator 72. If this signal, S_{2} =0, is logically 0 and the code pointer generator finds ring counter count R reaching the value 8 when e_{2} is not yet equal to 0, it is concluded that the error is in more than one track and, hence, is uncorrectable. This is indicated by the code pointer generator 72 providing a logical 1 value for the uncorrectable error signal E. If the signal S_{2} =0 has a logical 1 value, then the error is in the parity track. This is indicated by the code pointer generator providing the code pointer signal Q' with a logical 1 value for the signal Q'_{8}.
For twotrack correction, counter 60 is utilized while ring counter 70 is utilized when there is only one or no track in error. The N indicator 74 generates the signals N_{1} and N_{3} indicating respectively less than two and more than two tracks in error. Both N_{1} and N_{3} signals are logical 0 when exactly two track pointers have value 1 indicating two erroneous tracks. The pointer Q, in that case, are passed on uninhibited by the N indicator through the OR circuit 76 to the error track parameters generator 54. The error track parameters generator provides the binary number i for the binary counter 62 and the ji control signal for the error pattern generator 45. Thus, the binary counter 62 is already set to number i when the count 0 signal from counter 60 starts the count down of counter 62. The shift register SR2 is shifted simultaneously in synchronism with the timing control. At count 0 of counter 62, the last shift of shift register SR2 results in T^{i} S_{2} as the contents of SR2. The count 0 signal from counter 62 passes through OR circuit 102 and the AND circuit 101 to open the gates 64 and 65, thus passing S_{1} and T^{i} S_{2} on to the error pattern generator 45. The count 0 signal from counter 62 also stops any further action in counter 62 and shift register SR2.
The error pattern generator 45, on receiving S_{1} and T^{i} S_{2} as inputs produces the error pattern e_{2} using the control signal ji from the error track parameters generator 54. The syndrome S_{1} and error pattern e_{2} are passed on to the error corrector 42 through the open gates 65 and 103 to the error corrector.
The error corrector 42 utilizes the error pattern e_{2} and the syndrome S_{1} in making the error correction. The received data (with errors) is brought into the error corrector 42 from the frame buffer 40 and is provided to the various EXCLUSIVEOR gates in the error corrector 42 as Z_{i} vectors. The Z_{i} character denotation is explained in the frame formate of FIG. 5. The first track pointers I are brought from the error track parameters generator, and the track pointers Q' come through the OR gate 76 either from the code pointer generator 72 or from external means through the N indicator. With the aid of these pointers, the erroneous characters Z_{i} and Z_{j} are corrected to Z_{i} and Z_{j}. The other characters are passed on as corrected without making any change.
It will be appreciated that in the case of only one track error or no tracks in error, the corresponding values of e_{2} and S_{1} are 0 and, hence, the correction is properly effected by error corrector 42.
A better understanding of the operation of the error correction system may be obtained from the details of the various circuits forming the decoding system. The frame buffer and data distributor 40 can be of any known form capable of deskewing and distributing the information as required. It will be appreciated that the information input to the frame buffer and distributor 40 is in the form of 8bit bytes each with a parity bit. The crosstrack information is distributed to the shift registers SR3 and SR2 in parallel byte form as shown in FIG. 10 with the check byte first. A most basic storage and deskewing means would be a series of registers, one for each byte of information. The registers could be readable in the reverse direction as well as a direction orthogonal to the readin direction to obtain the Z_{i} information.
The shift register SR2 is shown in detail in FIG. 11. The information byte or check byte is shown as the input to a T^{7} multipler 44, the details of which are given in FIG. 11a. The bits of the byte after multiplication by T^{7} are utilized as inputs to modulo 2 adder circuits 20 associated with each of the storage stages of the shift register. The storage stages of the shift register are represented numerically by 07 corresponding to the 07 bits of the input byte. As was previously indicated in the theoretical discussion of the invention, feedback connections g_{1} through g_{7} are made in accordance with the value or 1 assigned to the term in the equation:
g(x)=1+g.sub.1 x+g.sub.2 x.sup.2 +g.sub.3 x.sup.3 +g.sub.4 x.sup.4 +g.sub.5 x.sup.5 +g.sub.6 x.sup.6 +g.sub.7 x.sup.7 +x.sup.8
If g_{i} in the equation equals 0, this indicates no feedback connection; while g_{i} =1 indicates a feedback connection. It should be appreciated that this is a backward shifting register. That is, the shift is from the last stage 7 towards the first stage 0; and the feedback 31 to the appropriate stages is from the 0 stage. Each shift of the shift register is essentially multiplying the input by T^{i}. The output of the shift register is essentially:
S.sub.2 =T.sup.7 [T.sup.7 C]⊕T.sup.6 [T.sup.7 B.sub.1 ]⊕T.sup.5 [T.sup.7 B.sub.2 ]⊕ . . . ⊕[T.sup.7 B.sub.7 ]
The T^{7} multiplier is shown in detail in FIG. 11a. The circuit consists of eight modulo 2 adders 34, the output of which represents the 0=7 bits of the T^{7} B byte. The input connections to the modulo 2 adder circuits 34 are made in accordance with the T^{7} matrix shown in FIG. 11a. For example, the first row of the matrix contains 1's in the 1, 4, 5, 6, and 7 positions representing that a corresponding connection should be made to the zero modulo 2 adder. Similarly, the 1's in the other rows of the matrix represent corresponding connections to the other modulo 2 adders as marked. This circuit multiplies the B byte inputs by T^{7}.
The FIG. 11 illustrated circuit is usable for both read forward and read backward operations of a digital tape recorder. The upper connections, identical to and labeled SR1, provide operations in read forward (FWD). The FWD signal activates modulo 2 adders 26 to modulo 2 add the quantity B_{i} to the other respective inputs to such circuits. The lower connections labeled SR2 include modulo 2 adders 30 enabled by the backward (BKWD) signal to operate as above described. Only SR1 or SR2 are enabled during a given time.
Generation of FWD and BKWD signals are from host CPU commands received by an I/O controller (not shown) respectively commanding read forward or backward.
FIG. 12 shows the shift register SR3 of the decoder. The input bytes C, B_{1}, B_{2}, . . . B_{7} are connected to a modulo 2 adder circuit 46 in that order. The output of the modulo 2 adder circuit 46 is fed into the last stage, stage 7, of the shift register, SR3 from whence it is successively shifted up until the parity for the indicated bytes is in the corresponding stages of the shift register SR3. The output of each stage of the shift register is the appropriate bit which taken together form the parity byte P.
FIG. 13 shows the N indicator circuit 74 which is capable of providing the control signals N_{1}, N_{3}, and the controlled pointers Q, N_{1} indicates that only one track pointer or none are on. The N_{3} signal indicates that more than two track pointers are on. The Q output represents the pointers Q_{0} through Q_{8}. The N_{1} output is obtained from an "only one or none" circuit 48 which has the pointers Q_{0} through Q_{8} as inputs thereto. The output N_{1} will only be obtained from the circuit when only one of the pointer inputs thereto is energized or none of them are energized. The output N_{3} is obtained from a "more than two" circuit 50 which is a threshold network capable of providing a logical 1 output when more than two of the inputs have logical 1's. The Q pointer output is obtained through AND gates 52 when N_{1} and N_{3} signals are not present.
FIG. 14 shows schematically the error track parameters generator 54 which generates the code pointers 1 identifying the first erroneous data track which is called the I^{th} track. It also generates the signals i as a binary number and the signals ji=0, 1, 2, 3, 4, 5, 6, 7 from the input pointer signals Q. FIG. 14 indicates that the logic circuits 14a, 14b, and 14c are included in the error track parameters generator 54 to obtain the abovenoted outputs.
Referring to FIG. 14a, there is shown the logic network connections for generating the I pointers I_{0} . . . I_{7} which identify the first erroneous data track called the I^{th} track. Combinations of the pointer signals Q_{0} . . . Q_{7} are utilized as inputs to AND circuits 56. The combinations are arranged in successively increasing order of one. For example, the grouping is Q_{0} and Q_{0}, Q_{1} followed by Q_{0}, Q_{1}, Q_{2}, etc. It should be observed that all of the inputs except the additional input in each of the combinations is inverted in a NOT circuit at the inputs to the respective AND circuits 56. It can be seen that as long as all the pointer inputs are zero, there will be no output from any of the AND circuits 56. However, the first nonzero pointer signal will be indicated by an output from its corresponding AND circuit 56. That is, the AND circuit 56 having that pointer as the additional pointer input.
FIG. 14b has as input the I indicators generated in FIG. 14a. The circuit generates the i parameter as a bbit binary number. The input combinations of the I indicators are determined according to columns in Table 2. The logic connections are determined in accordance with the 1's in the row in the columns of Table 2. For example, the column i(0) has a 1 in the 1, 3, 5, and 7 positions. Accordingly, the connections to the first OR circuit are the I_{1}, I_{3}, I_{5}, and I_{7} indicator inputs. These combinations of inputs are fed to OR circuits 58, the outputs of which form a binary number. For example, the i=5 indicated by I_{5} would have a 1 input to the first OR circuit 58 and a 1 input to the third OR circuit 58 giving an output of 101 which is the binary number 5.
Table 2______________________________________Parameter I as a Binary Number i as Binary Numberi Indicated By: i(2) i(1) i(0)______________________________________0 I.sub.0 0 0 01 I.sub.1 0 0 12 I.sub.2 0 1 03 I.sub.3 0 1 14 I.sub.4 1 0 05 I.sub.5 1 0 16 I.sub.6 1 1 07 I.sub.7 1 1 1______________________________________
FIG. 14c shows a logic circuit diagram which generates the ji values from the track pointers Q. This is accomplished by combining the Q pointers into pairs of inputs to separate AND circuits 80. The input paired arrangement of pointers has a first group of pairs separated by the value 1, while a second group of pairs is separated by the value 2. The third pair is separated by the value 3, the fourth pair by the value 4, etc. Each of these Q pointer pairs is fed to respective AND circuits 80 whose outputs form the input to appropriate OR circuits 82 to obtain the appropriate ji value. The ji=1 value is obtained from the first OR circuit 82a which has as inputs thereto the outputs from the first group of and circuits 80a which have the input pairs separated by one. Similarly, the other OR circuits 82b82f have connections thereto based on similar properties. For example, the second OR circuit 82 has an output value ji=2; while the third OR circuit 82c has a value ji= 3, etc. A single input pair N_{1} and P_{8} is provided to a separate OR circuit 83 which produces the output value ji=0 or j=8.
FIG. 15 shows the error pattern generator 45 generating the second error in the two track erasure error and the e_{2} and S_{2} =0 signals for the code pointer generator. The error pattern generator 45 has as one input S_{1} and as another input T^{i} S_{2}. Each of the bits of the vector inputs S_{1} and T^{i} S_{2} are utilized as inputs to each of the eight twoway ExclusiveOR gates 85. The output of each of these eight ExclusiveOR gates 85 is inputted to networks of ExclusiveOR gates M_{1} through M_{7}, there being no M network in the eightbranch circuit at the bottom of FIG. 15. The details of the network of ExclusiveOR gates M are shown in FIG. 15a with M_{3} being utilized as the example. The circuit actually performs a multiplication function on the B vector input. The multiplier matrix is obtained by solving the term M_{ji} =(I_{3} T^{ji})^{1}. The output of the multiplier consists of the input multiplied by M_{ji}. Each of the bits of the output byte from the multiplier M are inputted to a separate twoway AND gate 88. This means that each of the AND circuits 88 represented in FIG. 15 represent eight twoway AND gates. These gates have as another input the ji value associated with that AND gate. The output of the AND gates is fed to eightway OR gates 90, the output from which forms the eightdigit vector representing the error e_{2}. The signal S_{2} =0 is generated from the signals T^{1} S_{2} by means of an OR gate 91.
FIG. 15a shows the details of the M_{3} multiplier. The inputs to the modulo 2 adder circuits of the M_{3} multiplier are determined in accordance with the M_{3} matrix shown therein. The various matrices M_{1} through M_{7} corresponding to g(x)=1+x^{3} +x^{4} +x^{5} +x^{8} are given as follows: ##EQU7##
The connections of the various modulo 2 adder circuits 92 in the M_{3} multiplier or any of the multipliers is given by the appropriate row of the associated matrix. For example, in the M_{3} multiplier, the connections are made in accordance with the rows as follows: The 0^{th} row has a 1 in the 0, 1, 4, and 7 positions; thus the 0^{th} modulo 2 adder has a B_{0}, B_{1}, B_{4}, and B_{7} input. The other modulo 2 adder circuits have inputs corresponding to the 1 digits in the corresponding rows of the matrix. Note that the 4^{th} row has a 1 in only the 7^{th} position and hence, is shown by a direct connection.
Referring to FIG. 16, there is shown the details of the ring counter circuit 70 as shown in block form in FIG. 10. The ring counter 70 is shown having 08 stages with a feedback 94 from the eighth to the 0 stage. The output from each successive stage going to the next numerically higher state. The output from each of these stages is the corresponding count output r_{0} through r_{B}, which forms the count R as shown in FIG. 10. The output R is utilized as an input to the code pointer generator 72. The nine r pointers of the count R are inputted to nine separate AND gates 96 as can be seen in FIG. 17. As can be seen in FIG. 10, the other input to the code pointer generator 72 is N_{1} from the N indicator 74 and e_{2} and S_{2} =0 from the output of the error pattern generator 45. The e_{2} input is fed to an OR circuit 98 in FIG. 17 which produces an output when e_{2} ≠0. This output is fed to an AND circuit 99 along with N_{1}. The e_{2} ≠0 input to the AND circuit is NOTed so that when E_{2} =0 and N_{1} is present, the AND circuit 99 will produce a one output which is fed to the eightAND gates 96 and along with the appropriate R bit inputs produces as 1 output indicative of the particular code pointer Q' which indicates the single track in error. It will be appreciated that if e_{2} ≠0 at the output of the OR gate 98, a one will be produced which, through the NOT circuit, will be 0 at the AND gate 99; and, thus, the AND gate will produce no output. Therefore, the code pointers Q' will not be generated when e_{2} ≠0, except Q'_{8}. For Q'_{8}, the S_{2} =0 signal and the e_{2} ≠0 signal control the AND gate 96a indicating the 8^{th} track (parity track) is in error when S_{2} =0 and e_{2} ≠0 are both 1. The eighth count from the R count is fed to an OR circuit 97 which has as the other two inputs the N_{1} and e_{2} ≠0 output of the OR circuit 98. Each of these latter two inputs are NOTed so that if e_{2} =0, we get a 1 input to the OR circuit 97. Also, if N_{1} =0, we get a 1 input to the OR circuit 97. The r_{8} count will be an input to the OR circuit 97 also. Therefore, a 1 value of any of the value above three signals will produce the stop counter signal S. The eighth count r_{8} and the e_{2} ≠0 signals are input to the AND circuit 100. The output of this AND circuit 100 indicates that the error is uncorrectable when E has a 1 value.
Referring to FIG. 18, there is shown the error corrector circuit 42 which produces the corrected data bytes Z_{0},Z_{1}, . . . Z_{7} by combining the read data bytes Z_{0}, Z_{1}, . . . Z_{7}, the error pattern byte e_{2}, and the pointer signal I_{0} through I_{7} and Q'_{0} through Q'_{7}. The combining is done in accordance with the equations:
Z.sub.i =Z.sub.i ⊕S.sub.1 ⊕e.sub.2
Z.sub.j =Z.sub.j ⊕e.sub.2
It can be seen from these equations as shown in FIG. 10 that e_{2} is added modulo 2 to both the erroneous read bytes and S_{1} is added to the first erroneous read byte. This is accomplished by a set of eight modulo 2 summing networks 95 and two sets of eight AND gates 93 for each data byte Z_{0}, Z_{1}, Z_{2}, . . . Z_{7} as shown in FIG. 18. The first set of eight AND gates 93 acts like a normally closed gate controlled by the corresponding track pointer signal Q"_{i} ' and passes the e_{2} byte only when the associated Q" track pointer is on. The second set of nine AND gates 93 is controlled by the corresponding I signal and passes syndrome S_{1} only when the 1 pointer is on. The set of nine modulo 2 summing networks 92 combine the input signals Z_{i}, e_{2}, and S_{1} to produce the corrected byte Z_{i}.
As aforestated, magnetic tapes are read in both forward and backward directions. The error correction methods and apparatus of the present invention accommodate such requirements. When reading in the socalled forward direction, the decoder may be operated in the same mode as the encoder or backward shifted to save time. When readng the socalled backward direction, a backward shift with T^{7} premultiply, with an assymetrical polynomial symmetrically reversing feedback and input connections, etc. Also, all data signals in a signal set can be buffered with S_{1} and S_{2} being calculated on such buffered signals rather than serially.
Since the parity portion and orthogonally symmetrical portion are independent, in the event of catastrophic failures, two degraded modes of operation with correction are possibleone using parity only and a second using ORC only.
For a single track correction without the parity track, an independently generated track pointer is required. The described apparatus for twotrack correction is employed while forcing j=8; the single track in error i will be corrected as described for twotrack correction (using an independent pointer). Broadly, without the parity (or other code) inputs, the error correction capability is reduced and separate track identification is required; but the orthogonal symmetry still enables correction along a track based upon crosstrack byte calculations.
The invention may also be practiced with nonbinary notation, i.e., ternary, decimal, hexadecimal, etc., with equal advantage. The parity vector P may be a Hamming code, Fire code, and the like, or even a residue based upon a different polynominal.
While the invention has been particularly shown and described with reference to a preferred embomdiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (50)
C=TB.sub.1 ⊕T.sup.2 B.sub.2 ⊕T.sup.3 B.sub.3 ⊕ . . . ⊕T.sup.n.sbsp.2 B.sub.n.sbsb.2
S.sub.1 =P⊕P
S.sub.2 =C⊕T.sup.1 B.sub.1 ⊕T.sup.2 B.sub.2 ⊕ . . . ⊕T.sup.n.sbsp.2 B.sub.n.sbsb.2
e.sub.2 =M.sub.ji [S.sub.1 ⊕T.sup.1 S.sub.2 ]
M.sub.ji =[I.sub.d ⊕T.sup.ji ].sup.1
M.sub.ji =I.sub.d
m=1
n=7
ΣD.sub.n X.sup.m
m=7
n=1
1+B.sup.(ij).
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US5283791A (en) *  19880802  19940201  Cray Research Systems, Inc.  Error recovery method and apparatus for high performance disk drives 
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