USRE28923E  Error correction for two bytes in each code word in a multicode word system  Google Patents
Error correction for two bytes in each code word in a multicode word system Download PDFInfo
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 USRE28923E USRE28923E US05586766 US58676675A USRE28923E US RE28923 E USRE28923 E US RE28923E US 05586766 US05586766 US 05586766 US 58676675 A US58676675 A US 58676675A US RE28923 E USRE28923 E US RE28923E
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 G11—INFORMATION STORAGE
 G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
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 G11B20/1833—Error detection or correction; Testing, e.g. of dropouts by adding special lists or symbols to the coded information
Abstract
C.sub.1 =Z.sub.1 ⊕Z.sub.2 ⊕Z.sub.3 . . . ⊕Z.sub.k
C.sub.2 =T.sup.λZ.sub.1 ⊕T.sup.2 .sup.λ Z.sub.2 ⊕ . .
t(2.sup.f 1)/(2.sup.b 1)
S.sub.1 =C.sub.1 '⊕Z.sub.1 '⊕Z.sub.2 '⊕ . . . ⊕Z.sub.k '
S.sub.2 =C.sub.2 '⊕T.sup.λZ.sub.1 '⊕T.sup.2.sup.λ
Description
This invention relates to error detection and correction and, more particularly, to an improved error correcting code and system for detecting and correcting two .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.in a .[.multitrack.]. .Iadd.multicode word .Iaddend.data arrangement.
In data communication systems as well as computers, the information can be coded by adding redundant bits to the data message in such a way that the message can be decoded with a practical amount of apparatus to obtain the original information corrected in the event an error has been introduced. Parallel data arrangements, that is, arrangements where the information is contained in parallel bytes arranged in a block of data, are used in computers and are well known especially in multichannel recording apparatus. In copending application, Ser. No. 10,847, filed on Feb. 12, 1970, now U.S. Pat. No. 3,629,824, encoding and decoding apparatus are disclosed in which the redundant or check bits are associated with the data in a cross byte or cross track direction. This copending application sets forth a code capable of correcting one or more errors within a single, multiple bit byte of data. The data is divided into blocks which consists of k bytes of data (each of b bits), plus two check bytes, each of b bits. The decoder is effective in recovering the data without error when not more than a single byte of the received message is in error no matter how many bits may be in error in the single byte. In U.S. Pat. No. 3,319,223, filed Mar. 31, 1964, an error correcting code is disclosed in which the check characters generated from the information are added serially to the message block. The coding and decoding is implemented by means of shift register circuits. Another copending application, Ser. No. 99,490, filed Dec. 18, 1970, now U.S. Pat. No. 3,697,948 utilizes the aboveidentified code but extends the capabilities thereof by combining therewith pointer signals which extend the error correcting capability of the arrangement to two bytes in error regardless of the number of bits in error in each byte.
It is an object of the present invention to provide an improved error control system in parallel data systems such as computer tape recording systems and similar multichannel recording apparatus.
It is another object of the present invention to provide an error detection and correction system based on a new code which can be mechanized to provide two .[.channel.]. .Iadd.byte .Iaddend.correction .Iadd.in each code word .Iaddend.as well as detection of a large percentage of other errors without increasing the redundancy.
It is a further object of the present invention to provide an error detection and correction system in which larger size characters or bytes can be utilized without substantially increasing the encoding and decoding time and hardware.
It is a further object of the present invention to provide an error detection and correction code capable of providing correction for two tracks in error in a multichannel system when pointers for the tracks in error are provided.
It is another object of the present invention to provide an error detection and correction system in which all the necessary error correction functions can be realized by means of the same pair of shift registers.
The system for correcting two .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.in a .[.multitrack.]. .Iadd.multicode word .Iaddend.data arrangement consists of an encoding means for generating two check bytes C_{1} and C_{2} for the message data Z_{1}, Z_{2} ,...Z_{k} which is arranged in blocks having k bytes where each byte has f bits of data .[.extending in a cross track direction.]. where f = b × m where b and m are integers >1 and k is an integer 2<k<2^{b}. The check bytes are generated in accordance with the equations:
C.sub.1 = Z.sub.1 ⊕Z.sub.2 ⊕Z.sub.3...⊕Z.sub.k
and
C.sub.2 = T.sup.λZ.sub.1 ⊕T.sup.2 .sup.λ Z.sub.2 ⊕...⊕T.sup.k .sup.λ Z.sub.k
where T is the companion matrix of a binary primitive polynomial g(x) of degree f and λ is any integer given by the expression t(2^{f}  1)/(2^{b}  1) in which t is any positive integer prime to 2^{b}  1. The check bytes are appended to the incoming message data to obtain the encoded data for use in a .[.multitrack.]. .Iadd.multicode word .Iaddend.data system. The encoded data is decoded after usage (indicated by the ' symbol) by means of first and second shift registers with generate first and second syndromes from the encoded data in accordance with the equations:
S.sub.1 = C.sub.1 '+Z.sub.1 '⊕Z.sub.2 '⊕...Z.sub.k '
and
S.sub.2 = C.sub.2 '⊕T.sup.λ Z.sub.1 '⊕T.sup.2.sup.λ Z.sub.2 '⊕...⊕T.sup.k.sup.λ Z.sub.k '
Error pointers are provided which indicate the .[.tracks.]. .Iadd.bytes .Iaddend.in error .Iadd.in each code word .Iaddend.and means are provided which locate the bits in error in the .[.tracks.]. .Iadd.bytes .Iaddend.in error which can then be corrected in accordance with the errors indicated by the syndromes.
The foregoing and other objects, features and advantages of the invention, will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
FIG. 1 is a schematic diagram showing the data arrangement in a multitrack data system.
FIG. 2 shows a block diagram for carrying out the encoding of the present invention.
FIG. 3 is a schematic diagram showing the decoder arrangement .[.for.]. of the present invention.
FIG. 4 is a schematic diagram .[.showing the organization.]. of the first shift register of the pair of shift registers used for encoding and decoding in the error correction system of the invention.
FIG. 5 is a further schematic diagram showing the second shift register of the pair of shift registers.
FIG. 6 shows the error track parameter generator used in the decoder which includes the FIGS. 6a, 6b, 6c and 6d in its overall arrangement.
FIG. 6a is a schematic diagram showing the logic network connections for generating the i pointers.
FIG. 6b is a schematic logic diagram showing the generation of the Y parameter.
FIG. 6c is a schematic logic diagram showing the generation of the X parameter.
FIG. 6d is a schematic logic diagram for generating the control signals N_{0}, N_{1} and N_{3}.
FIG. 7 is a schematic diagram showing the error corrector circuit of the decoder.
FIG. 8 is a schematic logic diagram showing the arrangement for the detection of a large percentage of uncorrectable errors.
It will be appreciated by those skilled in the art that this invention can be applied to Information Handling Systems of various capacities. The invention will, therefore, be first described in algebraic terms which are applicable to any size system and subsequently in terms of a specific system.
Data is processed by the system in blocks consisting of k bytes, each byte having f bits of data where f = b × m. Here and throughout, b and m designate integers >1 and k is an integer 2<k<2^{b}. The values of f and k are to be considered invariant for a particular embodiment, but are variously chosen for embodiments of various capacities. A block of data is accordingly designated Z_{1}, Z_{2},...Z_{k} wherein Z_{1} represents the first byte in the block, Z_{2} the second byte, and so on to Z_{k} which represents the k^{th} and last byte. The encoder calculates from the block of incoming data two check bytes, (designated C_{1} and C_{2}) each of f bits and appends the check bytes to the k data bytes to generate the sent message of k+2 bytes. The data format arrangement is shown in FIG. 1. The check bytes are added in separate tracks, parallel and adjacent to the tracks carrying the data bytes. Each byte Z_{1} and C_{1} and C_{2} are f bit column vectors in the mathematical equations throughout and can be explicitly written as: ##EQU1## The check bytes C_{1} and C_{2} are computed from the information bytes Z_{1}, Z_{2},...Z_{k} using the following matrix equations:
C.sub.1 = Z.sub.1 ⊕Z.sub.2 ⊕...⊕Z.sub.k ( 1)
C.sub.2 = T.sup.λ Z.sub.1 ⊕T.sup.2 .sup.λ Z.sub.2 ⊕...⊕T.sup.k .sup.λ Z.sub.k ( 2)
wherein:
⊕ denotes the modulo 2 vector sum;
T is the companion matrix of a binary primitive polynomial g(x) of degree f which will be developed further as equation (3). For every f, there exists at least one primitive polynomial of degree f. For a list of primitive polynomials, see W. W. Petersen, Error Correcting Codes, M.I.T. Press, 1961.
T^{i} is the i^{th} power of the matrix T. (Computed using modulo 2 operations).
λ is any integer given by the expression:
t(2.sup. f  1)/(2^{b}  1) in which t is any positive integer prime to 2.sup. b  1. Since f = b × m, the above expression always results in a positive integer. The use of λ in this code has particular significance, which will become apparent from the discussion with respect to the preferred embodiment to follow.
In order to more clearly explain the invention, a specific value f = 8 has been chosen. The polynomial g(x) of degree 8 can be explicitly written as:
g(x)=g.sub.0 + g.sub.1 x g.sub.2 x.sup.2 +...g.sub.7 x.sup.7 + g.sub.8 x.sup.8
where:
g.sub.0 = g.sub.8  1 and g.sub.i is either 0 or 1 for:
i = 1,2,...7
The companion matrix T of the polynomial g(x) is defined as: ##EQU2##
As was mentioned previously in the Background of the Invention, copending application, Ser. No. 99,490, filed Dec. 18, 1970, now U.S. Pat. No. 3,697,948 discloses a multitrack error correction system having k data tracks and two check byte tracks. Two bdigit check bytes are generated from k bdigit information bytes where 2<k<2^{b}. It will be appreciated that in this prior art system, the byte size b can be increased. However, the encoding and decoding hardware increases considerably with the increase in size of the bytes participating in the computation. Accordingly, these prior art arrangements have attempted to keep the byte size as small as possible while still satisfying the relation 2<k<2^{b}.
There are a number of situations where an increase in the byte size participating in the code word computation is desirable. For example, in computer tape recording systems, dividing binary data tracks into 8bit bytes is preferred because of the 8bit byte organization of the main processor. Thus, an 8bit byte error correction arrangement would be preferred to the 4bit byte arrangement shown in the copending application.
The code generated in this invention is actually a shortened code which possesses an added capability of detecting a certain percentage of errors which cannot be corrected. The percentage R can be estimated as:
The full length is defined as 2^{b} +1 and the shortened length is defined as k+2, i.e., the maximum number of tracks on which the code can be used versus the actual number of tracks. For example, when k = 8, using a 4bit byte gives a detection capability estimated as 53 percent of the other errors as opposed to an estimated 97 percent with an 8bit byte arrangement.
Although the code generated in this invention is actually a shortened form of a longer code, the encoding and decoding apparatus required is equivalent to that required for the shortened code rather than the longer code. Apparatus is also described for encoding and decoding this special code by means of which two tracks in error can be corrected when track pointers are provided. The actual code generated as a result of this invention can best be described through an example using 8bit bytes. This arrangement will also be contrasted with the 4bit byte arrangement of the prior art so that the advantages thereof can better be appreciated. The binary form of the parity check matrix for the 4bit byte code in its full length is given by: ##EQU3## where O_{4} and I_{4} are 4 × 4 "zero" and "identity" matrices and T_{4} is the companion matrix of a degree 4 primitive polynomial. One such polynomial is 1 + x^{3} + x^{4}. Accordingly, T^{4} is given by: ##EQU4## Similarly, the parity check matrix for the 8bit byte code in its full length is given by: ##EQU5## where O_{8} and I_{8} are 8 × 8 "zero" and "identity" matrices and T_{8} is the companion matrix of the primitive polynomial 1 + x + x^{3} + x^{5} + x^{8}. ##EQU6## Note that T_{4} ^{i} are elements of the Galois Field GF(2^{4}) and T_{8} ^{i} are elements of the Galois Field GF(2^{8}). These elements have the properties that T_{4}, T_{4} ^{2},...,T_{4} ^{15} are all distinct and T_{4} ^{15} equals I_{4} and T_{8}, T_{8} ^{2},...,T_{8} ^{255} are all distinct and T_{8} ^{15} equals I_{8}. The Galois Field GF(2^{8}) contains a subfield which is isomorphic to GF(2^{4}). The elements of this subfield are given by:
T.sub.8 .sup.λ, T.sub.8.sup.2.sup.λ,...T.sub.8.sup.15.sup.λ
where:
λ = t(2.sup.8  1)/(2.sup.4  1)
for any t prime to (2^{4}  1). One such λ is 68. These subfield elements have the property:
T.sub.8 .sup.λ, T.sub.8.sup.2 .sup.λ,...T.sub.8.sup.15.sup.λ
are all distinct T_{8} ^{15}.sup.λ = I_{8}. Furthermore, T.sub. 8 ^{i} .sup.λ and T_{4} ^{i} possess a onetoone relationship in that the two sets are isomorphic in the "Sum" and "Product" operations of the corresponding Galois Field. Referring to the 8bit byte code given by the following parity check matrix: ##EQU7## It is apparent that this code possesses the same mathematical structure as that of the 4bit byte code given by the parity check matrix of equation (4). All the columns in the matrix of equation (8) have an equivalent column in the matrix of equation (6). For example, with:
λ = 68, T.sub.8.sup.5 .sup.λ = T.sub.8.sup.340 = T.sub.8.sup.255 . T.sub.8.sup.85 = T.sup.85
thus, it can be seen that the fifth column in equation (8) is equivalent to the 85th column in equation (6). It can be seen from the above, that the code constructed using the subfield elements T^{i}.sup.λ is a shortened form of the code given by equation (6). The code can be further shortened in the usual manner. For example, the 8track arrangement can be encoded using the parity check matrix: ##EQU8## Accordingly, for λ = 68, the T_{8} .sup.λ is given by: ##EQU9## The preferred embodiment of this invention will be illustrated using the code defined in matrix (9) in an 8track arrangement with 8bit bytes. Accordingly, the two check bytes C_{1} and C_{2} are computed from the information bytes Z_{1}, Z_{2}, Z_{3}, Z_{4}, Z_{5}, Z_{6} using the following equations:
C.sub.1 = I.sub.8 Z.sub.1 ⊕I.sub.8 Z.sub.2 ⊕...⊕I.sub.8 Z.sub.6 ( 11)
c.sub.2 = t.sub.8 .sup.λ z.sub.1 ⊕t.sub.8.sup.2 .sup.λ z.sub.2 ⊕...⊕t.sub.8.sup.6.sup.λ z.sub.6 ( 12)
after the message has been encoded and utilized at the recorder, the read message bytes are transmitted or conveyed to the decoder. The message is distributed by a read message distributor which sends the encoded message in parallel to a pair of shift registers SR1 and SR2. The decoder computes two expressions known as the syndrome S_{1} and S_{2} defined as:
S.sub.1 = C.sub.1 '⊕Z.sub.1 '⊕Z.sub.2 '⊕...⊕Z.sub.k '(13)
S.sub.2 = C.sub.2 '⊕T.sup.λ Z.sub.1 '⊕T.sup.2 .sup.λ Z.sub.2 '⊕...⊕T.sup.k .sup.λ Z.sub.k ' (14)
The received message byte Z_{1} ', Z_{2} ',...Z_{k} ', C_{1} ', C_{2} ' are the read message bytes corresponding to the recorded bytes Z_{1}, Z_{2},...Z_{k}, C_{1}, C_{2}, respectively. As was previously mentioned, there may be errors in up to two tracks causing errors in the corresponding bytes. These erroneous tracks are designated by track numbers i and j and are identified by pointer signals P_{i} and P.sub. j in the form of logical "1." For convenience, it is required that i ≦ j, 1 ≦ i ≦ k and 1 ≦ j ≦ k + 2. The case, where two indicated erroneous tracks are the check tracks, is ignored.
The "pointer" signals are derived from the system in which the error correction is taking place. Of course, there are various means of generating "pointer" signals such as is set forth in corresponding U.S. Pat. application, Ser. No. 40,836, filed May 26, 1970, entitled, "Enhanced Error Detection and Correction For Data Systems." In this application, the quality of the record/read back operations on a real times basis is used as pointers to possible error conditions.
The syndromes generated from the encoded data bytes and check bytes contain the error patterns. These error pattern bytes e_{i} and e_{j} in the bytes corresponding to the tracks i and j (when i = j, we assume ej = 0). S_{1} and S_{2} have the algebraic equivalent: ##EQU10## These expressions can be solved for e_{i} and e_{j} as follows: ##EQU11## wherein: ##EQU12## and:
y =  i modulo 2.sup.b  1 (20)
For each value ji, the values of parameter x and for each value of i, the parameter y are fixed. These parameters can be computed algebraically. For example, in the preferred embodiment where T.sup.λ = T_{8} ^{68} as given in equation (10), the values of x and y are tabulated in Tables 1 and 2.
TABLE 1.PARAMETER x______________________________________ ji= .sup.1 0 1 2 3 4 5 x= 0 3 6 11 12 5______________________________________
TABLE 2.PARAMETER y______________________________________ i= 1 2 3 4 5 6 y= 14 13 12 11 10 9______________________________________ 
Using the above computed values of x and y, the error pattern e_{j} is computed from the syndromes S_{1} and S_{2} according to equation (17). The erroneous bytes Z_{1} ' and Z_{j} ' can then be corrected using the error pattern e_{j} and the syndrome S_{1} to produce the corrected bytes Z_{1} and Z_{j} since: ##EQU13##
In summary, the decoding process consists of:
1. Computing the syndromes S_{1} and S_{2} from the received message bytes Z_{1} ', Z_{2} ',...Z_{k} ', C_{1} ', C_{2} ' according to equations (3) and (4).
2. Computing the error pattern e_{j} from the syndromes S_{1} and S_{2} according to equation (17) with proper values of parameters x and y from precalculated tables.
3. Correcting the erroneous bytes with the error pattern e_{j} and the syndrome S_{1} according to equations (21) and (22).
4. Detection of the uncorrectable errors according to the following:
4a. When more than two tracks are indicated as being in error, the code cannot provide reliable error correction.
4b. When two tracks are indicated as being in error, the error pattern bytes e_{i} and e_{j} have unique values.
4c. When exactly one track is indicated as being in error (the case where i is equal to j), then the error pattern byte e_{j} must be 0 in all bit positions. If the computed e_{j} is not 0 in all bit positions, then this is interpreted as detection of some other errors.
4d. When no track is indicated as being in error, then the syndromes S_{1} and S_{2} and, consequently, the error pattern bytes e_{i} e_{j} must be 0 in all bit positions. If not, this is interpreted as detection of errors.
Utilizing the previous example of 8bit bytes, it can be seen from FIG. 2, that the data Z_{1}, Z_{2},...Z_{k} in forms of blocks of equal size bytes is received at the input 9 of the encoder 10. The received data is distributed by a data distributor to shift registers SR1 and SR2. The distributor 12 applies the incoming data to these shift registers in parallel. The shift registers SR1, SR2 perform the computations previously described to generate the check bytes C_{1} and C_{2}. These check bytes are appended to the message data at the output 14 of the encoder 10. This encoded data is sent to the multitrack recorder or transmitter for utilization. FIGS. 4 and 5 show the shift registers SR1 and SR2, respectively. Each shift register contains 8 binary storage elements (0)...(7) with appropriate feedback connections and modulo 2 summing networks at each input stage. It is implied that with a time control signal, the shift register shifts the contents while simultaneously receiving the new input. Shift register devices of this type are widely known and given the feedback connection, it can be physically constructed from available logic hardware in many different ways.
Referring to FIG. 4, each input bit Z(0)...Z(7) of the 8bit byte is applied to a separate modulo 2 summing circuit 16 at the input to each of the eight separate shift register storage elements 18. The output 20 of each binary storage element 18 is fed back via a feedback connection 22 to the modulo 2 adding circuit 16 at the input thereto along the with new input.
In FIG. 5, each of the 8bits Z(0)...Z(7) of an 8bit byte are shown as inputs to the modulo 2 adder circuits 20  27 at the input to each storage element of the shift register. The outputs 30  37 of each of the binary storage elements (0)...(7) are connected to certain ones of the modulo 2 adder circuits 20  27 in accordance with the columns of the matrix T_{8} ^{68} which is given in equation (10). For example, the output 30 of the 0^{th} storage element is connected back to the modulo 2 adder circuits 21 and 24 at the inputs of the first and fourth stages of the shift register. These connections are made in accordance with the 0^{th} column of T_{8} ^{68} which has 1's in the first and fourth positions. The new 8bit vector input is entered into the register via the modulo 2 adding circuits 20  27 simultaneously with the feedback mentioned. If an 8digit byte X represents the present contents of shift register SR1 and shift register SR2 and Y representing the input is entered with a shifting operation; then the next contents in shift register SR1 is Y⊕X and in shift register SR2 is Y⊕T_{8} ^{68}. X.
The information is entered into the shift registers SR1 and SR2 in reverse order, that is, Z_{k} is entered first and Z_{1} is entered last. After the last byte Z_{1} has entered, the registers are shifted one more time with a 0 input.
The contents of shift register SR1 will be Z_{1} ⊕ Z_{2} ⊕ ...⊕ Z_{k} which represents the first check byte. The contents of shift register SR2 will be T.sup.λ Z_{1} ⊕ T^{2}.sup.λ Z_{2} ⊕...⊕ T^{k}.sup.λ Z_{k} which is the second check byte. At the start time of the encoder 10, t_{0}, the binary counter 40 is set to k + 1. The counter counts down in synchronism with the timing control signal. At count 0, the last shift of shift register SR1 and SR2 generates the respective check bytes. The count 0 signal obtained from the counter 40 closes the switches SW1 and SW2 after a unit time delay (during the next timing signal).
Referring to FIG. 3, the decoder 42 receives the encoded read or utilized message bytes Z_{1} ', Z_{2} ',...Z_{k} ', C_{1} ', C_{2} ' and the pointers P_{1}, P_{2} ,...P_{k}, P.sub. k_{+1}, P_{k} _{+2} which indicate the tracks in error. The decoder 42 computes from these inputs the corrected data bytes Z_{1}, Z_{2},...Z.sub. k or generates an uncorrectable error signal E. The symbol represents the corrected data.
The decoder 42 first computes the syndromes S_{1} and S_{2} in shift registers SR1 and SR2, as shown in FIGS. 4 and 5 from the read or received encoded message bytes Z_{1} ', Z_{2} ',...Z_{k} ', C_{1} ', C_{2} ' according to equations (3) and (4). The message bytes Z_{k} ', Z_{k} _{1} '...Z_{1} ' are applied to the shift registers SR1 and SR2 in that order by the read message distributor 44. Of course, the decoding is being performed to correct any errors that may have been introduced to the message as a result of the utilization thereof, either in the recorder or in the transmission with respect thereto. As each byte of the input message is received at the shift registers SR1 and SR2, the registers are simultaneously shifted by means of a time control signal. After the byte Z_{1} ' has entered, the byte C_{1} ' is entered into shift register SR1 and the byte C_{2} ' is entered into shift register SR2 while shifting the registers once. The contents of shift register SR1 is now C_{1} ' ⊕ Z_{1} ' ⊕ Z_{2} ' ⊕...⊕ Z_{k} ' which is the syndrome S_{1}. The contents of shift register SR2 is now C_{2} ' ⊕ T.sup.λ Z_{1} ' T^{2} .sup.λ Z_{2} ' ⊕...⊕ T^{k}.sup.λ Z_{k} ' which is the syndrome S_{2}. The syndrome generation is controlled by the timing control signal. The binary counter B_{1} is set to k + 1 at time t_{0} (starting time for the decoder) and counts down in synchronism with the timing control signals. At count 0, the last shift of shift registers SR1 and SR2 results in S_{1} as the contents of the shift register SR1 and S_{2} as the contents of shift register SR2.
The count 0 signal from the counter B_{1} starts counter B_{2} after a unit time delay, that is, with the next timing control signal. B_{2} is set to the binary value y at time t_{0}. Counter B_{2} counts down in synchronism with the timing control signal which continuously shifts registers SR1 and SR2 also. At the count 0, in the counter B_{2}, the switch SW1 is closed. This causes the contents of shift register SR1 which is S_{1} to enter shift register SR2. Accordingly, the contents of shift register SR2 is S_{1} ⊕T^{y}.sup.λ S_{2} and the contents of shift register SR1 remains S_{1}.
The count 0 signal generated by counter B_{2} initiates B_{3} after a unit time delay, that is, with the next timing control signal. Counter B_{3} is set to the binary value x at time t_{0}. Counter B_{3} counts down in synchronism with the timing control signal which continuously shifts registers SR1 and SR2. At the count 0 in the counter B_{3}, the last shift of SR1 and SR2 produces T^{x}.sup.λ (S_{1} ⊕ T^{y} .sup.λ S_{2}) as the contents of SR2 while the contents of shift registers SR1 remains S_{1}.
The count 0 signal from the counter B_{3} closes the switches SW2 and SW3 after a unit time delay (with the next timing control signal). The switch SW3 is also controlled by the pointer signal P_{k} _{+2} as described later in connection with the error corrector circuit.
FIG. 6 shows schematically the error track parameters generator 46 which generates the parameters x and y as binary numbers from the input pointer signals P_{1}, P_{2},...P_{k}, P_{k} _{+1}, P_{k} _{+2}. The error track parameters generator 46 also generates the new pointers I_{1}, I_{2},...I_{k} identifying the first erroneous data track which is called the Ith track. It also generates the signals N_{0}, N_{1}, N_{3}, indicating respectively, 0, 1 and more than 2 tracks in error. The error track parameters generator 46 of FIG. 6 indicates that the logic circuits 6a, 6b, 6c and 6d are included in order to obtain the abovenoted outputs.
Referring to FIG. 6a, there is shown, the logic network connections for generating the I pointers I_{1}...I_{6} which identifies the first erroneous data track called the Ith track. Combinations of the pointer signals P_{1} ...P_{6} are utilized as inputs to AND circuits 50. The combinations are arranged in successively increasing order of 1. For example, the grouping is P_{1}, then P_{1}, P_{2} followed by P_{1}, P_{2}, P_{3}, etc. It should be observed that all of the inputs except the additional input in each of the combinations is inverted in a NOT circuit at the inputs to the respective AND circuits 50. It can be seen that as long as all the pointer inputs are 0, there will be no output from any of the AND circuits. However, the first nonzero pointer signal will be indicated by an output from its corresponding AND circuit. That is, the AND circuit 50 having that pointer as the additional pointer input.
FIG. 6b has as inputs the I pointers generated in FIG. 6a. This circuit generates the y parameters as a bbit binary number y_{3}, y_{2}, y_{1}, y_{0}. The input combinations of the 1 pointers is determined according to Table 3. The logic connections can be determined by retabulating y as a bbit binary number with the corresponding I pointers as shown in Table 3.
Table 3. Parameter y as a binary member______________________________________ y as binary numberi Indicated by y y.sub.3 y.sub.2 y.sub.1 y.sub.0______________________________________1 I.sub.1 14 1 1 1 02 I.sub.2 13 1 1 0 13 I.sub.3 12 1 1 0 04 I.sub.4 11 1 0 1 15 I.sub.5 10 1 0 1 06 I.sub.6 9 1 0 0 1______________________________________
Therefore, the signals y_{3}, y_{2}, y_{1} and y_{0} are generated from I_{1}, I_{2},...I_{6}. The input I pointer signals are combined into three groups of three and then a group of all six. These are inputted to OR circuits 52 which produce the y parameter outputs. It will be appreciated that y_{3} is always a logical one when any of the I signals is logical 1. y_{2} is a logical 1 when I_{1} or I_{2} or I_{3} is a logical 1. y_{0} is a logical 1 when I_{2} or I_{4} or I_{6} is a logical 1.
FIG. 6c shows a logic circuit diagram which generates the x parameters as a bbit binary number x_{3}, x_{2}, x_{1}, x_{0} from the P pointers. Before the x parameter can be generated, the (ji) values must be generated from the track pointers P_{1}, P_{2},...P_{6}. This is accomplished by combining the P pointers into pairs of inputs to separate AND circuits 56. It can be seen that the input paired arrangement of pointers has the first group of pairs separated by the value 1, while the second group of pairs is separated by the value 2, the third group by the value 3, the fourth group by the value 4 and the last pair by the value 5. Each of these P pointer pairs is fed to respective AND circuits 56 whose outputs are inputted to appropriate OR circuits 58 to obtain the appropriate ji value. For example, ji = 1 is obtained from the OR circuit 58 connected to the AND circuits 56 having as inputs thereto the pairs separated by 1. Similarly, the other OR circuits 58 have connections thereto based on similar properties. For example, the second OR circuit 58 has an output value ji = 2, while the third has a value ji = 3 and the fourth has a value ji = 4. Each of the ji values are connected to the appropriate OR circuits 60. The connections for the associated functions are determined by means of Table 4 which is derived from Table 1. The procedure is similar to that in generating the connections for the previous parameter. The parameter x then is obtained as a bbit binary number with signals x_{3}, x_{2}, x_{1}, x_{0}.
Table 4. Parameter x as a binary number______________________________________ x as a binary numberji Function x x.sub.3 x.sub.2 x.sub.1 x______________________________________0 or j=7 N.sub.1 +P.sub.7 0 0 0 0 01 P.sub.1 P.sub.2 +P.sub.2 P.sub.3 +P.sub.3 P.sub.4 +P.sub.4 P.sub.5 +P.sub.5 P.sub.6 3 0 0 1 12 P.sub.1 P.sub.3 +P.sub.2 P.sub.4 +P.sub.3 P.sub.5 +P.sub.4 P.sub.6 6 0 1 1 03 P.sub.1 P.sub.4 +P.sub.2 P.sub.5 +P.sub.3 P.sub.6 11 1 0 1 14 P.sub.1 P.sub.5 +P.sub.2 P.sub.6 12 1 1 0 05 P.sub.1 P.sub.6 5 0 1 0 1______________________________________
Note that P_{k} _{+2} does not participate in the determination of the values ji. Also, ji = 0 or j = k+2 does not generate logical 1 on any of the x_{0}, x_{1}, x_{2}, x_{3} signal outputs.
FIG. 6d shows the circuit arrangement for generating the control signals N_{0}, N_{1} and N_{3}. N_{0} indicates that none of the track pointers P_{1}, P_{2} ,...P.sub. k_{+2} are on. N_{1} indicates only 1 is on. N_{3} indicates that more than two track pointers are on. The N_{0} signal is generated as an output from an AND circuit 62 having the 8 pointer signals P_{1}...P_{8} as inputs thereto. It can be seen that any one of the pointer inputs being on will cause no output from the AND circuit 62. Thus, the absence of N_{0} indicates that there is an energized track pointer. The N_{1} output is obtained from a `one and only one` circuit 64 which likewise has the pointers P_{1} through P_{8} as inputs thereto. The output N_{1} will only be obtained from circuit 64 when only one of the pointer inputs thereto is energized. The output N_{3} is obtained from a threshold network 66 which provides a logical one output when more than two of the inputs have logical 1's.
Referring to FIG. 7, there is shown the error corrector circuit 68 which produces the corrected data bytes Z_{1}, Z_{2} ,...Z_{k} by combining the read data bytes Z_{1} ', Z_{2} ' ,...Z_{k}, the error pattern byte e_{j} and the pointer signals I_{1},...I_{k} and P_{1}...P_{k}. The combining is done in accordance with the equations (21) and (22). These two equations are interpreted as follows.
If j = k + 2, i.e., the pointer P_{k} _{+2} is on, then e_{j} the output of SR2 should be inhibited. The inhibiting is done by AND gates (switch SW3) as shown in FIG. 3. Otherwise, e_{j} is added (modulo 2) to the erroneous read bytes and S_{1} is added to the first erroneous read byte. This is accomplished by a set of 8 modulo 2 summing networks 70 and 2 sets of 8 AND gates 72,74 for each data byte Z_{1} ', Z_{2} ', Z_{3} ', Z_{4} ', Z_{5} ', Z_{6} ' as shown in FIG. 7. The first set of 8 AND gates 72 acts like a normally closed gate controlled by the corresponding track pointer signal and passes the e_{j} byte only when that track pointer is on. The second set of 8 AND gates 74 are controlled by the corresponding I signal and pass syndrome S_{1} only when that I pointer is on. The set of 8 modulo 2 summing networks 70 combine the input signals Z_{i} ', e_{j} and S_{1} to produce the corrected byte Z_{i}.
Referring to FIG. 8, there is shown the uncorrectable error indicator logic circuit 80 for detection of a large percentage of uncorrectable errors. This circuit generates an error indicator signal E when one of the following happens:
1. N_{3} is on indicating more than two tracks are in error. This can be seen from the N_{3} input to the last OR circuit 81.
2. N_{1} is on indicating that only one track is in error and the e_{j}, the output of SR2, is not 0 in all bit positions. This is accomplished by having N_{1} and e_{j} ≠ 0 signals as inputs to an AND circuit 82, the output of which forms one of the inputs to the OR circuit 81. The e_{j} ≠ 0 signal is generated by an OR circuit 83 which receives all of the e_{j} bits as its input.
3. N_{0} is on indicating that no track is in error when e_{j}, the output of SR2, or S_{1}, the output of SR1, is not 0 in all bit positions. This is accomplished by deriving an S_{1} ≠ 0 signal from OR circuit 85 which has all the bits of S_{1} as inputs thereto. The S_{1} ≠ 0 signal is applied as an input to AND circuit 84 along with the N_{0} input. The AND circuit 84 output is connected to OR circuit 81. The e_{j} ≠ 0 signal and the N_{0} signal are connected as inputs to an AND circuit 86 whose output forms another input connection to OR circuit 81. Thus, any one of the inputs N_{0}, N_{1} and N_{3}, under the conditions enumerated above, produces an output signal E from OR circuit 81 indicating detection of uncorrectable errors.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (12)
C.sub.1 = Z.sub.1 ⊕Z.sub.2 ⊕Z.sub.3...⊕Z.sub.k
C.sub.2 = T.sup.λZ.sub.1 ⊕T.sup.2.sup.λ Z.sub.2 ⊕...⊕T.sup.k.sup.λ Z.sub.k
S.sub.1 = C.sub.1 '⊕Z.sub.1 '⊕Z.sub.2 '⊕...⊕Z.sub.k '
S.sub.2 = C.sub.2 '⊕T.sup.λ Z.sub.1 '⊕T.sup.2 .sup.λ Z.sub.2 '⊕...⊕T.sup.k .sup.λ Z.sub.k '
e.sub.j = T.sup.x.sup.λ [S.sub.1 ⊕T.sup.y .sup.λ S.sub.2 ].
C.sub.1 = Z.sub.1 ⊕Z.sub.2 ⊕Z.sub.3...⊕Z.sub.k
C.sub.2 = T.sup.λZ.sub.1 ⊕T.sup.2.sup.λ Z.sub.2 ⊕...⊕T.sup.k.sup.λ Z.sub.k
S.sub.1 = C.sub.1 '⊕Z.sub.1 '⊕Z.sub.2 '⊕...⊕Z.sub.k '
S.sub.2 = C.sub.2 '⊕T.sup.λZ.sub.1 '⊕T.sup.2.sup.λ Z.sub.2 '⊕...⊕T.sup.k.sup.λ Z.sub.k '
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Cited By (6)
Publication number  Priority date  Publication date  Assignee  Title 

WO1983002345A1 (en) *  19811230  19830707  Chen, ChinLong  Two bit per symbol sec/ded code 
US5218689A (en) *  19880816  19930608  Cray Research, Inc.  Single disk emulation interface for an array of asynchronously operating disk drives 
US5231638A (en) *  19890411  19930727  Fujitsu Limited  Error correction control apparatus 
US5255272A (en) *  19910225  19931019  Storage Technology Corporation  Predictive tape drive error correction apparatus 
US5283791A (en) *  19880802  19940201  Cray Research Systems, Inc.  Error recovery method and apparatus for high performance disk drives 
US5499251A (en) *  19900815  19960312  Televerket  Method of recovering lost bits in a digital transmission 
Citations (3)
Publication number  Priority date  Publication date  Assignee  Title 

US3588819A (en) *  19680918  19710628  Bell Telephone Labor Inc  Doublecharacter erasure correcting system 
US3629824A (en) *  19700212  19711221  Ibm  Apparatus for multipleerror correcting codes 
US3675200A (en) *  19701123  19720704  Ibm  System for expanded detection and correction of errors in parallel binary data produced by data tracks 
Patent Citations (3)
Publication number  Priority date  Publication date  Assignee  Title 

US3588819A (en) *  19680918  19710628  Bell Telephone Labor Inc  Doublecharacter erasure correcting system 
US3629824A (en) *  19700212  19711221  Ibm  Apparatus for multipleerror correcting codes 
US3675200A (en) *  19701123  19720704  Ibm  System for expanded detection and correction of errors in parallel binary data produced by data tracks 
Cited By (6)
Publication number  Priority date  Publication date  Assignee  Title 

WO1983002345A1 (en) *  19811230  19830707  Chen, ChinLong  Two bit per symbol sec/ded code 
US5283791A (en) *  19880802  19940201  Cray Research Systems, Inc.  Error recovery method and apparatus for high performance disk drives 
US5218689A (en) *  19880816  19930608  Cray Research, Inc.  Single disk emulation interface for an array of asynchronously operating disk drives 
US5231638A (en) *  19890411  19930727  Fujitsu Limited  Error correction control apparatus 
US5499251A (en) *  19900815  19960312  Televerket  Method of recovering lost bits in a digital transmission 
US5255272A (en) *  19910225  19931019  Storage Technology Corporation  Predictive tape drive error correction apparatus 
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