USD320755S - Intergrated circuit tester - Google Patents

Intergrated circuit tester Download PDF

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Publication number
USD320755S
USD320755S US07/296,185 US29618589F USD320755S US D320755 S USD320755 S US D320755S US 29618589 F US29618589 F US 29618589F US D320755 S USD320755 S US D320755S
Authority
US
United States
Prior art keywords
circuit tester
intergrated circuit
view
elevational view
intergrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/296,185
Inventor
Bjorn M. Dahlberg
Charles H. Schwar
Mauro V. Tegethoff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HILEVEL TECHNOLOGY Inc A CA CORP
Hilevel Technology Inc
Original Assignee
Hilevel Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hilevel Technology Inc filed Critical Hilevel Technology Inc
Priority to US07/296,185 priority Critical patent/USD320755S/en
Assigned to HILEVEL TECHNOLOGY, INC., A CA CORP. reassignment HILEVEL TECHNOLOGY, INC., A CA CORP. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: DAHLBERG, BJORN M., SCHWAR, CHARLES H., TEGETHOFF, MAURO V.
Application granted granted Critical
Publication of USD320755S publication Critical patent/USD320755S/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

FIG. 1 is a top, front and right side perspective view of a intergrated circuit tester showing our new design;
FIG. 2 is a top, front and right side perspective view, with the circuitry enclosure rotated 180 degrees;
FIG. 3 is a top plan view;
FIG. 4 is a right side elevational view;
FIG. 5 is a front elevational view;
FIG. 6 is a rear elevational view;
FIG. 7 is a top, front and right side perspective view of a second embodiment of our new design of FIGS. 1-6;
FIG. 8 is a top, front and right side perspective view, with the circuitry enclosure rotated 180 degrees;
FIG. 9 is a top plan view;
FIG. 10 is a right side elevational view, the left side elevational view being a mirror image;
FIG. 11 is a front elevational view;
FIG. 12 is a rear elevational view;
FIG. 13 is a top, front and right side perspective view of a third embodiment of our new design of FIGS. 1-6;
FIG. 14 is a top, front and right side perspective view, with the circuitry enclosure rotated 180 degrees;
FIG. 15 is a top plan view;
FIG. 16 is a right side elevational view, the left side elevational view being a mirror image;
FIG. 17 is a front elevational view; and
FIG. 18 is a rear elevational view thereof.

Claims (1)

  1. The ornamental design for a intergrated circuit tester, as shown and described.
US07/296,185 1989-01-11 1989-01-11 Intergrated circuit tester Expired - Lifetime USD320755S (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US07/296,185 USD320755S (en) 1989-01-11 1989-01-11 Intergrated circuit tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/296,185 USD320755S (en) 1989-01-11 1989-01-11 Intergrated circuit tester

Publications (1)

Publication Number Publication Date
USD320755S true USD320755S (en) 1991-10-15

Family

ID=70286509

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/296,185 Expired - Lifetime USD320755S (en) 1989-01-11 1989-01-11 Intergrated circuit tester

Country Status (1)

Country Link
US (1) USD320755S (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD977358S1 (en) * 2020-09-04 2023-02-07 Electronic Controls Company Sounder housing

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"VSLI Systems Design" publication dated Jun. 1988.
HILEVEL Technology, Inc. advertising brochure for TOPAZ-V.
HILEVEL Technology, Inc. news release dated Jun. 12, 1988.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD977358S1 (en) * 2020-09-04 2023-02-07 Electronic Controls Company Sounder housing

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