US9997471B2 - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
- Publication number
- US9997471B2 US9997471B2 US15/371,869 US201615371869A US9997471B2 US 9997471 B2 US9997471 B2 US 9997471B2 US 201615371869 A US201615371869 A US 201615371869A US 9997471 B2 US9997471 B2 US 9997471B2
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- redistribution layer
- semiconductor package
- chip
- package structure
- encapsulant
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title description 15
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 64
- 229910000679 solder Inorganic materials 0.000 claims description 23
- 239000000758 substrate Substances 0.000 description 47
- 238000000034 method Methods 0.000 description 27
- 239000000463 material Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 7
- 238000009413 insulation Methods 0.000 description 7
- 238000000465 moulding Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/24—Querying
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/40—Information retrieval; Database structures therefor; File system structures therefor of multimedia data, e.g. slideshows comprising image and additional audio data
- G06F16/43—Querying
- G06F16/435—Filtering based on additional data, e.g. user or group profiles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/90—Details of database functions independent of the retrieved data types
- G06F16/95—Retrieval from the web
- G06F16/953—Querying, e.g. by the use of web search engines
- G06F16/9535—Search customisation based on user profiles and personalisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q50/00—Information and communication technology [ICT] specially adapted for implementation of business processes of specific business sectors, e.g. utilities or tourism
- G06Q50/01—Social networking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/4814—Conductive parts
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- H01L21/486—Via connections through the substrate with or without pins
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q99/00—Subject matter not provided for in other groups of this subclass
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
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Definitions
- a semiconductor package structure includes plural of active and passive device chips. Active devices such as bipolar and field effect transistors are configured to control the flow of electrical current. Passive devices such as resistors, capacitors and inductors are used to create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active devices are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
- Active devices such as bipolar and field effect transistors are configured to control the flow of electrical current.
- Passive devices such as resistors, capacitors and inductors are used to create a relationship between voltage and current necessary to perform a variety of electrical functions.
- the passive and active devices are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
- semiconductor devices With the evolving of semiconductor technologies, semiconductor devices are becoming increasingly smaller. In the meantime, more functions need to be integrated into the semiconductor devices. Accordingly, the semiconductor devices need to have increasingly greater numbers of I/O contact pads packed into smaller areas, and the density of the I/O contact pads rises quickly with time. As a result, the packaging of the semiconductor devices becomes more difficult, which adversely affects the yield of the packaging.
- FIG. 1 is a flow chart illustrating a method for manufacturing a semiconductor package structure according to various aspects of the present disclosure.
- FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H and 2I are cross-sectional views at one of various operations of manufacturing semiconductor package structure according to one or more embodiments of the present disclosure.
- FIG. 3 is a flow chart illustrating a method for manufacturing a semiconductor package structure according to various aspects of the present disclosure.
- FIGS. 4A, 4B, 4C, 4D, 4E and 4F are cross-sectional views at one of various operations of manufacturing semiconductor package structure according to one or more embodiments of the present disclosure.
- FIG. 5 is a schematic diagram illustrating a semiconductor package structure in accordance with some embodiments of the present disclosure.
- FIG. 6 is a schematic diagram illustrating a semiconductor package structure in accordance with some embodiments of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath”, “below”, “lower”, “above”, “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another.
- the terms such as “first”, “second”, and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
- carrier substrate or “temporary substrate” refers to a carrier configured as an intermediate substrate for facility of fabrication of overlying layer such as redistribution layer, chip, encapsulant and other structures, or for dicing.
- the carrier substrate or the temporary substrate provides temporary supporting and fixing functions, and will be removed from the overlying structure.
- passive device refers to devices including resistors, capacitors, inductors or a combination thereof.
- RDL redistribution layer
- the term “interconnecting bump” refers to a conductor configured to electrically interconnecting two conductive structures through its two ends.
- the interconnecting bump is formed of a low melting point material, which can be formed by low temperature operation.
- the interconnecting bump is formed prior to formation of the encapsulant which surrounds sidewalls of the interconnecting bump.
- the interconnecting bump is a solder bump, a solder paste, or the like.
- the semiconductor package structure includes two or more redistribution layers, and these RDLs are interconnected through solder balls or solder pastes in conjunction with conductive posts embedded in an encapsulant, instead of through via structures penetrating a substrate.
- the chips are able to be embedded in the encapsulant, which reduces the overall height of the semiconductor package structure, and allows chips with distinct thicknesses to be disposed at the same level.
- FIG. 1 is a flow chart illustrating a method for manufacturing a semiconductor package structure according to various aspects of the present disclosure.
- the method 100 begins with operation 110 in which a first redistribution layer is formed over a first carrier substrate.
- the method 100 continues with operation 120 in which a plurality of first chips are disposed over the first redistribution layer.
- the method 100 proceeds with operation 130 in which a plurality of packages with a plurality of first interconnecting bumps are electrically connected to the first redistribution layer.
- the method 100 proceeds with operation 140 in which a first encapsulant is formed between the packages and the first redistribution layer.
- the method 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method 100 , and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.
- FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H and 2I are cross-sectional views at one of various operations of manufacturing semiconductor package structure according to one or more embodiments of the present disclosure.
- a first redistribution layer 20 is formed over a first carrier substrate 10 .
- the first carrier substrate 10 is configured as a temporary carrier for forming the first redistribution layer 20 , and will be removed subsequently.
- the first carrier substrate 10 is an insulative substrate such as a glass substrate.
- the first carrier substrate 10 may include a semiconductor substrate such as a silicon substrate, a conductive substrate such as a metal substrate, or other suitable substrate.
- the first redistribution layer 20 has a first surface 201 and a second surface 202 opposite to each other. In some embodiments, the second surface 202 of the first redistribution layer 20 faces the first carrier substrate 10 .
- the first redistribution layer 20 is formed by at least one conductive layer and at least one insulation layer, and configured to electrically communicate with two or more devices. In one or more embodiments, the first redistribution layer 20 includes three conductive layers 22 , 24 , 26 and at least one insulation layer 28 surrounding the conductive layers 22 , 24 , 26 . In some embodiments, the conductive layers 22 , 24 , 26 include different patterns, and some of the portions are electrically connected.
- the conductive layer 22 is exposed from the second surface 202
- the conductive layer 26 is exposed from the first surface 201 .
- the first redistribution layer 20 is formed by performing several deposition operations, photolithography operations and etching operations.
- the material of the conductive layers 22 , 24 , 26 includes metal such as copper, titanium, the like, or a combination thereof.
- the material of the at least one insulation layer 28 may include inorganic and/or organic insulation material.
- the first chips 30 include active device chips and/or passive device chips.
- the active device chip may include system on chip (SOC), memory chip such as a DRAM chip, and/or other chips.
- the passive device chip may include resistors, capacitors, inductors or a combination thereof formed therein. In some embodiments, the passive device chip may be in the form of integrated circuit, but not limited thereto.
- the first chips 30 may be mounted on the first redistribution layer 20 through surface mount technology (SMT) or other suitable bonding technologies.
- SMT surface mount technology
- each of the first chips 30 includes a plurality of contact pads 30 P, and the first chips 30 are electrically connected to the first redistribution layer 20 by bonding the contact pads 30 P to the exposed conductive layer 26 of the first redistribution layer 20 through conductive materials 34 such as solder paste, solder bump or other suitable conductive materials.
- the active device chips and the passive device chips are in electrical communication with each other through the first redistribution layer 20 .
- the thickness of different first chips 30 may be distinct. For example, the thickness of the active device chip and the passive device chip may be different.
- a plurality of packages 40 are disposed over the first redistribution layer 20 and electrically connected to the first redistribution layer 20 with a plurality of first interconnecting bumps 36 .
- the package 40 is a pre-formed structure including one or more chips which have been packaged with exposed external terminals.
- the package 40 is a memory device package such as a flash memory device package, but not limited thereto.
- the first interconnecting bump 36 is a solder ball, wherein one terminal of the solder ball is electrically connected to the external terminal of the package 40 , and the other terminal of the solder ball is electrically connected to the exposed conductive layer 26 of the first redistribution layer 20 .
- the first interconnecting bump 36 may include other types of conductor.
- a first encapsulant 38 is formed between the packages 40 and the first redistribution layer 20 .
- the material of the first encapsulant 38 is a molding compound.
- an underfill layer may be formed between the first chips 30 and the first redistribution layer 20 .
- the first encapsulant 38 is a molding under fill (MUF) layer and thus an additional underfill layer is not required.
- two opposite terminals of the solder ball are exposed from the first encapsulant 38 to electrically connect to the package 40 and the first redistribution layer 20 , respectively.
- the first encapsulant 38 covers an upper surface of the first chip 30 .
- the packages 40 are attached to a temporary substrate 42 .
- the temporary substrate 42 is a flexible film such as a tape fixed on a frame 44 .
- the temporary substrate 42 may include other types of substrates such as a rigid substrate.
- the first carrier substrate 10 is then detached from the first redistribution layer 20 .
- the first redistribution layer 20 is thinned from the second surface 202 to expose the conductive layer 22 of the first redistribution layer 20 .
- the first redistribution layer 20 is thinned by etching, but not limited.
- the first redistribution layer 20 may be thinned by grinding, polishing, or other suitable thinning methods.
- the thinning operation may be omitted.
- the exposed conductive layer 22 is configured as contact pads.
- a plurality of second interconnecting bumps 46 are formed over the first redistribution layer 20 and electrically connected to the exposed conductive layer 22 .
- the second interconnecting bump 46 is a solder ball, but not limited thereto.
- the first redistribution layer 20 are divided into pieces, and each piece of the first redistribution layer 20 is connected to the corresponding package 40 .
- the first redistribution layer 20 may be divided by sawing or other suitable cutting methods.
- the package 40 connected to the corresponding piece of the first redistribution layer 20 is detached from the temporary substrate 42 to form a semiconductor package structure 1 .
- the second interconnecting bumps 46 are configured as external connectors, and electrically connected to a circuit board 48 disposed over the second surface 202 of the first redistribution layer 20 such that the circuit board 48 is electrically connected to the first redistribution layer 20 with the second interconnecting bumps 46 .
- the semiconductor package structure 1 may be stacked on another package structure.
- the first chips 30 are embedded in the first encapsulant 38 , and thus the overall thickness is reduced.
- the first interconnecting bumps 36 are formed in the first encapsulant 38 , and prior to formation of the first encapsulant 38 , and thus no through via structure is required to electrically connect the package 40 and the first redistribution layer 20 . Consequently, the manufacturing cost and complexity are reduced.
- the first chips 30 are prevented from being thermally damaged due to high temperature in formation of through via structure.
- the first interconnecting bumps 36 are formed by low temperature operation, and the semiconductor package structure 1 requires one molding operation to form the first encapsulant 38 . Accordingly, warpage issue is alleviated.
- FIG. 3 is a flow chart illustrating a method for manufacturing a semiconductor package structure according to various aspects of the present disclosure.
- the method 200 is followed with operation 140 of the method 100 in FIG. 1 .
- the method 200 proceeds with operation 210 in which a second redistribution layer is formed over a second carrier substrate.
- the method 200 continues with operation 220 in which a plurality of second chips are disposed over the second redistribution layer.
- the method 200 proceeds with operation 230 in which each piece of the first redistribution layer with the corresponding package is electrically connected to the second redistribution layer with a plurality of second interconnecting bumps.
- the method 200 proceeds with operation 240 in which a second encapsulant is formed between the first redistribution layer and the second redistribution layer.
- the method 200 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method 200 , and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.
- FIGS. 4A, 4B, 4C, 4D, 4E and 4F are cross-sectional views at one of various operations of manufacturing semiconductor package structure according to one or more embodiments of the present disclosure.
- a second redistribution layer 60 is formed over a second carrier substrate 50 .
- the second carrier substrate 50 is configured as a temporary carrier for forming the second redistribution layer 60 , and will be removed subsequently.
- the second carrier substrate 50 is an insulative substrate such as a glass substrate.
- the second carrier substrate 50 may include a semiconductor substrate such as a silicon substrate, a conductive substrate such as a metal substrate, or other suitable substrate.
- the second redistribution layer 60 has a third surface 603 and a fourth surface 604 opposite to each other. In some embodiments, the fourth surface 604 of the second redistribution layer 60 faces the second carrier substrate 50 .
- the second redistribution layer 60 is formed by at least one conductive layer and at least one insulation layer, and configured to electrically communicate with two or more devices. In one or more embodiments, the second redistribution layer 60 includes three conductive layers 62 , 64 , 66 and at least one insulation layer 68 surrounding the conductive layers 62 , 64 , 66 . In some embodiments, the conductive layers 62 , 64 , 66 include different patterns, and some of the portions are electrically connected.
- the conductive layer 62 is exposed from the fourth surface 604
- the conductive layer 66 is exposed from the third surface 603 .
- the second redistribution layer 60 is formed by performing several deposition operations, photolithography operations and etching operations.
- the material of the conductive layers 62 , 64 , 66 includes metal such as copper, titanium, the like, or a combination thereof.
- the material of the at least one insulation layer 68 may include inorganic and/or organic insulation material.
- the second chips 70 include active device chips 72 and/or passive device chips 74 .
- the active device chip 72 may include system on chip (SOC).
- the passive device chip 74 may include resistors, capacitors, inductors or a combination thereof formed therein. In some embodiments, the passive device chip 74 may be in the form of integrated circuit, but not limited thereto.
- the second chips 70 may be mounted on the second redistribution layer 60 through surface mount technology (SMT) or other suitable bonding technologies.
- SMT surface mount technology
- each of the second chips 70 includes a plurality of contact pads 70 P, and the second chips 70 are electrically connected to the second redistribution layer 60 by bonding the contact pads 70 P to a portion of the exposed conductive layer 66 of the second redistribution layer 60 through conductive materials 76 such as solder paste, solder bump or other suitable conductive materials.
- the active device chips 72 and the passive device chips 74 are in electrical communication with each other through the second redistribution layer 60 .
- the thickness of different second chips 70 may be distinct. For example, the thickness of the active device chip 72 and the passive device chip 74 are different.
- the semiconductor package structure including the piece of the first redistribution layer 20 connected to the corresponding package 40 formed by the method illustrated in FIGS. 2A-2I are disposed on the second redistribution layer 60 , and electrically connected to the second redistribution layer 60 with the plurality of second interconnecting bumps 46 .
- the second interconnecting bump 46 is a solder ball, wherein one terminal of the solder ball is electrically connected to the first redistribution layer 20 , and the other terminal of the solder ball is electrically connected to another portion of the exposed conductive layer 66 of the second redistribution layer 60 .
- the second interconnecting bump 46 may include other types of conductor.
- a second encapsulant 78 is disposed between the first redistribution layer 20 and the second redistribution layer 60 .
- the second encapsulant 78 encloses the second chip 70 and surrounds lateral walls of the second interconnecting bumps 46 .
- the material of the second encapsulant 78 is a molding compound.
- an underfill layer may be formed between the second chips 70 and the second redistribution layer 60 .
- the second encapsulant 78 is a molding under fill (MUF) layer and thus an additional underfill layer is not required.
- two opposite terminals of the solder ball are exposed from the second encapsulant 78 to electrically connect to the first redistribution layer 20 and the second redistribution layer 60 , respectively.
- the packages 40 are attached to another temporary substrate 82 .
- the temporary substrate 82 is a flexible film such as a tape fixed on a frame 84 .
- the temporary substrate 82 may include other types of substrates such as a rigid substrate.
- the second carrier substrate 50 is then detached from the second redistribution layer 60 .
- the second redistribution layer 60 is thinned from the fourth surface 604 to expose the conductive layer 62 of the second redistribution layer 60 .
- the second redistribution layer 60 is thinned by etching, but not limited.
- the second redistribution layer 60 may be thinned by grinding, polishing, or other suitable thinning methods. In some embodiments, in case the conductive layer 62 is exposed from the second redistribution layer 60 in advance, the thinning operation may be omitted. In some embodiments, the exposed conductive layer 62 is configured as contact pads.
- the external connectors 86 are formed over the fourth surface 604 of the second redistribution layer 60 and electrically connected to a portion of the exposed conductive layer 62 of the second redistribution layer 60 .
- the external connectors 86 are arranged as a ball grid array (BGA), but not limited thereto.
- BGA ball grid array
- several third chips 88 may be disposed over the fourth surface 604 of the second redistribution layer 60 and electrically connected to another portion of the exposed conductive layer 62 of the second redistribution layer 60 .
- the third chip 88 is a passive device chip, which may include resistors, capacitors, inductors or a combination thereof formed therein.
- the third chips 88 are in electrical communication with the second chips 70 through the second redistribution layer 60 , and in electrical communication with the first chips 30 through the first redistribution layer 20 .
- the second redistribution layer 60 is sawed by any suitable cutting methods. Subsequently, the temporary substrate 82 is removed to form semiconductor package structures 2 .
- the first chips 30 and the second chips 70 are embedded in the first encapsulant 38 and the second encapsulant 78 , and thus the overall thickness is reduced.
- the first interconnecting bumps 36 are formed in the first encapsulant 38
- the second interconnecting bumps 46 are formed in the second encapsulant 78 , and thus no through via structure is required. Consequently, the manufacturing cost and complexity are reduced.
- the first chips 30 and the second chips 70 are prevented from being thermally damaged due to high temperature in formation of through via structure.
- the first interconnecting bumps 36 and the second interconnecting bumps 46 are formed by low temperature operation, and the semiconductor package structure 2 requires two molding operations to form the first encapsulant 38 and the second encapsulant 78 . Accordingly, warpage issue is alleviated.
- the present disclosure is not limited to the above-mentioned embodiments, and may have other different embodiments.
- the identical components in each of the following embodiments are marked with identical numerals.
- the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
- FIG. 5 is a schematic diagram illustrating a semiconductor package structure 3 in accordance with some embodiments of the present disclosure.
- the semiconductor package structure 3 includes a first redistribution layer (RDL) 20 , first chips 30 , first interconnecting bumps 36 , first encapsulant 38 , a second RDL 60 , second chips 70 , second interconnecting bumps 46 , and second encapsulant 78 .
- the first RDL 20 has a first surface 201 and a second surface 202 opposite to each other.
- the first chip 30 are disposed over the first RDL 20 with a plurality of contact pads 30 P facing the first surface 201 and electrically connected to the first RDL 20 .
- the first interconnecting bumps 36 are disposed over the first surface 201 and electrically connected to the first RDL 20 .
- the first encapsulant 38 is disposed over the first surface 201 of the first RDL 20 .
- the first encapsulant 38 encloses the first chips 30 and surrounds lateral walls of the first interconnecting bumps 36 .
- the second RDL 60 is over the second surface 202 of the first RDL 20 .
- the second RDL 60 has a third surface 603 and a fourth surface 604 opposite to each other, and the third surface 603 faces the second surface 202 .
- the second chips 70 are disposed over the second RDL 60 with a plurality of contact pads 70 P facing the third surface 603 .
- the second interconnecting bumps 46 are disposed over the third surface 603 and electrically connected to the second RDL 60 .
- the second encapsulant 78 is disposed between the first RDL 20 and the second RDL 60 .
- the second encapsulant 78 encloses the second chip 70 and surrounds lateral walls of the second interconnecting bumps 46 .
- the semiconductor package structure 3 further includes a package (not shown) disposed over the first encapsulant 38 and electrically connected to the first RDL 20 through the first interconnecting bumps 36 .
- the height of the second interconnecting bumps 46 is higher than the height of the second chip 70 .
- the semiconductor package structure 3 further includes a circuit board (not shown) disposed over the fourth surface 604 of the second RDL 60 , and external connectors 86 disposed between the fourth surface 604 and the circuit board to electrically connect the second RDL 60 with the circuit board.
- FIG. 6 is a schematic diagram illustrating a semiconductor package structure 4 in accordance with some embodiments of the present disclosure.
- the semiconductor package structure 4 further includes conductive posts 90 disposed in the second encapsulant 78 .
- each of the second interconnecting bumps 46 is a solder paste, where one terminal of the conductive post 90 is connected to the second RDL 60 , and the other terminal of the conductive post 90 is connected to the corresponding second interconnecting bump 46 .
- the fabrication and the materials of the conductive posts 90 and the second interconnecting bumps 46 are different.
- the conductive posts 90 are formed by deposition, photolithography and etching operations, and thus the pitch between adjacent conductive posts 90 can be reduced. Accordingly, the conductive post 90 in association with the solder paste is able to fulfill fine-pitch joint between the first RDL 20 and the second RDL 60 .
- the height ratio between the conductive posts 90 and the second interconnecting bumps 46 may be modified based on different considerations.
- the upper surface of the conductive post 90 is substantially leveled with the upper surface of the second chip 70 .
- the upper surface of the conductive post 90 is lower than the upper surface of the second chip 70 .
- the overall height of the conductive posts 90 and the second interconnecting bumps 46 is higher than the height of the second chip 70 .
- the chips are embedded in the encapsulant, and thus the overall thickness of the semiconductor package structure is reduced.
- the system performance is improved due to reduction of electrical communication path among chips.
- the chips configured for providing different functionalities such as active device chip and passive device chip may have different thicknesses, and thus the flexibility in selecting chips is increased.
- No through via structure is required, and therefore the manufacturing cost and complexity are reduced.
- the chips are prevented from being thermally damaged due to high temperature in formation of through via structure.
- the interconnecting bumps are formed of low melting point material, which can be formed by low temperature operation. Thus, thermal budget is reduced.
- the semiconductor package structure requires fewer molding operations to form the encapsulant(s). Accordingly, warpage issue is alleviated.
- a semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant.
- the redistribution layer has a first surface and a second surface opposite to each other.
- the chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer.
- the interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer.
- the encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.
- a semiconductor package structure in another exemplary aspect, includes a first redistribution layer, a first chip, a plurality of first interconnecting bumps, a first encapsulant, a second redistribution layer, a second chip, a plurality of second interconnecting bumps and a second encapsulant.
- the first redistribution layer has a first surface and a second surface opposite to each other.
- the first chip is disposed over the first redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the first redistribution layer.
- the first interconnecting bumps are disposed over the first surface and electrically connected to the first redistribution layer.
- the first encapsulant is disposed over the first surface of the first redistribution layer.
- the first encapsulant encloses the first chip and surrounds lateral walls of the first interconnecting bumps.
- the second redistribution layer is over the second surface of the first redistribution layer.
- the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the second surface.
- the second chip is disposed over the second redistribution layer with a plurality of contact pads facing the third surface.
- the second interconnecting bumps are disposed over the third surface and electrically connected to the second redistribution layer.
- the second encapsulant is disposed between the first redistribution layer and the second redistribution layer, and the second encapsulant encloses the second chip and surrounds lateral walls of the second interconnecting bumps.
- a method for manufacturing a semiconductor package structure includes: forming a first redistribution layer over a first carrier substrate; disposing a plurality of first chips over the first redistribution layer; electrically connecting a plurality of packages to the first redistribution layer with a plurality of first interconnecting bumps; and forming a first encapsulant between the packages and the first redistribution layer.
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Abstract
A semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.
Description
This application claims priority of U.S. provisional application Ser. No. 62/366,295 filed on 25 Jul. 2016, which is incorporated by reference in its entirety.
A semiconductor package structure includes plural of active and passive device chips. Active devices such as bipolar and field effect transistors are configured to control the flow of electrical current. Passive devices such as resistors, capacitors and inductors are used to create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active devices are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
With the evolving of semiconductor technologies, semiconductor devices are becoming increasingly smaller. In the meantime, more functions need to be integrated into the semiconductor devices. Accordingly, the semiconductor devices need to have increasingly greater numbers of I/O contact pads packed into smaller areas, and the density of the I/O contact pads rises quickly with time. As a result, the packaging of the semiconductor devices becomes more difficult, which adversely affects the yield of the packaging.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the terms such as “first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first”, “second”, and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
As used herein, the term “carrier substrate” or “temporary substrate” refers to a carrier configured as an intermediate substrate for facility of fabrication of overlying layer such as redistribution layer, chip, encapsulant and other structures, or for dicing. The carrier substrate or the temporary substrate provides temporary supporting and fixing functions, and will be removed from the overlying structure.
As used herein, the term “passive device” refers to devices including resistors, capacitors, inductors or a combination thereof.
As used herein, the term “redistribution layer (RDL)” refers to a layer stack formed from at least one conductive pattern and at least one insulation layer, and configured to electrically communicate with two or more devices.
As used herein, the term “interconnecting bump” refers to a conductor configured to electrically interconnecting two conductive structures through its two ends. In one or more embodiments, the interconnecting bump is formed of a low melting point material, which can be formed by low temperature operation. The interconnecting bump is formed prior to formation of the encapsulant which surrounds sidewalls of the interconnecting bump. In one or more embodiments, the interconnecting bump is a solder bump, a solder paste, or the like.
In some embodiments of the present disclosure, the semiconductor package structure includes two or more redistribution layers, and these RDLs are interconnected through solder balls or solder pastes in conjunction with conductive posts embedded in an encapsulant, instead of through via structures penetrating a substrate. The chips are able to be embedded in the encapsulant, which reduces the overall height of the semiconductor package structure, and allows chips with distinct thicknesses to be disposed at the same level.
The method 100 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method 100, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.
As depicted in FIG. 2B , several first chips 30 are disposed over the first redistribution layer 20. In one or more embodiments, the first chips 30 include active device chips and/or passive device chips. By way of examples, the active device chip may include system on chip (SOC), memory chip such as a DRAM chip, and/or other chips. The passive device chip may include resistors, capacitors, inductors or a combination thereof formed therein. In some embodiments, the passive device chip may be in the form of integrated circuit, but not limited thereto. The first chips 30 may be mounted on the first redistribution layer 20 through surface mount technology (SMT) or other suitable bonding technologies. In some embodiments, each of the first chips 30 includes a plurality of contact pads 30P, and the first chips 30 are electrically connected to the first redistribution layer 20 by bonding the contact pads 30P to the exposed conductive layer 26 of the first redistribution layer 20 through conductive materials 34 such as solder paste, solder bump or other suitable conductive materials. In one or more embodiments, the active device chips and the passive device chips are in electrical communication with each other through the first redistribution layer 20. In some embodiments, the thickness of different first chips 30 may be distinct. For example, the thickness of the active device chip and the passive device chip may be different.
As depicted in FIG. 2C , a plurality of packages 40 are disposed over the first redistribution layer 20 and electrically connected to the first redistribution layer 20 with a plurality of first interconnecting bumps 36. In one or more embodiments, the package 40 is a pre-formed structure including one or more chips which have been packaged with exposed external terminals. In one or more embodiments, the package 40 is a memory device package such as a flash memory device package, but not limited thereto. In one or more embodiments, the first interconnecting bump 36 is a solder ball, wherein one terminal of the solder ball is electrically connected to the external terminal of the package 40, and the other terminal of the solder ball is electrically connected to the exposed conductive layer 26 of the first redistribution layer 20. The first interconnecting bump 36 may include other types of conductor.
As depicted in FIG. 2D , a first encapsulant 38 is formed between the packages 40 and the first redistribution layer 20. In one or more embodiments, the material of the first encapsulant 38 is a molding compound. In some embodiments, an underfill layer may be formed between the first chips 30 and the first redistribution layer 20. In some embodiments, the first encapsulant 38 is a molding under fill (MUF) layer and thus an additional underfill layer is not required. In one or more embodiments, two opposite terminals of the solder ball are exposed from the first encapsulant 38 to electrically connect to the package 40 and the first redistribution layer 20, respectively. In some embodiments, the first encapsulant 38 covers an upper surface of the first chip 30.
As depicted in FIG. 2E , the packages 40 are attached to a temporary substrate 42. In one or more embodiments, the temporary substrate 42 is a flexible film such as a tape fixed on a frame 44. In some embodiments, the temporary substrate 42 may include other types of substrates such as a rigid substrate. The first carrier substrate 10 is then detached from the first redistribution layer 20.
As depicted in FIG. 2F , the first redistribution layer 20 is thinned from the second surface 202 to expose the conductive layer 22 of the first redistribution layer 20. In one or more embodiments, the first redistribution layer 20 is thinned by etching, but not limited. In some embodiments, the first redistribution layer 20 may be thinned by grinding, polishing, or other suitable thinning methods. In some embodiments, in case the conductive layer 22 is exposed from the first redistribution layer 20 in advance, the thinning operation may be omitted. In some embodiments, the exposed conductive layer 22 is configured as contact pads.
As depicted in FIG. 2G , a plurality of second interconnecting bumps 46 are formed over the first redistribution layer 20 and electrically connected to the exposed conductive layer 22. In one or more embodiments, the second interconnecting bump 46 is a solder ball, but not limited thereto.
As depicted in FIG. 2H , the first redistribution layer 20 are divided into pieces, and each piece of the first redistribution layer 20 is connected to the corresponding package 40. In one or more embodiments, the first redistribution layer 20 may be divided by sawing or other suitable cutting methods.
As depicted in FIG. 2I , the package 40 connected to the corresponding piece of the first redistribution layer 20 is detached from the temporary substrate 42 to form a semiconductor package structure 1. In one or more embodiments, the second interconnecting bumps 46 are configured as external connectors, and electrically connected to a circuit board 48 disposed over the second surface 202 of the first redistribution layer 20 such that the circuit board 48 is electrically connected to the first redistribution layer 20 with the second interconnecting bumps 46. In one or more embodiments, the semiconductor package structure 1 may be stacked on another package structure.
The first chips 30 are embedded in the first encapsulant 38, and thus the overall thickness is reduced. The first interconnecting bumps 36 are formed in the first encapsulant 38, and prior to formation of the first encapsulant 38, and thus no through via structure is required to electrically connect the package 40 and the first redistribution layer 20. Consequently, the manufacturing cost and complexity are reduced. In addition, the first chips 30 are prevented from being thermally damaged due to high temperature in formation of through via structure. Also, the first interconnecting bumps 36 are formed by low temperature operation, and the semiconductor package structure 1 requires one molding operation to form the first encapsulant 38. Accordingly, warpage issue is alleviated.
The method 200 is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method 200, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.
As depicted in FIG. 4B , several second chips 70 are disposed over the second redistribution layer 60. In one or more embodiments, the second chips 70 include active device chips 72 and/or passive device chips 74. By way of example, the active device chip 72 may include system on chip (SOC). The passive device chip 74 may include resistors, capacitors, inductors or a combination thereof formed therein. In some embodiments, the passive device chip 74 may be in the form of integrated circuit, but not limited thereto. The second chips 70 may be mounted on the second redistribution layer 60 through surface mount technology (SMT) or other suitable bonding technologies. In some embodiments, each of the second chips 70 includes a plurality of contact pads 70P, and the second chips 70 are electrically connected to the second redistribution layer 60 by bonding the contact pads 70P to a portion of the exposed conductive layer 66 of the second redistribution layer 60 through conductive materials 76 such as solder paste, solder bump or other suitable conductive materials. In one or more embodiments, the active device chips 72 and the passive device chips 74 are in electrical communication with each other through the second redistribution layer 60. In some embodiments, the thickness of different second chips 70 may be distinct. For example, the thickness of the active device chip 72 and the passive device chip 74 are different.
As depicted in FIG. 4C , the semiconductor package structure including the piece of the first redistribution layer 20 connected to the corresponding package 40 formed by the method illustrated in FIGS. 2A-2I are disposed on the second redistribution layer 60, and electrically connected to the second redistribution layer 60 with the plurality of second interconnecting bumps 46. In one or more embodiments, the second interconnecting bump 46 is a solder ball, wherein one terminal of the solder ball is electrically connected to the first redistribution layer 20, and the other terminal of the solder ball is electrically connected to another portion of the exposed conductive layer 66 of the second redistribution layer 60. The second interconnecting bump 46 may include other types of conductor.
As depicted in FIG. 4D , a second encapsulant 78 is disposed between the first redistribution layer 20 and the second redistribution layer 60. In one or more embodiments, the second encapsulant 78 encloses the second chip 70 and surrounds lateral walls of the second interconnecting bumps 46. In one or more embodiments, the material of the second encapsulant 78 is a molding compound. In some embodiments, an underfill layer may be formed between the second chips 70 and the second redistribution layer 60. In some embodiments, the second encapsulant 78 is a molding under fill (MUF) layer and thus an additional underfill layer is not required. In one or more embodiments, two opposite terminals of the solder ball are exposed from the second encapsulant 78 to electrically connect to the first redistribution layer 20 and the second redistribution layer 60, respectively.
As depicted in FIG. 4E , the packages 40 are attached to another temporary substrate 82. In one or more embodiments, the temporary substrate 82 is a flexible film such as a tape fixed on a frame 84. In some embodiments, the temporary substrate 82 may include other types of substrates such as a rigid substrate. The second carrier substrate 50 is then detached from the second redistribution layer 60. In some embodiments, the second redistribution layer 60 is thinned from the fourth surface 604 to expose the conductive layer 62 of the second redistribution layer 60. In one or more embodiments, the second redistribution layer 60 is thinned by etching, but not limited. In some embodiments, the second redistribution layer 60 may be thinned by grinding, polishing, or other suitable thinning methods. In some embodiments, in case the conductive layer 62 is exposed from the second redistribution layer 60 in advance, the thinning operation may be omitted. In some embodiments, the exposed conductive layer 62 is configured as contact pads.
As depicted in FIG. 4F , several external connectors 86 are formed over the fourth surface 604 of the second redistribution layer 60 and electrically connected to a portion of the exposed conductive layer 62 of the second redistribution layer 60. In one or more embodiments, the external connectors 86 are arranged as a ball grid array (BGA), but not limited thereto. In one or more embodiments, several third chips 88 may be disposed over the fourth surface 604 of the second redistribution layer 60 and electrically connected to another portion of the exposed conductive layer 62 of the second redistribution layer 60. In some embodiments, the third chip 88 is a passive device chip, which may include resistors, capacitors, inductors or a combination thereof formed therein. The third chips 88 are in electrical communication with the second chips 70 through the second redistribution layer 60, and in electrical communication with the first chips 30 through the first redistribution layer 20. The second redistribution layer 60 is sawed by any suitable cutting methods. Subsequently, the temporary substrate 82 is removed to form semiconductor package structures 2.
The first chips 30 and the second chips 70 are embedded in the first encapsulant 38 and the second encapsulant 78, and thus the overall thickness is reduced. The first interconnecting bumps 36 are formed in the first encapsulant 38, and the second interconnecting bumps 46 are formed in the second encapsulant 78, and thus no through via structure is required. Consequently, the manufacturing cost and complexity are reduced. In addition, the first chips 30 and the second chips 70 are prevented from being thermally damaged due to high temperature in formation of through via structure. Also, the first interconnecting bumps 36 and the second interconnecting bumps 46 are formed by low temperature operation, and the semiconductor package structure 2 requires two molding operations to form the first encapsulant 38 and the second encapsulant 78. Accordingly, warpage issue is alleviated.
The present disclosure is not limited to the above-mentioned embodiments, and may have other different embodiments. To simplify the description and for the convenience of comparison between each of the embodiments of the present disclosure, the identical components in each of the following embodiments are marked with identical numerals. For making it easier to compare the difference between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
In the present disclosure, the chips are embedded in the encapsulant, and thus the overall thickness of the semiconductor package structure is reduced. The system performance is improved due to reduction of electrical communication path among chips. The chips configured for providing different functionalities such as active device chip and passive device chip may have different thicknesses, and thus the flexibility in selecting chips is increased. No through via structure is required, and therefore the manufacturing cost and complexity are reduced. The chips are prevented from being thermally damaged due to high temperature in formation of through via structure. Compared to through via structure, the interconnecting bumps are formed of low melting point material, which can be formed by low temperature operation. Thus, thermal budget is reduced. Also, the semiconductor package structure requires fewer molding operations to form the encapsulant(s). Accordingly, warpage issue is alleviated.
In one exemplary aspect, a semiconductor package structure includes a redistribution layer (RDL), a chip, a plurality of interconnecting bumps and an encapsulant. The redistribution layer has a first surface and a second surface opposite to each other. The chip is disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer. The interconnecting bumps are disposed over the first surface and electrically connected to the redistribution layer. The encapsulant is disposed over the first surface of the redistribution layer, and the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.
In another exemplary aspect, a semiconductor package structure includes a first redistribution layer, a first chip, a plurality of first interconnecting bumps, a first encapsulant, a second redistribution layer, a second chip, a plurality of second interconnecting bumps and a second encapsulant. The first redistribution layer has a first surface and a second surface opposite to each other. The first chip is disposed over the first redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the first redistribution layer. The first interconnecting bumps are disposed over the first surface and electrically connected to the first redistribution layer. The first encapsulant is disposed over the first surface of the first redistribution layer. The first encapsulant encloses the first chip and surrounds lateral walls of the first interconnecting bumps. The second redistribution layer is over the second surface of the first redistribution layer. The second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the second surface. The second chip is disposed over the second redistribution layer with a plurality of contact pads facing the third surface. The second interconnecting bumps are disposed over the third surface and electrically connected to the second redistribution layer. The second encapsulant is disposed between the first redistribution layer and the second redistribution layer, and the second encapsulant encloses the second chip and surrounds lateral walls of the second interconnecting bumps.
In yet another aspect, a method for manufacturing a semiconductor package structure includes: forming a first redistribution layer over a first carrier substrate; disposing a plurality of first chips over the first redistribution layer; electrically connecting a plurality of packages to the first redistribution layer with a plurality of first interconnecting bumps; and forming a first encapsulant between the packages and the first redistribution layer.
The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A semiconductor package structure, comprising:
a redistribution layer (RDL) having a first surface and a second surface opposite to each other;
a chip disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer;
a plurality of interconnecting bumps disposed over the first surface and electrically connected to the redistribution layer;
a second redistribution layer over the second surface of the redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface faces the second surface;
a second chip disposed over the second surface and electrically connected to the redistribution layer, wherein the second chip includes a plurality of contact pads facing the third surface of the second redistribution layer; and
an encapsulant disposed over the first surface of the redistribution layer, wherein the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps.
2. The semiconductor package structure of claim 1 , further comprising a circuit board disposed over the second surface of the redistribution layer, and a plurality of external connectors disposed between the second surface and the circuit board to electrically connect the redistribution layer with the circuit board.
3. The semiconductor package structure of claim 1 , further comprising a package disposed over the encapsulant and electrically connected to the redistribution layer through the interconnecting bumps.
4. The semiconductor package structure of claim 1 , wherein each of the plurality of interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of interconnecting bumps are exposed from the encapsulant.
5. The semiconductor package structure of claim 1 , wherein the chip comprises an active device chip and a passive device chip.
6. The semiconductor package structure of claim 1 , further comprising a plurality of second interconnecting bumps between the second surface and the third surface, and electrically connected to the redistribution layer and the second redistribution layer.
7. A semiconductor package structure, comprising:
a first redistribution layer (RDL) having a first surface and a second surface opposite to each other;
a first chip disposed over the first redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the first redistribution layer;
a plurality of first interconnecting bumps disposed over the first surface and electrically connected to the first redistribution layer;
a first encapsulant disposed over the first surface of the first redistribution layer, wherein the first encapsulant encloses the first chip and surrounds lateral walls of the first interconnecting bumps;
a second redistribution layer over the second surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the second surface;
a second chip disposed over the second redistribution layer with a plurality of contact pads facing the third surface;
a plurality of second interconnecting bumps disposed over the third surface and electrically connected to the second redistribution layer; and
a second encapsulant disposed between the first redistribution layer and the second redistribution layer, wherein the second encapsulant encloses the second chip and surrounds lateral walls of the second interconnecting bumps.
8. The semiconductor package structure of claim 7 , further comprising a circuit board disposed over the fourth surface of the second redistribution layer, and a plurality of external connectors disposed between the fourth surface and the circuit board to electrically connect the second redistribution layer with the circuit board.
9. The semiconductor package structure of claim 7 , further comprising a package disposed over the first encapsulant and electrically connected to the first redistribution layer through the first interconnecting bumps.
10. The semiconductor package structure of claim 7 , wherein each of the plurality of first interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of first interconnecting bumps are exposed from the first encapsulant.
11. The semiconductor package structure of claim 7 , wherein each of the plurality of second interconnecting bumps is a solder ball, and two opposite terminals of each of the plurality of second interconnecting bumps are exposed from the second encapsulant.
12. The semiconductor package structure of claim 7 , further comprising a plurality of conductive posts disposed in the second encapsulant, wherein each of the plurality of conductive posts is a solder paste, one terminal of each of the plurality of conductive posts is connected to the second redistribution layer, and the other terminal of each of the plurality of conductive posts is connected to a corresponding second interconnecting bump of the plurality of second interconnecting bumps.
13. The semiconductor package structure of claim 7 , wherein the first chip comprises a memory chip and a passive device chip.
14. The semiconductor package structure of claim 7 , wherein the second chip comprises an active device chip and a passive device chip.
15. The semiconductor package structure of claim 7 , further comprising a third chip disposed over the fourth surface and electrically connected to the second redistribution layer.
16. A semiconductor package structure, comprising:
a redistribution layer (RDL) having a first surface and a second surface opposite to each other;
a chip disposed over the redistribution layer with a plurality of contact pads facing the first surface and electrically connected to the redistribution layer;
a plurality of interconnecting bumps disposed over the first surface and electrically connected to the redistribution layer;
a plurality of conductive posts disposed over the first surface, wherein one terminal of each of the plurality of conductive posts is connected to the redistribution layer, and the other terminal of each of the plurality of conductive posts is connected to a corresponding interconnecting bump of the plurality of interconnecting bumps; and
an encapsulant disposed over the first surface of the redistribution layer, wherein the encapsulant encloses the chip and surrounds lateral walls of the interconnecting bumps and lateral walls of the conductive posts.
17. The semiconductor package structure of claim 16 , further comprising a circuit board disposed over the second surface of the redistribution layer, and a plurality of external connectors disposed between the second surface and the circuit board to electrically connect the redistribution layer with the circuit board.
18. The semiconductor package structure of claim 16 , further comprising a package disposed over the encapsulant and electrically connected to the redistribution layer through the interconnecting bumps and the conductive posts.
19. The semiconductor package structure of claim 16 , wherein the chip comprises an active device chip and a passive device chip.
20. The semiconductor package structure of claim 16 , further comprising a second chip disposed over the second surface and electrically connected to the redistribution layer.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/371,869 US9997471B2 (en) | 2016-07-25 | 2016-12-07 | Semiconductor package structure and manufacturing method thereof |
TW106111706A TWI739821B (en) | 2016-07-25 | 2017-04-07 | Semiconductor package structure and manufacturing method thereof |
CN201710450368.1A CN107658274B (en) | 2016-07-25 | 2017-06-15 | Semiconductor package structure and manufacturing method thereof |
US16/004,600 US10636747B2 (en) | 2016-07-25 | 2018-06-11 | Semiconductor package structure |
US16/859,037 US11532569B2 (en) | 2016-07-25 | 2020-04-27 | Method for manufacturing semiconductor package structure |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662366295P | 2016-07-25 | 2016-07-25 | |
US15/371,869 US9997471B2 (en) | 2016-07-25 | 2016-12-07 | Semiconductor package structure and manufacturing method thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/004,600 Continuation US10636747B2 (en) | 2016-07-25 | 2018-06-11 | Semiconductor package structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180025992A1 US20180025992A1 (en) | 2018-01-25 |
US9997471B2 true US9997471B2 (en) | 2018-06-12 |
Family
ID=60988680
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/371,869 Active US9997471B2 (en) | 2016-07-25 | 2016-12-07 | Semiconductor package structure and manufacturing method thereof |
US16/004,600 Active US10636747B2 (en) | 2016-07-25 | 2018-06-11 | Semiconductor package structure |
US16/859,037 Active 2037-05-24 US11532569B2 (en) | 2016-07-25 | 2020-04-27 | Method for manufacturing semiconductor package structure |
US17/466,829 Abandoned US20220129995A1 (en) | 2016-07-25 | 2021-09-03 | Online dating and social networking system |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/004,600 Active US10636747B2 (en) | 2016-07-25 | 2018-06-11 | Semiconductor package structure |
US16/859,037 Active 2037-05-24 US11532569B2 (en) | 2016-07-25 | 2020-04-27 | Method for manufacturing semiconductor package structure |
US17/466,829 Abandoned US20220129995A1 (en) | 2016-07-25 | 2021-09-03 | Online dating and social networking system |
Country Status (3)
Country | Link |
---|---|
US (4) | US9997471B2 (en) |
CN (1) | CN107658274B (en) |
TW (1) | TWI739821B (en) |
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Also Published As
Publication number | Publication date |
---|---|
CN107658274A (en) | 2018-02-02 |
US20200258849A1 (en) | 2020-08-13 |
TWI739821B (en) | 2021-09-21 |
US11532569B2 (en) | 2022-12-20 |
CN107658274B (en) | 2022-12-27 |
US20180294237A1 (en) | 2018-10-11 |
US20220129995A1 (en) | 2022-04-28 |
US10636747B2 (en) | 2020-04-28 |
US20180025992A1 (en) | 2018-01-25 |
TW201813023A (en) | 2018-04-01 |
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