US9871623B2 - Viterbi decoding apparatus and viterbi decoding method - Google Patents
Viterbi decoding apparatus and viterbi decoding method Download PDFInfo
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- US9871623B2 US9871623B2 US15/153,842 US201615153842A US9871623B2 US 9871623 B2 US9871623 B2 US 9871623B2 US 201615153842 A US201615153842 A US 201615153842A US 9871623 B2 US9871623 B2 US 9871623B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
Definitions
- the invention relates in general to Viterbi decoding technologies, and more particularly to a Viterbi decoding technology capable of providing two types of decoded results.
- Concatenated error correction codes currently applied to numerous types of communication systems and signal broadcasting systems enhance the performance of encoded results through combining two or more encoding technologies.
- a receiver in such system needs to first perform an inner code decoding process, and then perform an outer code decoding process on the inner code decoded result.
- DVD-T Digital Video Broadcasting—Terrestrial
- the receiver needs to decode convolutional encoded data by a Viterbi decoder and then sends the decoded result to a Reed-Solomon decoder.
- a typical Viterbi decoder selects an optimum decoded result from many possible decoded results and provides the selected optimum decoded result to the Reed-Solomon decoder.
- the optimum decoded result identified by the Viterbi decoder may not be correct data (i.e., actual data transmitted by the transmitter).
- the Reed-Solomon decoder is usually incapable of decoding such packet as the packet contains too many errors.
- the Viterbi decoder is designed to provide more than one decoded result (e.g., simultaneously providing an optimum decoded result and a second optimum decoded result) to the Reed-Solomon decoder. If the Reed-Solomon decoder cannot decode the optimum packet, it may attempt to decode the second optimum decoded result, hence enhancing the probability of successful decoding.
- the invention is directed to a Viterbi decoding apparatus and a Viterbi decoding method that are different from a conventional solution of generating a second optimum decoded result.
- a Viterbi decoding apparatus includes a main decoder, a re-encoder, an adjusting module, a secondary decoder and a secondary result generating module.
- the main decoder performs a Viterbi decoding process on input data to generate a set of main decoded results.
- the re-encoder performs a convolutional encoding process on the set of main decoded results to generate a set of re-encoded results.
- the adjusting module adjusts the input data according to the set of re-encoded results to generate adjusted input data corresponding to a predetermined path in a Viterbi trellis diagram.
- the secondary decoder generates a plurality of symbols according to the adjusted input data.
- the secondary result generating module generates a set of secondary decoded results according to the plurality of symbols and the set of main decoded results.
- a Viterbi decoding method is provided.
- a Viterbi decoding process is performed on input data to generate a set of main decoded results.
- a convolutional encoding process is performed on the set of main decoded results to generate a set of re-encoded results.
- the input data is adjusted according to the set of re-encoded results to generate adjusted input data corresponding to a predetermined path in a Viterbi trellis diagram.
- a plurality of symbols are generated according to the adjusted input data.
- a set of secondary decoded results are generated according to the plurality of symbols and the set of main decoded results.
- FIG. 1 is a function block diagram of a Viterbi decoding apparatus according to an embodiment of the present invention
- FIG. 2 is a schematic diagram of examples of an adjusting module and a secondary result generating module in a Viterbi decoding apparatus according to an embodiment of the present invention
- FIG. 3 is a partial diagram of an example of a secondary Viterbi decoder according to an embodiment of the present invention.
- FIG. 4(A) and FIG. 4(B) are examples of a trellis diagram and corresponding decoded results
- FIG. 5 is a flowchart of a Viterbi decoding process according to an embodiment of the present invention.
- FIG. 6 is a detail partial process of a Viterbi decoding step according to an embodiment of the present invention.
- drawings of the present invention include function block diagrams of multiple function modules related to one another. These drawings are not detailed circuit diagrams, and connection lines therein are for indicating signal flows only. The interactions between the function elements/or processes are not necessarily achieved through direct electrical connections. Further, functions of the individual elements are not necessarily distributed as depicted in the drawings, and separate blocks are not necessarily implemented by separate electronic elements.
- FIG. 1 shows a function block diagram of a Viterbi decoding apparatus 100 according to an embodiment of the present invention.
- the Viterbi decoding apparatus 100 includes a main Viterbi decoder 11 , a re-encoder 12 , an adjusting module 13 , a secondary Viterbi decoder 14 and a secondary result generating module 15 .
- the Viterbi decoding apparatus 100 may be integrated in various kinds of electronic systems adopting concatenated error correction codes, or may be an independent unit.
- the main Viterbi decoder 11 performs a Viterbi decoding process on its input data, and identifies a decoded result corresponding to an optimum path in a trellis diagram as a set of main decoded results according to the input data.
- the main Viterbi decoder 11 which may be typical Viterbi decoder, includes a branch metric unit (BMU), a path metric unit (PMU) and a trace-back unit, and selects a series of bits or multiple symbols corresponding to an optimum path in the trellis diagram as decoded results by an add-compare-select process.
- BMU branch metric unit
- PMU path metric unit
- trace-back unit selects a series of bits or multiple symbols corresponding to an optimum path in the trellis diagram as decoded results by an add-compare-select process.
- a parity bit in original input data is removed, such that a decoded result contains only a data bit associated with actual information.
- the re-encoder 12 performs a convolutional encoding process on the set of main decoded results generated by the main Viterbi decoder 11 to generate a set of re-encoded results.
- the function of the re-encoder 12 may be regarded as simulating the task of the transmitter—a set of input data including a parity bit is reconstructed according to the set of main decoded results generated by the Viterbi decoder 11 .
- the adjusting module 13 adjusts the input data according to the set of re-encoded data generated by the re-encoder 12 to generate adjusted input data that substantially corresponds to a predetermined path in the Viterbi trellis diagram.
- the predetermined path is an all-zero path, e.g., a linear path totally corresponding to a node “00” at the top of the trellis diagram in FIG. 4(A) .
- the adjusting module 13 adjusts the input data, such that the main decoded results generated from performing a Viterbi decoding process on the adjusted input data correspond to the all-zero path in the Viterbi trellis diagram.
- FIG. 2 further shows a detailed example of the adjusting module 13 , which is capable of causing the adjusted input data to be substantially corresponding to the all-zero path. Associated operation details are as below.
- the adjusting module 13 includes a positive/negative sign determining unit 13 A, a first delay line 13 B and a multiplier 13 C.
- the positive/negative sign determining unit 13 A obtains the positive/negative sign of each re-encoded result in the set of re-encoded results.
- a signal provided to the main Viterbi decoder 11 includes N sets of data (where N is an integer greater than 1)
- the set of the re-encoded results generated by the re-encoder 12 includes N re-encoded results
- the function of the positive/negative sign determining module 13 A is to obtain the positive/negative sign of each of the N re-encoded results. As shown in FIG.
- the first delay line 13 B provides a delay amount for the input signal of the main Viterbi decoder 11 , and transmits a delayed result that is to be multiplied by the output signal of the positive/negative sign determining unit 13 A to the multiplier 13 C.
- the delay amount provided by the first delay line 13 B is set to be substantially equal to the total delay caused by the main Viterbi decoder 11 , the re-encoder 12 and the positive/negative sign determining module 13 A. As such, each set of delayed input signal is multiplied by the positive/negative sign corresponding to the same set of data.
- the multiplier 13 C multiples the i th positive/negative sign in the N positive/negative signs by the i th set of data of the input data to generate N sets of adjusted data as the adjusted input data outputted by the adjusting module 13 (where i is an integral index between 1 and N).
- the transmitter maps a signal having data contents corresponding to digital logic “0” as a signal having an amplitude “+1”, and maps a signal having data contents corresponding to digital logic “1” as a signal having an amplitude “ ⁇ 1”.
- the receiver determines that the amplitude of an input signal is positive, this signal is mapped to digital logic “0”; if the receiver determines that the amplitude of an input signal is negative, the signal is mapped to digital logic “1”.
- each set of delayed input signal is multiplied by the positive/negative sign corresponding to the same set of data.
- the positive/negative sign of each set of delay signal is consistent with the positive/negative sign obtained by the positive/negative sign determining module 13 A, such that the amplitude of each set of adjusted input data outputted by the adjusting module is positive.
- the optimum decoded result obtained is all digital logic “0” (corresponding to the all-zero path in the trellis diagram).
- the secondary Viterbi decoder 14 performs a non-typical Viterbi decoding process on the adjusted input data outputted by the adjusting module 13 .
- One main difference between the so-called non-typical Viterbi decoding process and a conventional Viterbi process is that, based on the premise that the foregoing predetermined path serves as the optimum path, the secondary Viterbi decoder 14 identifies information associated with another path.
- the another path may be a second optimum path. Details of an operation mechanism of the secondary Viterbi decoder 14 are given with reference to the exemplary trellis diagrams in FIG. 4(A) and FIG. 4(B) .
- the size of a symbol is 2 bits
- the constraint length of a convolutional code is 3
- the code rate is 1/2.
- the four nodes at the leftmost column correspond to two bits b 0 b 1 in the first symbol
- the four nodes at the second column from the left correspond to a bit b 1 in the first symbol and a bit b 2 in the second symbol
- the four nodes at the third column from the left correspond to two bits b 2 b 3 in the second symbol, and so forth.
- the secondary Viterbi decoder 14 first may identify the metric of each branch in the trellis diagram, and select a survival path (to be referred to as a non-zero survival path), which is traced back from the nodes N 1 to N 7 of the all-zero path by an add-compare-select process in Viterbi technologies and different from the all-zero path.
- FIG. 4(A) depicts the attributes of the branches determined by the secondary Viterbi decoder 14 .
- a dotted connecting line represents a lower survival probability of the branch
- a solid connecting line represents a high survival probability of the branch
- a thin line represents that the branch is totally excluded from all of the considered survival paths
- a solid line represents that the branch is a part of a particular survival path.
- the secondary Viterbi decoder 14 calculates respective accumulated branch metric differences between the non-zero survival path and the all-zero path for the nodes N 1 to N 7 .
- a smaller accumulated branch metric difference means that the non-zero survival path is more ideal.
- the path having a smaller accumulated branch metric difference is better than a path having a larger accumulated branch metric difference.
- the secondary Viterbi decoder 14 respectively calculates 7 accumulated branch metric differences of the nodes N 1 to N 7 , and determines a preferred non-zero survival path from the 7 branch paths.
- FIG. 3 shows a partial diagram of an exemplary secondary Viterbi decoder 14 according to an embodiment of the present invention.
- the secondary Viterbi decoder 14 includes a recording unit 14 A, a comparing unit 14 B, an updating unit 14 C, and a symbol establishing unit 14 D.
- the symbol establishing unit 14 D sequentially establishes a plurality of symbol records and a metric index corresponding to each of the symbol records.
- the updating unit 14 C selectively updates the symbol records and the metric indices stored in the recording unit 14 A according to a comparison result of the comparing unit 14 B.
- the symbol records in the recording unit 14 A are outputted by the secondary Viterbi decoder 14 to serve as a plurality of symbols used by the secondary result generating module 15 .
- Detailed operations of the circuit units are given below with reference of the exemplary trellis diagram in FIG. 4(B) .
- the comparing unit 14 B sequentially receives the accumulated branch metric differences of the nodes N 1 to N 7 . Each time a latest accumulated branch metric difference is received, the comparing unit 14 B compares the latest accumulated branch metric difference with the currently recorded metric index to determine which is better. If the determination result of the comparing unit 14 B indicates that the latest accumulated branch metric difference is better than the currently recorded metric index, the updating unit 14 C updates the currently recorded symbol record and metric index according to the latest accumulated branch metric difference and the corresponding survival path.
- the symbol establishing unit 14 D determines whether to establish a new set of symbol record and a metric index corresponding to the symbol record in the recording unit 14 A. When it is determined that a new set of symbol record and a metric index corresponding to the symbol record are to be established in the recording unit 14 A, the symbol establishing unit 14 D establishes a new set of symbol record and a metric index corresponding to the symbol record in the recording unit 14 A according to the latest accumulated branch metric difference and the corresponding survival path.
- the comparing unit 14 B receives another latest accumulated branch metric difference, so as to respectively calculate and compare the branch paths of the nodes.
- the symbol establishing unit 14 D determines whether to establish a new set of symbol record and a metric index corresponding to the symbol record.
- the symbol establishing determines that a new set of symbol record and a metric index corresponding to the symbol record are to be established in the recording module 14 .
- all of the first metric index m 01 , the second metric index m 23 and the third metric index is updated to m 45 to 3.
- the secondary Viterbi decoder 14 may gradually establish and update multiple sets of symbol records, and output these symbol records after having obtained an appropriate number of symbol records.
- the main function of the secondary Viterbi decoder 14 is to select a survival path, which is traced back from each node of a predetermined path and different from the predetermined path, and to calculate an accumulated branch metric difference from the selected survival path and the predetermined path to the node to accordingly determine a plurality of symbols.
- a survival path that is traced back from each of the nodes N 1 to N 7 from the all-zero path and different from the predetermined path is selected as a better and adjusted second optimum survival path.
- the secondary result generating module 14 generates a set of secondary decoded results according to the plurality of symbols generated by the secondary Viterbi decoder 14 and the set of main decoded results generated by the main Viterbi decoder 11 .
- the secondary result generating module 15 includes a second delay line 15 A and an adder 15 B.
- a delay amount provided by the second delay line 15 A is set to be substantially equal to the total delay caused by the four blocks including the re-encoder 12 , the positive/negative sign determining unit 13 A, the multiplier 13 C and the secondary Viterbi decoder 14 .
- each set of delayed main decoded results are added with the symbol corresponding to the same set of data in the adder 15 B.
- the main decoded results generated by the main Viterbi decoder 11 and the secondary decoded results generated by the secondary Viterbi decoder 15 are both provided to a subsequent circuit (e.g., a Reed-Solomon decoder) for further use.
- a subsequent circuit e.g., a Reed-Solomon decoder
- the performance of a subsequent circuit can be enhanced (e.g., increasing the probability of successful decoding).
- the secondary circuit e.g., a Reed-Solomon decoder
- Viterbi decoder 14 of the present invention may be designed to generate more than one set of second optimum symbols that may be respectively combined with the main decoded results, and to provide more than two sets of decoded results to a subsequent circuit based on the required decoding reliability and cost considerations.
- all or a part of the above function modules may be implemented by various control and processing platforms, including fixed and programmable logic circuits, including programmable logic gate arrays, application specific integrated circuits (ASIC), microcontrollers, microprocessors, digital signal processors (DSP), or other necessary circuits.
- ASIC application specific integrated circuits
- DSP digital signal processors
- the recording unit 14 A may include one or multiple volatile or non-volatile memory devices, e.g., random access semiconductor memories, read-only memories (ROM), magnetic and/or optical memories, and flash memories.
- FIG. 5 shows a flowchart of a Viterbi decoding method according to another embodiment of the present invention.
- a Viterbi decoding process is performed on input data to generate a set of main decoded results.
- a convolutional encoding process is performed on the set of main decoded results to generate a set of re-encoded results.
- the input data is adjusted according to the set of re-encoded results to generate adjusted input data substantially corresponding to a predetermined path in a Viterbi trellis diagram.
- step S 54 an add-compare-select process is performed on the adjusted input data according to the Viterbi trellis diagram to select a survival path, which is traced back from a plurality of nodes of the predetermined path and different from the predetermined path, and an accumulated branch metric difference from the selected survival path and the predetermined path to the node is calculated to accordingly determine a plurality of symbols.
- step S 55 a set of secondary decoded results are generated according to the plurality of symbols and the set of main decoded results.
- FIG. 6 further shows details of a partial process of step S 54 .
- step S 54 A a latest accumulated branch metric difference is received.
- step S 54 B it is determined whether the latest accumulated branch metric difference is better than a currently recorded metric index.
- step S 54 D is performed when the determination result of step S 54 B is negative, or else step S 54 C is performed when the determination result of step S 54 B is affirmative.
- step S 54 C a symbol record and a metric index of the currently recorded symbol record are updated according to the latest accumulated branch metric difference and the corresponding survival path.
- step S 54 D it is determined whether a new set of symbol record and a metric index corresponding to the symbol record are to be established.
- step S 54 D When the determination result of step S 54 D is negative, the process returns to step S 54 A, followed by the subsequent steps.
- step S 54 E is performed, in which a new set of symbol record and a metric index corresponding to the symbol record are established. The process then returns to step S 54 A.
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| TW104115236 | 2015-05-13 | ||
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| TW104115236A TWI569589B (en) | 2015-05-13 | 2015-05-13 | Viterbi decoding apparatus and viterbi decoding method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5966412A (en) * | 1997-06-30 | 1999-10-12 | Thomson Consumer Electronics, Inc. | Apparatus and method for processing a Quadrature Amplitude Modulated (QAM) signal |
| US20010008022A1 (en) * | 1999-12-28 | 2001-07-12 | Yoshiro Kokuryo | Coder with error correction, decoder with error correction and data transmission apparatus using the coder and decoder |
| US20060161834A1 (en) * | 2005-01-17 | 2006-07-20 | Toshiyuki Saito | Error correction decoder |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5469452A (en) * | 1991-09-27 | 1995-11-21 | Qualcomm Incorporated | Viterbi decoder bit efficient chainback memory method and decoder incorporating same |
| TW351904B (en) * | 1996-04-09 | 1999-02-01 | Thomson Multimedia Sa | Digital packet data trellis decoder |
| US6094465A (en) * | 1997-03-21 | 2000-07-25 | Qualcomm Incorporated | Method and apparatus for performing decoding of CRC outer concatenated codes |
| WO1999055010A1 (en) * | 1998-04-17 | 1999-10-28 | Tiernan Communications, Inc. | Method and apparatus for tcm decoding using qpsk viterbi decoder |
| JPH11340840A (en) * | 1998-05-28 | 1999-12-10 | Fujitsu Ltd | Mobile communication terminal and transmission bit rate determination method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5966412A (en) * | 1997-06-30 | 1999-10-12 | Thomson Consumer Electronics, Inc. | Apparatus and method for processing a Quadrature Amplitude Modulated (QAM) signal |
| US20010008022A1 (en) * | 1999-12-28 | 2001-07-12 | Yoshiro Kokuryo | Coder with error correction, decoder with error correction and data transmission apparatus using the coder and decoder |
| US20060161834A1 (en) * | 2005-01-17 | 2006-07-20 | Toshiyuki Saito | Error correction decoder |
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| TW201640834A (en) | 2016-11-16 |
| US20160337082A1 (en) | 2016-11-17 |
| TWI569589B (en) | 2017-02-01 |
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