US9588543B2 - Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device - Google Patents

Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device Download PDF

Info

Publication number
US9588543B2
US9588543B2 US14/139,951 US201314139951A US9588543B2 US 9588543 B2 US9588543 B2 US 9588543B2 US 201314139951 A US201314139951 A US 201314139951A US 9588543 B2 US9588543 B2 US 9588543B2
Authority
US
United States
Prior art keywords
data
peripheral device
signal
instruction
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/139,951
Other versions
US20140189415A1 (en
Inventor
Tsung-Huang Chen
Li-Chun Tu
Wen-Chi Chao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IN2014MU2013 external-priority patent/IN2013MU02014A/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US14/139,951 priority Critical patent/US9588543B2/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAO, WEN-CHI, CHEN, TSUNG-HUANG, TU, LI-CHUN
Publication of US20140189415A1 publication Critical patent/US20140189415A1/en
Priority to US14/905,971 priority patent/US20160154454A1/en
Application granted granted Critical
Publication of US9588543B2 publication Critical patent/US9588543B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Definitions

  • the present invention relates to communication technology between a processor and a peripheral device.
  • a media peripheral interface, an electronic device with the media peripheral interface, and a communication method between a processor and a peripheral device are disclosed.
  • a media peripheral interface for communication between a processor and a peripheral device.
  • the media peripheral interface comprises a clock port, a plurality of data I/Os, and a data strobe port.
  • the clock port is operative to transfer a clock signal to the peripheral device.
  • the data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device.
  • the data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device.
  • command information transferred via the data I/Os is captured.
  • data transferred via the data I/Os are captured.
  • an electronic device In another exemplary embodiment of the invention, an electronic device is shown.
  • the disclosed electronic device comprises the processor and the peripheral device which are coupled to each other via the media peripheral interface.
  • the processor, the media peripheral interface and the peripheral device are enclosed in a single module (or a single package) as a system-in-package.
  • a communication method between a processor and a peripheral device comprises the following steps: transferring a clock signal to the peripheral device; transferring a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device; utilizing the clock signal to capture the command information transferred from the processor to the peripheral device; and, in accordance with rising edges and falling edges of the data strobe signal, capturing the data transferred between the processor and the peripheral device.
  • FIG. 1 is a block diagram depicting an electronic device 100 in accordance with an exemplary embodiment of the invention
  • FIGS. 2A-2B , FIGS. 3A-3C and FIG. 4 show waveforms of the signals transferred via the ports and I/Os of the disclosed media peripheral interface 106 in accordance with different exemplary embodiments of the invention.
  • FIG. 5 is a flowchart depicting the communication method between a processor and a peripheral device.
  • FIG. 1 is a block diagram depicting an electronic device 100 in accordance with an exemplary embodiment of the invention.
  • the electronic device 100 comprises a processor 102 , a peripheral device 104 and a media peripheral interface 106 .
  • the media peripheral interface 106 may be implemented as a hardware module and is coupled between the processor 102 and the peripheral device 104 for communication therebetween.
  • the processor 102 and the media peripheral interface 106 form a host 108 , and the host 108 is operative to communicate with the peripheral device 104 .
  • the processor 102 , the peripheral device 104 and the media peripheral interface 106 are enclosed in a single module (or a package) as a system-in-package (SIP) 110 (but not limited thereto).
  • the peripheral device 104 may be a PSRAM, a FLASH memory, and so on.
  • the media peripheral interface 106 may work as a display interface, a camera interface and so on.
  • the media peripheral interface 106 comprises a clock port CLK, a plurality of data I/Os (labeled DATA), a data strobe port DQS, and a data mask signal port DM.
  • the clock port CLK is operative to transfer a clock signal (also designated as CLK) to the peripheral device 104 .
  • the data I/Os (DATA) are provided for command transfer to the peripheral device 104 and for data transfer to and from the peripheral device 104 .
  • the data strobe port DQS is operative to transfer a data strobe signal (also designated as DQS) to or from the peripheral device 104 according to an instruction that the processor 102 issues to the peripheral device 104 .
  • a data strobe signal DQS is transferred ‘to’ the peripheral device 104 when a ‘write’ instruction is issued by processor 102
  • a data strobe signal DQS is transferred ‘from’ the peripheral device 104 when a ‘read’ instruction is issued by the processor 102
  • the data mask signal port DM is optional (e.g., depending on the bit number of the data I/Os DATA), and operative to transfer a data mask signal (also designated as DM) to the peripheral device 104 to mask particular transition edges of the data strobe signal DQS accordingly.
  • the command information transferred via the data I/Os DATA is captured.
  • data transferred via the data I/Os DATA they are captured according to rising edges and falling edges of the data strobe signal DQS when the data mask signal DM is disabled.
  • the data transferred via the data I/Os Data is captured according to particular transition edges (e.g. only H ⁇ L transition edges, or, only L ⁇ H transition edges) of the data strobe signal DQS.
  • the clock port CLK is not limited to providing a single connection terminal. In some embodiments, the clock port CLK may provide a differential pair and the clock signal CLK may be a differential signal. Further, note that the data strobe port DQS is not limited to providing a single connection terminal. In some embodiments, the data strobe port DQS may provide a differential pair and the data strobe signal DQS may be a differential signal.
  • FIGS. 2A-2B , FIGS. 3A-3C and FIG. 4 show waveforms of the signals transferred via the ports and I/Os of the disclosed media peripheral interface 106 in accordance with different exemplary embodiments of the invention.
  • the signal CE# is a chip enable signal.
  • the number of data I/Os (DATA0 ⁇ 3) is four and no data mask signal DM is utilized. Four bits are captured each time.
  • Command information (instruction+read/write address) is first transferred via the data I/Os DATA0 ⁇ 3 in an instruction phase (phase INST) and an address phase (phase ADDRESS) and is captured according to the rising edges and the falling edges of the clock signal CLK. Later, in a data phase, data transferred via the data I/Os DATA0 ⁇ 3 are captured according to rising edges and falling edges of the data strobe signal DQS.
  • the media peripheral interface 106 of the invention captures data according to the disclosed data strobe signal DQS.
  • DQS data strobe signal
  • the number of data I/Os (DATA0 ⁇ 7) is eight, quite large for byte addressing.
  • a data mask port DM is provided by the media peripheral interface 106 and a data mask signal DM is transferred thereon, operative to mask particular transition edges (masking all H ⁇ L transitions, or, masking all L ⁇ H transitions) of the data strobe signal DQS.
  • the data mask signal DM is disabled in the DATA PHASE. Data transferred via the data I/Os DATA0 ⁇ 7 are captured according to rising edges and falling edges of the data strobe signal DQS.
  • the data strobe signal DQS may be enabled in other exemplary embodiments and only H ⁇ L transition edges or only L ⁇ H transition edges of the data strobe signal DQS are utilized in capturing the data transferred via the data I/Os DATA0 ⁇ 7.
  • the command information (instruction+read/write address) is captured by only particular transition edges (e.g. only H ⁇ L transition edges, or, only L ⁇ H transition edges) of the clock signal CLK rather than by all transition edges of the clock signal CLK.
  • a blank area (e.g., between the data capture intervals) of the data strobe signal DQS is utilized to transfer the instruction.
  • the number of data I/Os (DATA0 ⁇ 3) is four and no data mask signal DM is utilized, and, the instruction that the processor 102 issues to the peripheral device 104 is transferred by the data strobe port DQS.
  • the instruction and the read/write address are separately transferred by the data strobe port DQS and the data I/Os DATA0 ⁇ 3 and are simultaneously captured according to the rising edges and the falling edges of the clock signal CLK. Less clock cycles are required when command information is captured.
  • the number of data I/Os is expended to eight (DATA0 ⁇ 7) in comparison with the exemplary embodiment of FIG. 3A and, accordingly, a data mask port DM is provided in the media peripheral interface 106 .
  • the instruction and the read/write address are separately transferred by the data strobe port DQS and the data I/Os DATA0 ⁇ 7 and are simultaneously captured according to the rising edges and the falling edges of the clock signal CLK.
  • the instruction transferred by the data strobe port DQS and the read/write address transferred by the data I/Os are captured by only particular transition edges (e.g. only H ⁇ L transition edges, or, only L ⁇ H transition edges) of the clock signal CLK rather than by all transition edges of the clock signal CLK.
  • the instruction transferred by the data strobe port DQS and the read/write address transferred by the data I/Os DATA0 ⁇ 7 are captured according to only the rising edges of the clock signal CLK.
  • the peripheral device 104 may operate in a wrap mode to be read/written in a wrap-around fashion.
  • a wrap mode For example, when the peripheral device 104 is a FLASH memory, a block-wise read/write service may be requested. The pages of the requested block may be transferred in a wrap-around fashion, thus, completing the read/write operation on the requested block.
  • the peripheral device 104 operates in a wrap mode, the data transferred via the data I/Os DATA of the media peripheral interface 106 is transferred in a wrap-around fashion.
  • FIG. 4 shows how the data is transferred in the wrap-around fashion, wherein 32 data is requested.
  • phase ‘INST-FADDRESS’ data D 8 is read out from the peripheral device 104 first and then data D 9 to data D 31 are read out sequentially and then data D 0 -D 8 are returned subsequently.
  • the media peripheral interface 106 may be switched to work as a conventional serial peripheral interface (SPI) when the data rate of the peripheral device 104 is quite low.
  • SPI serial peripheral interface
  • the data strobe port DQS and the data mask signal port DM may be left unused.
  • FIG. 5 is a flowchart depicting the communication method.
  • a clock signal CLK is transferred to the peripheral device, and, a data strobe signal DQS is transferred to or from the peripheral device according to an instruction that the processor issues to the peripheral device.
  • the clock signal CLK is utilized to capture the command information transferred from the processor to the peripheral device and, in accordance with rising edges and falling edges of the data strobe signal DQS, the data transferred between the processor and the peripheral device is captured.
  • a blank area of DQS is utilized to transfer the instruction that the processor issues to the peripheral device, such that the read/write address corresponding to the instruction is transferred by a path which is different from that of the instruction.
  • the instruction transferred in the blank area of the data strobe signal DQS and the read/write address that the processor transfers to the peripheral device may be captured simultaneously according to rising edges and falling edges (or, only the particular transition edges) of the clock signal CLK.
  • a data mask signal is further transferred to the peripheral device to mask particular transition edges of the data strobe signal accordingly.
  • the peripheral device when the peripheral device operates in a wrap mode, the data is transferred in a wrap-around fashion.
  • the disclosed communication method may be implemented by firmware executed by a controller.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

A media peripheral interface for communication between a processor and a peripheral device includes a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 61/746,337 filed Dec. 27, 2012, the entirety of which is incorporated by reference herein. Further, this Application claims priority of India Patent Application No. 2014/MUM/2013, filed on Jun. 13, 2013, the entirety of which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to communication technology between a processor and a peripheral device.
Description of the Related Art
Nowadays, electronic devices are increasingly complex and a higher data rate is required. A simple but high-speed communication protocol between a processor and a peripheral device is called for.
BRIEF SUMMARY OF THE INVENTION
A media peripheral interface, an electronic device with the media peripheral interface, and a communication method between a processor and a peripheral device are disclosed.
In an exemplary embodiment of the invention, a media peripheral interface for communication between a processor and a peripheral device is disclosed. The media peripheral interface comprises a clock port, a plurality of data I/Os, and a data strobe port. The clock port is operative to transfer a clock signal to the peripheral device. The data I/Os are provided for command transfer to the peripheral device and for data transfer to and from the peripheral device. The data strobe port is operative to transfer a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device. According to the clock signal, command information transferred via the data I/Os is captured. According to rising edges and falling edges of the data strobe signal, data transferred via the data I/Os are captured.
In another exemplary embodiment of the invention, an electronic device is shown. In addition to the disclosed media peripheral interface, the disclosed electronic device comprises the processor and the peripheral device which are coupled to each other via the media peripheral interface. In an exemplary embodiment, the processor, the media peripheral interface and the peripheral device are enclosed in a single module (or a single package) as a system-in-package.
In another exemplary embodiment of the invention, a communication method between a processor and a peripheral device is shown, which comprises the following steps: transferring a clock signal to the peripheral device; transferring a data strobe signal to or from the peripheral device according to an instruction that the processor issues to the peripheral device; utilizing the clock signal to capture the command information transferred from the processor to the peripheral device; and, in accordance with rising edges and falling edges of the data strobe signal, capturing the data transferred between the processor and the peripheral device.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 is a block diagram depicting an electronic device 100 in accordance with an exemplary embodiment of the invention;
FIGS. 2A-2B, FIGS. 3A-3C and FIG. 4 show waveforms of the signals transferred via the ports and I/Os of the disclosed media peripheral interface 106 in accordance with different exemplary embodiments of the invention; and
FIG. 5 is a flowchart depicting the communication method between a processor and a peripheral device.
 DETAILED DESCRIPTION OF THE INVENTION
The following description shows several exemplary embodiments of carrying out the invention. The description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 is a block diagram depicting an electronic device 100 in accordance with an exemplary embodiment of the invention. The electronic device 100 comprises a processor 102, a peripheral device 104 and a media peripheral interface 106. The media peripheral interface 106 may be implemented as a hardware module and is coupled between the processor 102 and the peripheral device 104 for communication therebetween. The processor 102 and the media peripheral interface 106 form a host 108, and the host 108 is operative to communicate with the peripheral device 104. In some exemplary embodiments, the processor 102, the peripheral device 104 and the media peripheral interface 106 are enclosed in a single module (or a package) as a system-in-package (SIP) 110 (but not limited thereto). The peripheral device 104 may be a PSRAM, a FLASH memory, and so on. In addition to implementing a PSRAM interface or a FLASH interface, the media peripheral interface 106 may work as a display interface, a camera interface and so on.
As shown in FIG. 1, the media peripheral interface 106 comprises a clock port CLK, a plurality of data I/Os (labeled DATA), a data strobe port DQS, and a data mask signal port DM. The clock port CLK is operative to transfer a clock signal (also designated as CLK) to the peripheral device 104. The data I/Os (DATA) are provided for command transfer to the peripheral device 104 and for data transfer to and from the peripheral device 104. The data strobe port DQS is operative to transfer a data strobe signal (also designated as DQS) to or from the peripheral device 104 according to an instruction that the processor 102 issues to the peripheral device 104. For example, a data strobe signal DQS is transferred ‘to’ the peripheral device 104 when a ‘write’ instruction is issued by processor 102, and, a data strobe signal DQS is transferred ‘from’ the peripheral device 104 when a ‘read’ instruction is issued by the processor 102. The data mask signal port DM is optional (e.g., depending on the bit number of the data I/Os DATA), and operative to transfer a data mask signal (also designated as DM) to the peripheral device 104 to mask particular transition edges of the data strobe signal DQS accordingly. According to the clock signal CLK, the command information transferred via the data I/Os DATA is captured. As for data transferred via the data I/Os DATA, they are captured according to rising edges and falling edges of the data strobe signal DQS when the data mask signal DM is disabled. When the data mask signal DM is enabled, the data transferred via the data I/Os Data is captured according to particular transition edges (e.g. only H→L transition edges, or, only L→H transition edges) of the data strobe signal DQS. Note that the clock port CLK is not limited to providing a single connection terminal. In some embodiments, the clock port CLK may provide a differential pair and the clock signal CLK may be a differential signal. Further, note that the data strobe port DQS is not limited to providing a single connection terminal. In some embodiments, the data strobe port DQS may provide a differential pair and the data strobe signal DQS may be a differential signal.
FIGS. 2A-2B, FIGS. 3A-3C and FIG. 4 show waveforms of the signals transferred via the ports and I/Os of the disclosed media peripheral interface 106 in accordance with different exemplary embodiments of the invention. The signal CE# is a chip enable signal.
Referring to FIG. 2A, in this exemplary embodiment, the number of data I/Os (DATA0˜3) is four and no data mask signal DM is utilized. Four bits are captured each time. Command information (instruction+read/write address) is first transferred via the data I/Os DATA0˜3 in an instruction phase (phase INST) and an address phase (phase ADDRESS) and is captured according to the rising edges and the falling edges of the clock signal CLK. Later, in a data phase, data transferred via the data I/Os DATA0˜3 are captured according to rising edges and falling edges of the data strobe signal DQS. In comparison with a conventional serial peripheral interface (SPI, wherein the data is captured according to the clock signal of the host side) the media peripheral interface 106 of the invention captures data according to the disclosed data strobe signal DQS. Thus, data reliability is dramatically improved especially for high-frequency applications.
Referring to FIG. 2B, in this exemplary embodiment, the number of data I/Os (DATA0˜7) is eight, quite large for byte addressing. Thus, a data mask port DM is provided by the media peripheral interface 106 and a data mask signal DM is transferred thereon, operative to mask particular transition edges (masking all H→L transitions, or, masking all L→H transitions) of the data strobe signal DQS. In FIG. 2B, the data mask signal DM is disabled in the DATA PHASE. Data transferred via the data I/Os DATA0˜7 are captured according to rising edges and falling edges of the data strobe signal DQS. However, according to user requirements, the data strobe signal DQS may be enabled in other exemplary embodiments and only H→L transition edges or only L→H transition edges of the data strobe signal DQS are utilized in capturing the data transferred via the data I/Os DATA0˜7.
Further, in some embodiments, the command information (instruction+read/write address) is captured by only particular transition edges (e.g. only H→L transition edges, or, only L→H transition edges) of the clock signal CLK rather than by all transition edges of the clock signal CLK.
Further, instead of using the data I/Os to transfer the instruction that the processor 102 issues to the peripheral device 104, a blank area (e.g., between the data capture intervals) of the data strobe signal DQS is utilized to transfer the instruction. Referring to FIG. 3A, in this exemplary embodiment, the number of data I/Os (DATA0˜3) is four and no data mask signal DM is utilized, and, the instruction that the processor 102 issues to the peripheral device 104 is transferred by the data strobe port DQS. In such an embodiment, the instruction and the read/write address are separately transferred by the data strobe port DQS and the data I/Os DATA0˜3 and are simultaneously captured according to the rising edges and the falling edges of the clock signal CLK. Less clock cycles are required when command information is captured.
Referring to the exemplary embodiment of FIG. 3B, the number of data I/Os is expended to eight (DATA0˜7) in comparison with the exemplary embodiment of FIG. 3A and, accordingly, a data mask port DM is provided in the media peripheral interface 106. In the eight bits data interface, the instruction and the read/write address are separately transferred by the data strobe port DQS and the data I/Os DATA0˜7 and are simultaneously captured according to the rising edges and the falling edges of the clock signal CLK.
Note that in some embodiments the instruction transferred by the data strobe port DQS and the read/write address transferred by the data I/Os are captured by only particular transition edges (e.g. only H→L transition edges, or, only L→H transition edges) of the clock signal CLK rather than by all transition edges of the clock signal CLK. As shown in FIG. 3C, the instruction transferred by the data strobe port DQS and the read/write address transferred by the data I/Os DATA0˜7 are captured according to only the rising edges of the clock signal CLK.
In some exemplary embodiments, the peripheral device 104 may operate in a wrap mode to be read/written in a wrap-around fashion. For example, when the peripheral device 104 is a FLASH memory, a block-wise read/write service may be requested. The pages of the requested block may be transferred in a wrap-around fashion, thus, completing the read/write operation on the requested block. When the peripheral device 104 operates in a wrap mode, the data transferred via the data I/Os DATA of the media peripheral interface 106 is transferred in a wrap-around fashion. FIG. 4 shows how the data is transferred in the wrap-around fashion, wherein 32 data is requested. According to the read address captured in a command information phase (phase ‘INST-FADDRESS’), data D8 is read out from the peripheral device 104 first and then data D9 to data D31 are read out sequentially and then data D0-D8 are returned subsequently.
In some exemplary embodiments, the media peripheral interface 106 may be switched to work as a conventional serial peripheral interface (SPI) when the data rate of the peripheral device 104 is quite low. When being switched to be a conventional SPI, the data strobe port DQS and the data mask signal port DM may be left unused.
Further, a communication method between a processor and a peripheral device is disclosed. FIG. 5 is a flowchart depicting the communication method. In step S502, a clock signal CLK is transferred to the peripheral device, and, a data strobe signal DQS is transferred to or from the peripheral device according to an instruction that the processor issues to the peripheral device. In step S504, the clock signal CLK is utilized to capture the command information transferred from the processor to the peripheral device and, in accordance with rising edges and falling edges of the data strobe signal DQS, the data transferred between the processor and the peripheral device is captured.
In some exemplary embodiments, a blank area of DQS is utilized to transfer the instruction that the processor issues to the peripheral device, such that the read/write address corresponding to the instruction is transferred by a path which is different from that of the instruction. The instruction transferred in the blank area of the data strobe signal DQS and the read/write address that the processor transfers to the peripheral device may be captured simultaneously according to rising edges and falling edges (or, only the particular transition edges) of the clock signal CLK.
In some exemplary embodiments, a data mask signal is further transferred to the peripheral device to mask particular transition edges of the data strobe signal accordingly.
Further, when the peripheral device operates in a wrap mode, the data is transferred in a wrap-around fashion.
In some exemplary embodiments, the disclosed communication method may be implemented by firmware executed by a controller.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (17)

What is claimed is:
1. A media peripheral interface coupled between a processor and a peripheral device, comprising:
a clock port, transferring a clock signal to the peripheral device;
data I/Os, for transferring a read/write address that the processor issues to the peripheral device and for transferring data to and from the peripheral device; and
a data strobe port, for transferring an instruction that the processor issues to the peripheral device and transferring a data strobe signal to or from the peripheral device according to the instruction,
wherein:
the instruction is transferred via the data strobe port and captured according to the clock signal when the read/write address is transferred via the data I/Os; and
the data transferred via the data I/Os are captured according to rising edges and falling edges of the data strobe signal.
2. The media peripheral interface as claimed in claim 1, wherein the instruction transferred via the data strobe port and the read/write address transferred via the data I/Os are captured according to rising edges and falling edges of the clock signal.
3. The media peripheral interface as claimed in claim 1, wherein the instruction transferred via the data strobe port and the read/write address transferred via the data I/Os are captured according to particular transition edges of the clock signal.
4. The media peripheral interface as claimed in claim 1, further comprising:
a data mask signal port, for transferring a data mask signal to the peripheral device,
wherein, in accordance with the data mask signal, particular transition edges of the data strobe signal are masked.
5. The media peripheral interface as claimed in claim 1, wherein:
when the peripheral device operates in a wrap mode, the data transferred via the data I/Os are transferred in a wrap-around fashion.
6. The media peripheral interface as claimed in claim 1, wherein:
the clock port is implemented as a differential pair and the clock signal is a differential signal.
7. The media peripheral interface as claimed in claim 1, wherein:
the data strobe port is implemented as a differential pair and the data strobe signal is a differential signal.
8. The media peripheral interface as claimed in claim 1, which is a PSRAM interface, a FLASH interface, a display interface, or a camera interface.
9. An electronic device comprising:
the media peripheral interface as claimed in claim 1; and
the processor and the peripheral device coupled to each other via the media peripheral interface.
10. The electronic device as claimed in claim 9, wherein the processor, the media peripheral interface and the peripheral device are enclosed in a single module as a system-in-package.
11. A communication method between a processor and a peripheral device, comprising:
transferring a clock signal to the peripheral device;
capturing an instruction and a read/write address transferred from the processor to the peripheral device according to the clock signal, wherein transferring the read/write address via data I/Os and using a blank area of a data strobe signal to transfer the instruction that the processor issues to the peripheral device, thereby the read/write address corresponding to the instruction is transferred by a path which is different from that of the instruction;
transferring the data strobe signal to or from the peripheral device according to the instruction; and
capturing data transferred between the processor and the peripheral device via the data I/Os according to rising edges and falling edges of the data strobe signal.
12. The communication method as claimed in claim 11, wherein the instruction and the read/write address are captured simultaneously according to rising edges and falling edges of the clock signal.
13. The communication method as claimed in claim 11, wherein the instruction and the read/write address are captured simultaneously according to particular transition edges of the clock signal.
14. The communication method as claimed in claim 11, further comprising:
transferring a data mask signal to the peripheral device to mask particular transition edges of the data strobe signal in accordance with the data mask signal.
15. The communication method as claimed in claim 11, further comprising:
transferring the data transferred in a wrap-around fashion when the peripheral device operates in a wrap mode.
16. The communication method as claimed in claim 11, wherein:
the clock signal is a differential signal.
17. The communication method as claimed in claim 11, for communication between the processor and a PSRAM, a FLASH, a display or a camera.
US14/139,951 2012-12-27 2013-12-24 Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device Active 2035-01-20 US9588543B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/139,951 US9588543B2 (en) 2012-12-27 2013-12-24 Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device
US14/905,971 US20160154454A1 (en) 2013-12-24 2015-06-05 Storage apparatus, storage system, storage apparatus controlling method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201261746337P 2012-12-27 2012-12-27
IN2014MU2013 IN2013MU02014A (en) 2012-12-27 2013-06-13
IN2014/MUM/2013 2013-06-13
US14/139,951 US9588543B2 (en) 2012-12-27 2013-12-24 Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device

Publications (2)

Publication Number Publication Date
US20140189415A1 US20140189415A1 (en) 2014-07-03
US9588543B2 true US9588543B2 (en) 2017-03-07

Family

ID=49563470

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/139,951 Active 2035-01-20 US9588543B2 (en) 2012-12-27 2013-12-24 Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device

Country Status (4)

Country Link
US (1) US9588543B2 (en)
EP (1) EP2750046B1 (en)
CN (1) CN103399839B (en)
TW (1) TWI506443B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6790435B2 (en) * 2016-04-20 2020-11-25 ソニー株式会社 Receivers, transmitters, and communication systems, as well as signal receiving, signaling, and communication methods.
US10936046B2 (en) * 2018-06-11 2021-03-02 Silicon Motion, Inc. Method for performing power saving control in a memory device, associated memory device and memory controller thereof, and associated electronic device
US11681352B2 (en) * 2019-11-26 2023-06-20 Adesto Technologies Corporation Standby current reduction in memory devices
JP7424825B2 (en) * 2019-12-26 2024-01-30 ファナック株式会社 I/O signal information display system

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1710664A (en) 2004-06-18 2005-12-21 乐金电子(中国)研究开发中心有限公司 Method for prolonging use time of portable device through controlling memory
CN1710519A (en) 2004-06-18 2005-12-21 乐金电子(中国)研究开发中心有限公司 Self-refreshing electricity consumption method of saving SDRAM through spare data
CN1815464A (en) 2005-01-31 2006-08-09 富士通株式会社 Synchronous data transfer circuit, computer system and memory system
CN1838103A (en) 2005-03-22 2006-09-27 英特尔公司 System and method to reduce memory latency in microprocessor systems
US20070288778A1 (en) 2006-06-09 2007-12-13 Broadcom Corporation Method for managing and controlling the low power modes for an integrated circuit device
CN101221542A (en) 2007-10-30 2008-07-16 北京时代民芯科技有限公司 External memory storage interface
US20090231936A1 (en) * 2004-01-27 2009-09-17 Micron Technology, Inc. Memory device having strobe terminals with multiple functions
CN101727412A (en) 2008-10-30 2010-06-09 恩益禧电子股份有限公司 Memory interface and operating method of memory interface
CN101884033A (en) 2007-08-31 2010-11-10 提琴存储器公司 Memory power management
CN102262593A (en) 2010-05-25 2011-11-30 联发科技股份有限公司 Data movement engine and memory control method
US20120089770A1 (en) * 2006-12-12 2012-04-12 Kim Yeon-Ho Flash memory devices with high data transmission rates and memory systems including such flash memory devices
US20140133240A1 (en) 2012-11-13 2014-05-15 Lite-On It Corporation Solid state storage device with sleep control circuit
US20150242271A1 (en) 2007-03-29 2015-08-27 Violin Memory Inc Memory management system and method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2023998A1 (en) * 1989-11-13 1991-05-14 Thomas F. Lewis Apparatus and method for guaranteeing strobe separation timing
US6145039A (en) * 1998-11-03 2000-11-07 Intel Corporation Method and apparatus for an improved interface between computer components
KR100800665B1 (en) * 2001-09-29 2008-02-01 삼성전자주식회사 Devices for the interface between the central processing unit and peripherals
US6894531B1 (en) * 2003-05-22 2005-05-17 Altera Corporation Interface for a programmable logic device
TWI433150B (en) * 2009-07-27 2014-04-01 Sunplus Technology Co Ltd Apparatus and method for data strobe and timing variation detection of an sdram interface
US8751714B2 (en) * 2010-09-24 2014-06-10 Intel Corporation Implementing quickpath interconnect protocol over a PCIe interface

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090231936A1 (en) * 2004-01-27 2009-09-17 Micron Technology, Inc. Memory device having strobe terminals with multiple functions
CN1710519A (en) 2004-06-18 2005-12-21 乐金电子(中国)研究开发中心有限公司 Self-refreshing electricity consumption method of saving SDRAM through spare data
CN1710664A (en) 2004-06-18 2005-12-21 乐金电子(中国)研究开发中心有限公司 Method for prolonging use time of portable device through controlling memory
CN1815464A (en) 2005-01-31 2006-08-09 富士通株式会社 Synchronous data transfer circuit, computer system and memory system
US7711973B2 (en) 2005-01-31 2010-05-04 Fujitsu Limited Synchronous data transfer circuit, computer system and memory system
CN1838103A (en) 2005-03-22 2006-09-27 英特尔公司 System and method to reduce memory latency in microprocessor systems
US7779188B2 (en) 2005-03-22 2010-08-17 Intel Corporation System and method to reduce memory latency in microprocessor systems connected with a bus
US20070288778A1 (en) 2006-06-09 2007-12-13 Broadcom Corporation Method for managing and controlling the low power modes for an integrated circuit device
US20120089770A1 (en) * 2006-12-12 2012-04-12 Kim Yeon-Ho Flash memory devices with high data transmission rates and memory systems including such flash memory devices
US20150242271A1 (en) 2007-03-29 2015-08-27 Violin Memory Inc Memory management system and method
CN101884033A (en) 2007-08-31 2010-11-10 提琴存储器公司 Memory power management
CN101221542A (en) 2007-10-30 2008-07-16 北京时代民芯科技有限公司 External memory storage interface
CN101727412A (en) 2008-10-30 2010-06-09 恩益禧电子股份有限公司 Memory interface and operating method of memory interface
US8271824B2 (en) 2008-10-30 2012-09-18 Renesas Electronics Corporation Memory interface and operating method of memory interface
US20110296095A1 (en) 2010-05-25 2011-12-01 Mediatek Inc. Data movement engine and memory control methods thereof
CN102262593A (en) 2010-05-25 2011-11-30 联发科技股份有限公司 Data movement engine and memory control method
US20140133240A1 (en) 2012-11-13 2014-05-15 Lite-On It Corporation Solid state storage device with sleep control circuit

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
"Synchronous Dynamic Random-Access Memory;" Wikipedia; Sep. 23, 2014; pp. 1-18.
DDR3 SDRAM Standard; JEDEC Solid State Technology Association; Jul. 2010; pp. 1-226.
Micron, "General DDR SDRAM Functionality" TN4605.p65-Rev. A; Micron DesignLine, vol. 8, Issue 3 (3Q99); 2001. *
PCI Local Bus Specification Passage; Dec. 18, 1998; pp. 1-12.
PCI Local Bus Specification; Dec. 18, 1998; pp. 1-322.

Also Published As

Publication number Publication date
CN103399839B (en) 2018-10-26
EP2750046A2 (en) 2014-07-02
TWI506443B (en) 2015-11-01
EP2750046A3 (en) 2014-10-15
TW201426316A (en) 2014-07-01
CN103399839A (en) 2013-11-20
US20140189415A1 (en) 2014-07-03
EP2750046B1 (en) 2015-09-30

Similar Documents

Publication Publication Date Title
US8055808B2 (en) Semiconductor memory device and control method for semiconductor memory device
US7013359B1 (en) High speed memory interface system and method
US7171508B2 (en) Dual port memory with asymmetric inputs and outputs, device, system and method
US8028144B2 (en) Memory module with reduced access granularity
US8364881B2 (en) Flash memory controller and methods of programming and reading flash memory devices using the controller
US9025409B2 (en) Memory buffers and modules supporting dynamic point-to-point connections
US10095614B2 (en) Memory controller and accessing system utilizing the same
US8738827B2 (en) Circuits and methods for providing communication between a memory card and a host device
US9588543B2 (en) Media peripheral interface, electronic device with media peripheral interface, and communication method between processor and peripheral device
CN104956440A (en) Apparatus, method and system for determining a reference voltage of a memory
JP2007011788A (en) Memory card and its host device
US7761668B2 (en) Processor architecture having multi-ported memory
US10884956B2 (en) I/O bus shared memory system
JP2005293573A (en) Integrated circuit card system, memory card and control method thereof
TWI717884B (en) Control system of accessing data for memory cards and method thereof
US20110072168A1 (en) Data transfer system with different operating modes
US11626149B2 (en) SPI NOR memory with optimized read and program operation
US9377957B2 (en) Method and apparatus for latency reduction
TWI816046B (en) Control system of accessing data for memory storage and method thereof
CN201435077Y (en) Circuit structure supporting multiple SD card slave device access
JP2007226380A (en) Non-volatile memory card
JP2008242601A (en) Memory card control device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MEDIATEK INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, TSUNG-HUANG;TU, LI-CHUN;CHAO, WEN-CHI;REEL/FRAME:031869/0101

Effective date: 20131023

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8