US9317646B2 - Masks formed based on integrated circuit layout design having cell that includes extended active region - Google Patents

Masks formed based on integrated circuit layout design having cell that includes extended active region Download PDF

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US9317646B2
US9317646B2 US14/826,553 US201514826553A US9317646B2 US 9317646 B2 US9317646 B2 US 9317646B2 US 201514826553 A US201514826553 A US 201514826553A US 9317646 B2 US9317646 B2 US 9317646B2
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Prior art keywords
region
cell
gate strip
active region
masks
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US14/826,553
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US20150356225A1 (en
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Lee-Chung Lu
Li-Chun Tien
Hui-Zhong ZHUANG
Chang-Yu Wu
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LU, LEE-CHUNG, TIEN, LI-CHUN, WU, CHANG-YU, ZHUANG, Hui-zhong
Publication of US20150356225A1 publication Critical patent/US20150356225A1/en
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Priority to US15/956,629 priority patent/USRE49331E1/en
Priority to US18/055,067 priority patent/US20230072698A1/en
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    • G06F17/5072—
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • Standard cells having fixed functions are widely used.
  • Standard cells are typically pre-designed and saved in cell libraries.
  • the standard cells are retrieved from the cell libraries and placed into desired locations. Routing is then performed to connect the standard cells with each other and with other circuits on the chip.
  • Pre-defined design rules are followed when placing the standard cells into the desired locations. For example, spacing the active regions apart from the cell boundaries, so that when neighboring cells are abutted, the active regions of neighboring cells will not adjoin each other. The precaution associated with the active regions; however, incurs area penalties. The reserved space between the active regions and the cell boundaries results in a significant increase in the areas of the standard cells. In addition, because the active regions are spaced apart from the cell boundaries, when the standard cells are placed abutting each other, the active regions will not be joined, even if some of the active regions in the neighboring cells need to be electrically coupled. The spaced apart active regions have to be electrically connected using metal lines. The performance of the resulting device is worse than if the active regions are continuous.
  • Layout patterns and configurations can affect yield and design performance of the standard cells.
  • FIGS. 1A and 1B are a first transistor region and a second transistor region of a single standard cell in accordance with one or more embodiments;
  • FIGS. 2A through 2C are layouts of different arrangements and types of standard cells in accordance with one or more embodiments.
  • FIG. 3 is a layout of a pair of standard cells having continuous active regions in accordance with one or more embodiments
  • FIG. 4 is a layout of a single standard cell having an extended active region in accordance with one or more embodiments
  • FIG. 5 is a layout of a single standard cell having an extended active region and dummy poly biasing in accordance with one or more embodiments
  • FIG. 6 is a layout of a single standard cell having an extended active region with active region biasing and separate dummy poly biasing in accordance with one or more embodiments;
  • FIG. 7 is a layout of a single standard cell having an extended active region and biasing at a drain region in accordance with one or more embodiments.
  • FIG. 8 is a layout of a single standard cell having an extended active region and biasing at a source region in accordance with one or more embodiments.
  • FIG. 9 is a layout of a pair of standard cells in accordance with one or more embodiments.
  • an integrated circuit is manufactured by performing one or more lithographic processes, growing processes, etching processes, or other processes based on a set of masks.
  • a set of masks is fabricated based on an integrated circuit design layout that depicts a plurality of features of the integrated circuit in various component layers.
  • FIGS. 1A and 1B are a first transistor region and a second transistor region of a single standard cell in accordance with one or more embodiments.
  • portions of a single standard cell 100 are depicted separately for facilitating the illustration of the present disclosure.
  • the present disclosure is not limited to generating layouts of inverter cells and is applicable for generating layouts of other types of circuits including, for example, AND, OR, XOR, XNOR gates, and the like.
  • the standard inverter cell 100 includes upper and lower boundaries 100 a and 100 b and left and right cell boundaries 100 c and 100 d as indicated by the dashed lines shown in FIGS. 1A and 1B .
  • the first transistor region (e.g., a PMOS transistor 110 ) of the standard inverter cell 100 as shown in FIG. 1A includes a p-type active region 114 (as indicated by the dimensions X a by Y a ) including source region 114 a (as indicated by the dimensions X b by Y a ) and drain region 114 b (as indicated by the dimensions X c by Y a ) and a first portion of an active gate strip 115 as a gate G 1 .
  • the source and drain regions 114 a and 114 b are on opposite sides of gate G 1 . Further, dummy gate strips 116 are placed at left and right boundaries 100 c and 100 d . Dummy gate strips 116 do not act as a gate to any transistors. Each dummy gate strip 116 has only one-half a width inside the standard inverter cell 100 and the other half is outside the standard inverter cell 100 . Active gate strip 115 and dummy gate strips 116 are parallel to each other and equally spaced apart. Gate strip 115 and dummy gate strips 116 are formed of polysilicon or other conductive materials such as metals, metal alloys and metal silicides. Further, a VDD power supply line is connected to source region 114 a by a metal connection (e.g., a metal line 117 and contact plug 118 ), and supplies a voltage level VDD.
  • a metal connection e.g., a metal line 117 and contact plug 118
  • the second transistor region (e.g., an NMOS transistor 119 ) of the standard inverter cell 100 as shown in FIG. 1B includes a second portion of gate strip 115 as a gate G 2 and an n-type active region (i.e., oxide-dimensioned region (OD)) 120 (as indicated by the dimensions X a by Y b ) including a source region 120 a (as indicated by the dimensions X b by Y b ) and a drain region 120 b (as indicated by the dimensions X c by Y b ).
  • Active regions 114 and 120 are spaced apart from each other by an isolation region 122 (e.g., a shallow trench isolation (STI) region) as shown in FIG. 1B .
  • an isolation region 122 e.g., a shallow trench isolation (STI) region
  • a VSS power supply line is connected to source region 120 a by a metal connection (e.g., a metal line 127 and a contact plug 128 ) and supplies a ground level or negative voltage level.
  • Gate strip 115 includes a gate pitch P which is measured from an edge of gate strip 115 to a respective edge of a neighboring gate strip (e.g., dummy gate 116 ).
  • a width “w” of standard inverter cell 100 is defined by a measurement from left to right boundaries 100 c and 100 d .
  • the cell width is also referred to as the cell pitch.
  • a length of standard inverter cell 100 is defined by the measurement from upper to lower boundaries 100 a and 100 b .
  • edges of active regions 114 and 120 are spaced apart from the right and left boundaries 100 c and 100 d by a distance a as shown in FIG. 1A .
  • FIGS. 2A through 2C are layouts of different arrangements and types of standard cells in accordance with one or more embodiments.
  • the single standard inverter cell 100 (on the left of reference line R 1 ) abuts another standard inverter cell 130 (on the right of reference line R 1 ).
  • the standard cell 130 includes the same features as that of standard inverter cell 100 and therefore a detailed description thereof is omitted.
  • the adjoining cells 100 and 130 are adjoined at their side boundaries (i.e., the right side boundary 100 d of cell 100 and the left side boundary 130 c of the cell 130 ).
  • a dummy gate strip 116 is at the adjoining cell boundaries 100 d and 130 c , between the active regions 114 of the PMOS transistor regions 110 of both cells 100 and 130 and between the active regions 120 of the NMOS transistor regions 119 of both cells 100 and 130 .
  • drain regions 114 b and 120 b of cell 100 are disposed to the left of the dummy gate strip 116
  • source regions 114 a and 120 a of cell 130 are disposed to the right of the dummy gate strip 116 .
  • the active regions 114 of the cells 100 and 130 are discrete (i.e., spaced apart from each other), and the active regions 120 of cells 100 and 130 are also discrete.
  • active regions of adjoining cells are continuous in FIG. 2B as explained below, to prevent area penalties, i.e., increased area usage, during a layout design process, and to increase gate density and the long OD region (LOD) effect.
  • LOD effect refers the improved performance and reduced process variation as a result of a long, continuous OD region in comparison with a shorter, discrete OD region.
  • standard inverter cells 100 (on the left of reference line R 2 ) and 130 (on the right of reference line R 2 ) are adjoined at side boundaries 100 d and 130 c .
  • the standard inverter cells 100 and 130 include a continuous active region 132 (as indicated by the dimensions X 1 by Y 1 ) in the PMOS transistor regions 110 and a continuous active region 134 (as indicated by dimensions X 1 by Y 2 ) in the NMOS transistor 119 .
  • the dummy gate strip 116 and adjacent drain region 114 b of the standard inverter cell 100 and adjacent source region 114 a of the standard inverter cell 130 together form a parasitic transistor (e.g., transistor P 1 in the PMOS transistor region 110 ).
  • the dummy gate strip 116 and adjacent drain region 120 b and adjacent source region 120 a together form a parasitic transistor (e.g., transistor N 1 in the NMOS transistor region 119 ).
  • unwanted capacitance exists between the parasitic transistors P 1 and N 1 because of these parasitic transistors P 1 and N 1 are within close proximity to each other. The resulting unwanted capacitance affects circuit performance.
  • FIG. 2C is another example of a standard cell 140 according to one or more embodiments.
  • the standard cell 140 is similar to the standard cell 100 ; however, in standard cell 140 , an extended active region 142 (as indicated by the dimensions X 2 by Y 3 ) is included in the PMOS transistor region 110 and an extended active region 143 (as indicated by the dimensions X 2 by Y 4 ) is included in the NMOS transistor region 119 .
  • the standard cell 140 is referred to as a poly on OD edge (PODE) cell.
  • PODE poly on OD edge
  • extended active regions 142 and 143 extend over an edge of dummy gate strips 116 at side boundaries 140 c and 140 d of the standard cell 140 .
  • a blank region 149 exists between the two cells such that the cells have discrete OD regions similar to that shown in FIG. 1B .
  • the use of PODE type standard cells resolve this issue by extending the poly to the OD edge.
  • the OD is recessed at the edge and other layers need to be placed above the recess, the device performance is potentially degraded.
  • a poly is used to block the OD edge. If two PODE type standard cells abut each other, the devices should be separated (as depicted in FIG. 9 ).
  • FIG. 3 is a layout of an example variation of a combination of the standard cells 100 (on the left of reference line R 3 ) and 130 (on the right of reference line R 3 ) as similarly shown in FIG. 2B .
  • the layout of FIG. 3 includes continuous active regions 132 and 134 and is used for illustrating an operation for eliminating parasitic capacitance within the continuous active regions 132 and 134 .
  • a poly cut is performed (as depicted by box A) to separate upper and lower portions of the dummy gate strip 116 .
  • the upper portion i.e., the portion above box A
  • the lower portion i.e., the portion below box A
  • the electrical connection to VDD and VSS is made by metal connections to turn off the parasitic transistors (P 1 and N 1 ).
  • poly metal VDD connection is used to electrically couple the VDD power supply line to a metal line 117 at the source region 114 a of the second standard cell 130 .
  • poly metal VSS connection is used to electrically couple the VSS power supply line to a metal line 127 at the source region 120 a of the second standard cell 130 .
  • FIG. 4 is a layout of a standard cell 150 having an oxide diffusion (OD) extension layers including extended active regions 152 and 154 in accordance with one or more embodiments.
  • the standard cell 150 in FIG. 4 is a single standard cell having OD extension layers and is similar to the standard cell 100 shown in FIGS. 1A and 1B except in the PMOS transistor region 110 includes three additional gate strips ( 115 b , 115 c , and 115 d ) and an additional source region 114 c .
  • the gate strip 115 b is between and functions as the gate electrode for the drain region 114 b and the additional source region 114 c .
  • the gate strip 115 c can be used for connection with another device or as a dummy gate strip.
  • the standard cell 150 includes the first gate strip 115 a , the second gate strip 115 b , and the third gate strip 115 c are in parallel with each other.
  • Upper and lower boundaries 150 a and 150 b are at opposite ends of the standard cell 150
  • left and right side boundaries 150 c and 150 d are parallel to the plurality of gate strips 115 a , 115 b and 115 c .
  • the PMOS transistor 110 comprises a first portion of the first gate strip 115 a as a first gate G 1 and a first portion of the second gate strip 115 b as a second gate G 2 .
  • the PMOS transistor 110 further includes the extended active region 152 (as indicated by dimensions X 3 by Y 5 ) including a first source region 114 a and a first drain region 114 b at opposite sides of the first gate G 1 , and the first drain region 114 b and a second source region 114 c at opposite sides of the second gate G 2 .
  • the active region 152 is extended by two gate pitches (i.e., one gate pitch on each side). The use of an extended active region allows the metal (M 0 ) poly to be positioned in the active OD region and therefore there is no degradation regarding the device size.
  • Standard cell 150 further includes a NMOS transistor 119 including a second portion of the first gate strip 115 a as a third gate G 3 and a second portion of the second gate strip 115 b as a fourth gate G 4 , the second extended active region 154 (as indicated by dimensions X 3 by Y 6 ) includes a third source region 120 a opposite first source region 114 a of the PMOS transistor 110 and adjacent to third gate G 3 , and a second drain region 120 b opposite second source region 114 c and adjacent to fourth gate G 4 .
  • First and second source regions 114 a and 114 c of PMOS transistor 110 are connected with VDD power supply line by metal connections (e.g., metal line 117 and contact plugs 118 ). Further, third source region 120 a of NMOS transistor 119 is connected with VSS power supply line by a metal connection (e.g., metal line 127 and contact plug 128 ).
  • first gate strip 115 a is an active gate strip and second gate strip 116 is a dummy gate strip. Further, according to one or more embodiments, gate strip 115 d is a non-operative floating poly and gate strip 115 c is an active gate strip for other devices (not shown).
  • first drain region 114 b of PMOS transistor 110 is electrically connected with second drain region 120 b of NMOS transistor 119 by a metal connection.
  • FIG. 5 is a layout of a single standard cell 160 having extended active regions and dummy poly biasing to prevent parasitic capacitance in accordance with one or more embodiments.
  • the layout of standard cell 160 is similar to the layout of standard cell 150 shown in FIG. 5 .
  • PMOS transistor 110 and NMOS transistor 119 include extended active region 161 (as indicated by dimensions X 4 and Y 7 ) and extended active region 162 (as indicated by dimensions X 4 and Y 8 ) which are extended by one gate pitch at one side (e.g., a left side boundary 160 c ) of standard cell 160 instead of both sides.
  • extended active region 161 as indicated by dimensions X 4 and Y 7
  • extended active region 162 as indicated by dimensions X 4 and Y 8
  • the active regions 161 and 162 are not extended beyond the third source region 114 c of PMOS transistor 110 of standard cell 160 and second drain region 120 b of NMOS transistor 119 . Therefore, third source region 114 c of PMOS transistor 110 of standard cell 160 and second drain region 120 b of NMOS transistor 119 align near the side cell boundary 160 d.
  • Standard cell 160 further includes a third gate strip 115 c parallel to first gate strip 115 a and includes an upper portion as a fifth gate G 5 and a lower portion as a sixth gate G 6 .
  • First and second dummy source regions 164 and 165 corresponding to PMOS transistor 110 and NMOS transistor 119 are defined within the extension of the active regions 161 and 162 .
  • First and second dummy source regions 164 and 165 are disposed to the left of the third gate strip 115 c and adjacent to a side boundary (e.g., the left side boundary 160 c ).
  • VDD power supply line is electrically connected to first dummy source region 164 and VSS power supply line is electrically connected to second dummy source region 165 by metal connections.
  • Use of first and second dummy source regions 164 and 165 at boundary 160 c prevents the generation of parasitic capacitance, and protects the source region 114 a and the LOD effect as a result of the extended active regions 161 and 162 .
  • third gate strip 115 c is a dummy gate strip and is biased at VDD power supply line or the VSS power supply line.
  • some or all layouts of standard cells for NOT, AND, OR, XOR, or XNOR gates, and/or the like are arranged in a manner that the source regions are positioned adjacent to the cell side boundaries, such as side boundaries 160 c and 160 d of cell 160 . Accordingly, generation of parasitic transistors at the side boundaries 160 c and 160 d when abutting another cell is prevented.
  • FIG. 6 is a layout of single standard cell 160 ′ with active region biasing and separate dummy poly biasing in accordance with one or more embodiments.
  • a poly cut is performed (as depicted box “A”) at fifth gate G 5 and sixth gate G 6 and fifth gate G 5 is electrically connected with VDD power supply line by a metal connection, and sixth gate G 6 is electrically connected with VSS power supply line by a metal connection.
  • fifth gate G 5 and the sixth gate G 6 are cut, and the fifth gate G 5 which corresponds to a parasitic transistor, is connected to power, the connection of fifth gate G 5 to power disables the fifth gate G 5 Further, sixth gate G 6 is connected to ground and is not used as a transistor.
  • FIG. 7 is a layout of a single standard cell 170 having extended active region 171 (as indicated by dimensions X 5 by Y 9 ) and extended active region 172 (as indicated by dimensions X 5 by Y 10 ) in accordance with one or more embodiments. Active regions 171 and 172 are extended by one gate pitch at a right side of standard cell 170 . Some of the elements within standard cell 170 are the same as standard cell 160 therefore a description thereof is omitted.
  • third gate strip 115 c is parallel to and adjacent to second gate strip 115 b and includes the upper portion as the fifth gate G 5 and the lower portion as the sixth gate G 6 .
  • First and second dummy source regions 174 and 175 are defined within the corresponding active regions 171 and 172 and are disposed to the right of the gate strip 115 c along a side boundary 170 d of standard cell 170 .
  • First dummy source region 174 and second source region 114 c are at opposite sides of fifth gate G 5
  • second dummy source region 175 and second drain region 120 b are at opposite sides of sixth gate G 6 .
  • VDD power supply line is electrically connected to first dummy source region 174 and VSS power supply line is electrically connected to second dummy source region 175 .
  • source region 175 is electrically coupled to VSS (i.e., also referred to as biasing performed at a drain side of NMOS transistor 119 ).
  • Third gate strip 115 c is connected with VSS power supply line to effectively disable the parasitic transistor formed by the drain region 120 b , the source region 175 , and the gate G 6 .
  • FIG. 8 is a layout of a single standard cell 180 having an extended active region 181 (as indicated by dimensions X 6 by Y 11 ) and an extended active region 182 (as indicated by dimensions X 6 by Y 12 ) and performing biasing at a source region in accordance with one or more embodiments.
  • standard cell 180 is an inverter, for example, and includes first, second and third gate strips 115 a , 115 b and 115 c parallel with each other.
  • a PMOS transistor 110 includes a first portion of first gate strip 115 a as a first gate G 1 , first extended active region 181 including a first source region 114 a and a first drain region 114 b at opposite sides of first gate G 1 , a first portion of second gate strip 115 b as a second gate G 2 , a first dummy source region 184 and first source region 114 a disposed opposite second gate G 2 , and a first portion of third gate strip 115 c as a third gate G 3 and a second dummy source region 185 and first drain region 114 b disposed opposite third gate G 3 .
  • Standard cell 180 further includes NMOS transistor 119 including a second portion of first gate strip 115 a as a fourth gate G 4 , second extended active region 182 including a second source region 120 a opposite first source region 114 a and second source region 120 a and second drain region 120 b disposed at opposite sides of the fourth gate G 4 .
  • a second portion of second gate strip 115 b as a fifth gate G 5 , and a third dummy source region 186 and second source region 120 a are disposed at opposite sides of the fifth gate G 5
  • a second portion of third gate strip 120 c as a sixth gate G 6 , the second drain region 120 b and a third drain region 120 c are disposed at opposite sides of sixth gate G 6 .
  • First dummy source region 184 , second dummy source region 185 and first source region 114 a are connected with VDD power supply line by metal connections, and third dummy source region 186 , and second source region 120 a are connected with the VSS power supply line by metal connections.
  • first, second and third source regions 184 , 185 and 186 are disposed along the side boundaries 180 c and 180 d of standard cell 180 . Biasing is performed on the source side of the standard cell 180 .
  • the first, second and third drain regions 114 b , 120 b and 120 c are connected together and act as an output of the inverter.
  • FIG. 9 illustrates a pair of PODE type standard cells according to one or more embodiments.
  • two PODE type standard cells 140 on the left of reference line R 4
  • 190 on the right of reference line R 4
  • Standard cell 190 has cell boundaries 190 a , 190 b , 190 c and 190 d and further comprises the same components as that of standard cell 140 , therefore a detailed description of standard cell 190 is omitted to avoid unnecessary repetition.
  • blank region 149 exists between the two cells such that the cells have discrete OD regions similar to that shown in FIG. 2A .
  • One or more embodiments include a set of masks corresponding to an integrated circuit layout.
  • the integrated circuit layout comprises a first cell comprising a first transistor region and a second transistor region, and a second cell comprising a third transistor region and a fourth transistor region.
  • the first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region.
  • the set of masks is formed based on the integrated circuit layout.
  • One or more embodiments include a set of masks corresponding to an integrated circuit layout.
  • the integrated circuit layout comprises a first cell comprising a first active region and a first side boundary, and a second cell comprising a second active region and a second side boundary along the first side boundary.
  • the integrated circuit layout further comprises a first gate strip in the first cell parallel to the first side boundary and overlying the first active region, a second gate strip in the second cell parallel to the second side boundary and overlying the second active region, and a dummy gate strip parallel to and between the first gate strip and the second gate strip, wherein the dummy gate strip overlies at least one of the first active region or the second active region.
  • the set of masks is formed based on the integrated circuit layout.
  • One or more embodiments include a set of masks corresponding to an integrated circuit layout.
  • the integrated circuit layout comprises a first cell comprising a first active region and a first side boundary, and a second cell comprising a second active region and a second side boundary along the first side boundary.
  • the integrated circuit layout further comprises a first gate strip in the first cell parallel to the first side boundary and overlying the first active region, a second gate strip in the second cell parallel to the second side boundary and overlying the second active region, a blank region abutting the first active region and the second active region, a first dummy gate strip in the first cell between the first gate strip and the first side boundary, and overlying the first active region and the blank region, and a second dummy gate strip in the second cell between the second gate strip and the second side boundary, and overlying the second active region and the blank region.
  • the set of masks is formed based on the integrated circuit layout.

Abstract

A set of masks corresponds to an integrated circuit layout. The integrated circuit layout includes a first cell having a first transistor region and a second transistor region, and a second cell having a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.

Description

PRIORITY CLAIM
The present application is a divisional of U.S. application Ser. No. 13/779,104, filed Feb. 27, 2013, which claims the priority of U.S. Provisional Application No. 61/747,751, filed Dec. 31, 2012, which are incorporated herein by reference in their entireties.
BACKGROUND
In the design of integrated circuits, particularly digital circuits, standard cells having fixed functions are widely used. Standard cells are typically pre-designed and saved in cell libraries. During an integrated circuit design process, the standard cells are retrieved from the cell libraries and placed into desired locations. Routing is then performed to connect the standard cells with each other and with other circuits on the chip.
Pre-defined design rules are followed when placing the standard cells into the desired locations. For example, spacing the active regions apart from the cell boundaries, so that when neighboring cells are abutted, the active regions of neighboring cells will not adjoin each other. The precaution associated with the active regions; however, incurs area penalties. The reserved space between the active regions and the cell boundaries results in a significant increase in the areas of the standard cells. In addition, because the active regions are spaced apart from the cell boundaries, when the standard cells are placed abutting each other, the active regions will not be joined, even if some of the active regions in the neighboring cells need to be electrically coupled. The spaced apart active regions have to be electrically connected using metal lines. The performance of the resulting device is worse than if the active regions are continuous.
Layout patterns and configurations can affect yield and design performance of the standard cells.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGS. 1A and 1B are a first transistor region and a second transistor region of a single standard cell in accordance with one or more embodiments;
FIGS. 2A through 2C are layouts of different arrangements and types of standard cells in accordance with one or more embodiments.
FIG. 3 is a layout of a pair of standard cells having continuous active regions in accordance with one or more embodiments;
FIG. 4 is a layout of a single standard cell having an extended active region in accordance with one or more embodiments;
FIG. 5 is a layout of a single standard cell having an extended active region and dummy poly biasing in accordance with one or more embodiments;
FIG. 6 is a layout of a single standard cell having an extended active region with active region biasing and separate dummy poly biasing in accordance with one or more embodiments;
FIG. 7 is a layout of a single standard cell having an extended active region and biasing at a drain region in accordance with one or more embodiments; and
FIG. 8 is a layout of a single standard cell having an extended active region and biasing at a source region in accordance with one or more embodiments.
FIG. 9 is a layout of a pair of standard cells in accordance with one or more embodiments.
 DETAILED DESCRIPTION
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.
One or more embodiments of integrated circuit design layouts including standard cells are shown. Throughout the various views and embodiments, like reference numbers are used to designate like elements. In some embodiments, an integrated circuit is manufactured by performing one or more lithographic processes, growing processes, etching processes, or other processes based on a set of masks. In some embodiments, a set of masks is fabricated based on an integrated circuit design layout that depicts a plurality of features of the integrated circuit in various component layers.
FIGS. 1A and 1B are a first transistor region and a second transistor region of a single standard cell in accordance with one or more embodiments.
In FIGS. 1A and 1B, according to one or more embodiments, portions of a single standard cell 100 (e.g., an inverter cell) are depicted separately for facilitating the illustration of the present disclosure. The present disclosure is not limited to generating layouts of inverter cells and is applicable for generating layouts of other types of circuits including, for example, AND, OR, XOR, XNOR gates, and the like.
The standard inverter cell 100 includes upper and lower boundaries 100 a and 100 b and left and right cell boundaries 100 c and 100 d as indicated by the dashed lines shown in FIGS. 1A and 1B. The first transistor region (e.g., a PMOS transistor 110) of the standard inverter cell 100 as shown in FIG. 1A includes a p-type active region 114 (as indicated by the dimensions Xa by Ya) including source region 114 a (as indicated by the dimensions Xb by Ya) and drain region 114 b (as indicated by the dimensions Xc by Ya) and a first portion of an active gate strip 115 as a gate G1. The source and drain regions 114 a and 114 b are on opposite sides of gate G1. Further, dummy gate strips 116 are placed at left and right boundaries 100 c and 100 d. Dummy gate strips 116 do not act as a gate to any transistors. Each dummy gate strip 116 has only one-half a width inside the standard inverter cell 100 and the other half is outside the standard inverter cell 100. Active gate strip 115 and dummy gate strips 116 are parallel to each other and equally spaced apart. Gate strip 115 and dummy gate strips 116 are formed of polysilicon or other conductive materials such as metals, metal alloys and metal silicides. Further, a VDD power supply line is connected to source region 114 a by a metal connection (e.g., a metal line 117 and contact plug 118), and supplies a voltage level VDD.
The second transistor region (e.g., an NMOS transistor 119) of the standard inverter cell 100 as shown in FIG. 1B includes a second portion of gate strip 115 as a gate G2 and an n-type active region (i.e., oxide-dimensioned region (OD)) 120 (as indicated by the dimensions Xa by Yb) including a source region 120 a (as indicated by the dimensions Xb by Yb) and a drain region 120 b (as indicated by the dimensions Xc by Yb). Active regions 114 and 120 are spaced apart from each other by an isolation region 122 (e.g., a shallow trench isolation (STI) region) as shown in FIG. 1B. A VSS power supply line is connected to source region 120 a by a metal connection (e.g., a metal line 127 and a contact plug 128) and supplies a ground level or negative voltage level. Gate strip 115 includes a gate pitch P which is measured from an edge of gate strip 115 to a respective edge of a neighboring gate strip (e.g., dummy gate 116).
A width “w” of standard inverter cell 100 is defined by a measurement from left to right boundaries 100 c and 100 d. The cell width is also referred to as the cell pitch. A length of standard inverter cell 100 is defined by the measurement from upper to lower boundaries 100 a and 100 b. In one or more embodiments, edges of active regions 114 and 120 are spaced apart from the right and left boundaries 100 c and 100 d by a distance a as shown in FIG. 1A.
FIGS. 2A through 2C are layouts of different arrangements and types of standard cells in accordance with one or more embodiments.
In FIG. 2A, the single standard inverter cell 100 (on the left of reference line R1) abuts another standard inverter cell 130 (on the right of reference line R1). The standard cell 130 includes the same features as that of standard inverter cell 100 and therefore a detailed description thereof is omitted. The adjoining cells 100 and 130 are adjoined at their side boundaries (i.e., the right side boundary 100 d of cell 100 and the left side boundary 130 c of the cell 130). A dummy gate strip 116 is at the adjoining cell boundaries 100 d and 130 c, between the active regions 114 of the PMOS transistor regions 110 of both cells 100 and 130 and between the active regions 120 of the NMOS transistor regions 119 of both cells 100 and 130. As such, drain regions 114 b and 120 b of cell 100 are disposed to the left of the dummy gate strip 116, and source regions 114 a and 120 a of cell 130 are disposed to the right of the dummy gate strip 116.
Further, in one or more embodiments, the active regions 114 of the cells 100 and 130 are discrete (i.e., spaced apart from each other), and the active regions 120 of cells 100 and 130 are also discrete. In one or more embodiments, active regions of adjoining cells are continuous in FIG. 2B as explained below, to prevent area penalties, i.e., increased area usage, during a layout design process, and to increase gate density and the long OD region (LOD) effect. LOD effect refers the improved performance and reduced process variation as a result of a long, continuous OD region in comparison with a shorter, discrete OD region.
In FIG. 2B, standard inverter cells 100 (on the left of reference line R2) and 130 (on the right of reference line R2) are adjoined at side boundaries 100 d and 130 c. Further, the standard inverter cells 100 and 130 include a continuous active region 132 (as indicated by the dimensions X1 by Y1) in the PMOS transistor regions 110 and a continuous active region 134 (as indicated by dimensions X1 by Y2) in the NMOS transistor 119. The dummy gate strip 116 and adjacent drain region 114 b of the standard inverter cell 100 and adjacent source region 114 a of the standard inverter cell 130 together form a parasitic transistor (e.g., transistor P1 in the PMOS transistor region 110). The dummy gate strip 116 and adjacent drain region 120 b and adjacent source region 120 a together form a parasitic transistor (e.g., transistor N1 in the NMOS transistor region 119). As a result, unwanted capacitance exists between the parasitic transistors P1 and N1 because of these parasitic transistors P1 and N1 are within close proximity to each other. The resulting unwanted capacitance affects circuit performance.
FIG. 2C is another example of a standard cell 140 according to one or more embodiments. The standard cell 140 is similar to the standard cell 100; however, in standard cell 140, an extended active region 142 (as indicated by the dimensions X2 by Y3) is included in the PMOS transistor region 110 and an extended active region 143 (as indicated by the dimensions X2 by Y4) is included in the NMOS transistor region 119. The standard cell 140 is referred to as a poly on OD edge (PODE) cell. As shown, extended active regions 142 and 143 extend over an edge of dummy gate strips 116 at side boundaries 140 c and 140 d of the standard cell 140. When two PODE type standard cells are abutted (as depicted in FIG. 9), a blank region 149 exists between the two cells such that the cells have discrete OD regions similar to that shown in FIG. 1B. In cases with devices where the edge of the OD regions have some sinking or recess effect, the use of PODE type standard cells resolve this issue by extending the poly to the OD edge. When the OD is recessed at the edge and other layers need to be placed above the recess, the device performance is potentially degraded. Thus, in order to avoid the OD recess, a poly is used to block the OD edge. If two PODE type standard cells abut each other, the devices should be separated (as depicted in FIG. 9).
FIG. 3 is a layout of an example variation of a combination of the standard cells 100 (on the left of reference line R3) and 130 (on the right of reference line R3) as similarly shown in FIG. 2B. The layout of FIG. 3 includes continuous active regions 132 and 134 and is used for illustrating an operation for eliminating parasitic capacitance within the continuous active regions 132 and 134.
As shown in FIG. 3, the standard cells 100 and 130 are the same as shown in FIG. 2B, therefore a description of the elements is omitted. In one or more embodiments, a poly cut is performed (as depicted by box A) to separate upper and lower portions of the dummy gate strip 116. The upper portion (i.e., the portion above box A) is electrically connected to the VDD power supply line and the lower portion (i.e., the portion below box A) is electrically connected to the VSS power supply line. The electrical connection to VDD and VSS is made by metal connections to turn off the parasitic transistors (P1 and N1). For example, poly metal VDD connection is used to electrically couple the VDD power supply line to a metal line 117 at the source region 114 a of the second standard cell 130. Also, poly metal VSS connection is used to electrically couple the VSS power supply line to a metal line 127 at the source region 120 a of the second standard cell 130.) The use of the continuous active regions 132 and 134 provides the benefit of regaining gate density and the LOD effect.
FIG. 4 is a layout of a standard cell 150 having an oxide diffusion (OD) extension layers including extended active regions 152 and 154 in accordance with one or more embodiments. The standard cell 150 in FIG. 4 is a single standard cell having OD extension layers and is similar to the standard cell 100 shown in FIGS. 1A and 1B except in the PMOS transistor region 110 includes three additional gate strips (115 b, 115 c, and 115 d) and an additional source region 114 c. The gate strip 115 b is between and functions as the gate electrode for the drain region 114 b and the additional source region 114 c. The gate strip 115 c can be used for connection with another device or as a dummy gate strip.
The standard cell 150 includes the first gate strip 115 a, the second gate strip 115 b, and the third gate strip 115 c are in parallel with each other. Upper and lower boundaries 150 a and 150 b are at opposite ends of the standard cell 150, and left and right side boundaries 150 c and 150 d are parallel to the plurality of gate strips 115 a, 115 b and 115 c. The PMOS transistor 110 comprises a first portion of the first gate strip 115 a as a first gate G1 and a first portion of the second gate strip 115 b as a second gate G2.
The PMOS transistor 110 further includes the extended active region 152 (as indicated by dimensions X3 by Y5) including a first source region 114 a and a first drain region 114 b at opposite sides of the first gate G1, and the first drain region 114 b and a second source region 114 c at opposite sides of the second gate G2. The active region 152 is extended by two gate pitches (i.e., one gate pitch on each side). The use of an extended active region allows the metal (M0) poly to be positioned in the active OD region and therefore there is no degradation regarding the device size.
Standard cell 150 further includes a NMOS transistor 119 including a second portion of the first gate strip 115 a as a third gate G3 and a second portion of the second gate strip 115 b as a fourth gate G4, the second extended active region 154 (as indicated by dimensions X3 by Y6) includes a third source region 120 a opposite first source region 114 a of the PMOS transistor 110 and adjacent to third gate G3, and a second drain region 120 b opposite second source region 114 c and adjacent to fourth gate G4.
First and second source regions 114 a and 114 c of PMOS transistor 110 are connected with VDD power supply line by metal connections (e.g., metal line 117 and contact plugs 118). Further, third source region 120 a of NMOS transistor 119 is connected with VSS power supply line by a metal connection (e.g., metal line 127 and contact plug 128). In one or more embodiments, first gate strip 115 a is an active gate strip and second gate strip 116 is a dummy gate strip. Further, according to one or more embodiments, gate strip 115 d is a non-operative floating poly and gate strip 115 c is an active gate strip for other devices (not shown).
In one or more embodiments, first drain region 114 b of PMOS transistor 110 is electrically connected with second drain region 120 b of NMOS transistor 119 by a metal connection.
FIG. 5 is a layout of a single standard cell 160 having extended active regions and dummy poly biasing to prevent parasitic capacitance in accordance with one or more embodiments. The layout of standard cell 160 is similar to the layout of standard cell 150 shown in FIG. 5. Compared with standard cell 150, PMOS transistor 110 and NMOS transistor 119 include extended active region 161 (as indicated by dimensions X4 and Y7) and extended active region 162 (as indicated by dimensions X4 and Y8) which are extended by one gate pitch at one side (e.g., a left side boundary 160 c) of standard cell 160 instead of both sides. In the example depicted in FIG. 5, the active regions 161 and 162 are not extended beyond the third source region 114 c of PMOS transistor 110 of standard cell 160 and second drain region 120 b of NMOS transistor 119. Therefore, third source region 114 c of PMOS transistor 110 of standard cell 160 and second drain region 120 b of NMOS transistor 119 align near the side cell boundary 160 d.
Standard cell 160 further includes a third gate strip 115 c parallel to first gate strip 115 a and includes an upper portion as a fifth gate G5 and a lower portion as a sixth gate G6. First and second dummy source regions 164 and 165 corresponding to PMOS transistor 110 and NMOS transistor 119 are defined within the extension of the active regions 161 and 162. First and second dummy source regions 164 and 165 are disposed to the left of the third gate strip 115 c and adjacent to a side boundary (e.g., the left side boundary 160 c). VDD power supply line is electrically connected to first dummy source region 164 and VSS power supply line is electrically connected to second dummy source region 165 by metal connections. Use of first and second dummy source regions 164 and 165 at boundary 160 c prevents the generation of parasitic capacitance, and protects the source region 114 a and the LOD effect as a result of the extended active regions 161 and 162.
In one or more embodiments, third gate strip 115 c is a dummy gate strip and is biased at VDD power supply line or the VSS power supply line.
In some embodiments, some or all layouts of standard cells for NOT, AND, OR, XOR, or XNOR gates, and/or the like are arranged in a manner that the source regions are positioned adjacent to the cell side boundaries, such as side boundaries 160 c and 160 d of cell 160. Accordingly, generation of parasitic transistors at the side boundaries 160 c and 160 d when abutting another cell is prevented.
FIG. 6 is a layout of single standard cell 160′ with active region biasing and separate dummy poly biasing in accordance with one or more embodiments. In FIG. 6, compared with the standard cell 160 in FIG. 5, a poly cut is performed (as depicted box “A”) at fifth gate G5 and sixth gate G6 and fifth gate G5 is electrically connected with VDD power supply line by a metal connection, and sixth gate G6 is electrically connected with VSS power supply line by a metal connection. Since the fifth gate G5 and the sixth gate G6 are cut, and the fifth gate G5 which corresponds to a parasitic transistor, is connected to power, the connection of fifth gate G5 to power disables the fifth gate G5 Further, sixth gate G6 is connected to ground and is not used as a transistor.
FIG. 7 is a layout of a single standard cell 170 having extended active region 171 (as indicated by dimensions X5 by Y9) and extended active region 172 (as indicated by dimensions X5 by Y10) in accordance with one or more embodiments. Active regions 171 and 172 are extended by one gate pitch at a right side of standard cell 170. Some of the elements within standard cell 170 are the same as standard cell 160 therefore a description thereof is omitted.
In FIG. 7, third gate strip 115 c is parallel to and adjacent to second gate strip 115 b and includes the upper portion as the fifth gate G5 and the lower portion as the sixth gate G6. First and second dummy source regions 174 and 175 are defined within the corresponding active regions 171 and 172 and are disposed to the right of the gate strip 115 c along a side boundary 170 d of standard cell 170. First dummy source region 174 and second source region 114 c are at opposite sides of fifth gate G5, and second dummy source region 175 and second drain region 120 b are at opposite sides of sixth gate G6. VDD power supply line is electrically connected to first dummy source region 174 and VSS power supply line is electrically connected to second dummy source region 175. As shown in FIG. 7, in one or more embodiments, source region 175 is electrically coupled to VSS (i.e., also referred to as biasing performed at a drain side of NMOS transistor 119). Third gate strip 115 c is connected with VSS power supply line to effectively disable the parasitic transistor formed by the drain region 120 b, the source region 175, and the gate G6.
FIG. 8 is a layout of a single standard cell 180 having an extended active region 181 (as indicated by dimensions X6 by Y11) and an extended active region 182 (as indicated by dimensions X6 by Y12) and performing biasing at a source region in accordance with one or more embodiments.
In FIG. 8, standard cell 180 is an inverter, for example, and includes first, second and third gate strips 115 a, 115 b and 115 c parallel with each other. Upper and lower boundaries 180 a and 180 b on opposite ends of standard cell 180 and left and right side boundaries 180 c and 180 d parallel to first, second and third gates 115 a, 115 b and 115 c. A PMOS transistor 110 includes a first portion of first gate strip 115 a as a first gate G1, first extended active region 181 including a first source region 114 a and a first drain region 114 b at opposite sides of first gate G1, a first portion of second gate strip 115 b as a second gate G2, a first dummy source region 184 and first source region 114 a disposed opposite second gate G2, and a first portion of third gate strip 115 c as a third gate G3 and a second dummy source region 185 and first drain region 114 b disposed opposite third gate G3.
Standard cell 180 further includes NMOS transistor 119 including a second portion of first gate strip 115 a as a fourth gate G4, second extended active region 182 including a second source region 120 a opposite first source region 114 a and second source region 120 a and second drain region 120 b disposed at opposite sides of the fourth gate G4. A second portion of second gate strip 115 b as a fifth gate G5, and a third dummy source region 186 and second source region 120 a are disposed at opposite sides of the fifth gate G5, and a second portion of third gate strip 120 c as a sixth gate G6, the second drain region 120 b and a third drain region 120 c are disposed at opposite sides of sixth gate G6. First dummy source region 184, second dummy source region 185 and first source region 114 a are connected with VDD power supply line by metal connections, and third dummy source region 186, and second source region 120 a are connected with the VSS power supply line by metal connections. As shown, first, second and third source regions 184, 185 and 186 are disposed along the side boundaries 180 c and 180 d of standard cell 180. Biasing is performed on the source side of the standard cell 180. The first, second and third drain regions 114 b, 120 b and 120 c are connected together and act as an output of the inverter.
FIG. 9 illustrates a pair of PODE type standard cells according to one or more embodiments. As shown in FIG. 9, two PODE type standard cells 140 (on the left of reference line R4) and 190 (on the right of reference line R4) are provided. Details regarding the standard cell 140 are discussed above with regards to FIG. 2C. Standard cell 190 has cell boundaries 190 a, 190 b, 190 c and 190 d and further comprises the same components as that of standard cell 140, therefore a detailed description of standard cell 190 is omitted to avoid unnecessary repetition. As mentioned above, when PODE type standard cells 140 and 190 are abutted as shown in FIG. 9, blank region 149 exists between the two cells such that the cells have discrete OD regions similar to that shown in FIG. 2A.
One or more embodiments include a set of masks corresponding to an integrated circuit layout. The integrated circuit layout comprises a first cell comprising a first transistor region and a second transistor region, and a second cell comprising a third transistor region and a fourth transistor region. The first cell and the second cell adjoin each other at side cell boundaries thereof, the first transistor region and the third transistor region are formed in a first continuous active region, and the second transistor region and the fourth transistor region are formed in a second continuous active region. The set of masks is formed based on the integrated circuit layout.
One or more embodiments include a set of masks corresponding to an integrated circuit layout. The integrated circuit layout comprises a first cell comprising a first active region and a first side boundary, and a second cell comprising a second active region and a second side boundary along the first side boundary. The integrated circuit layout further comprises a first gate strip in the first cell parallel to the first side boundary and overlying the first active region, a second gate strip in the second cell parallel to the second side boundary and overlying the second active region, and a dummy gate strip parallel to and between the first gate strip and the second gate strip, wherein the dummy gate strip overlies at least one of the first active region or the second active region. The set of masks is formed based on the integrated circuit layout.
One or more embodiments include a set of masks corresponding to an integrated circuit layout. The integrated circuit layout comprises a first cell comprising a first active region and a first side boundary, and a second cell comprising a second active region and a second side boundary along the first side boundary. The integrated circuit layout further comprises a first gate strip in the first cell parallel to the first side boundary and overlying the first active region, a second gate strip in the second cell parallel to the second side boundary and overlying the second active region, a blank region abutting the first active region and the second active region, a first dummy gate strip in the first cell between the first gate strip and the first side boundary, and overlying the first active region and the blank region, and a second dummy gate strip in the second cell between the second gate strip and the second side boundary, and overlying the second active region and the blank region. The set of masks is formed based on the integrated circuit layout.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.

Claims (20)

What is claimed is:
1. A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
a first cell comprising a first transistor region and a second transistor region;
a second cell comprising a third transistor region and a fourth transistor region,
wherein
the first cell and the second cell adjoin each other at side cell boundaries thereof,
the first transistor region and the third transistor region are formed in a first continuous active region, and
the second transistor region and the fourth transistor region are formed in a second continuous active region; and
a middle gate strip extending from the first transistor region to the second transistor region, along a line at which the first cell adjoins the second cell,
wherein the set of masks is formed based on the integrated circuit layout.
2. The set of masks of claim 1, wherein the first cell further comprises:
a first gate strip; and
upper and lower cell boundaries on opposite ends of the first cell,
wherein
the side cell boundaries are parallel to the first gate strip;
the first transistor region comprises a first PMOS transistor comprising a first portion of the first gate strip as a first gate, a first source region and a first drain region adjacent to the first gate, and
the second transistor region comprises a first NMOS transistor comprising a second portion of the first gate strip as a second gate, and a second source region and a second drain region adjacent to the second gate.
3. The set of masks of claim 2, wherein the second cell further comprises:
a second gate strip parallel to the first gate strip; and
upper and lower cell boundaries on opposite sides of the second cell,
wherein
the third transistor region comprises a second PMOS transistor comprising a first portion of the second gate strip as a third gate, and a third source region and a third drain region adjacent to the third gate, and
the fourth transistor region comprises a second NMOS transistor comprising a second portion of the second gate strip as a fourth gate, and a fourth source region and a fourth drain region adjacent to the fourth gate.
4. The set of masks of claim 3, wherein the first gate strip and the second gate strips are active gate strips and the middle gate strip is a dummy gate strip.
5. The set of masks of claim 3, wherein the integrated circuit layout further comprises:
a first power supply line extending across the upper cell boundaries of the first cell and the second cell; and
a second power supply line extending across the lower cell boundaries of the first cell and the second cell,
wherein the first power supply line is electrically coupled to the first source region and the third source region and the second power supply line is electrically coupled to the second source region and the fourth source region.
6. The set of masks of claim 5, wherein:
an upper portion of the middle gate strip, the first drain region, and the third source region form a parasitic transistor;
a lower portion of the middle gate strip, the second drain region, and the fourth source region form a parasitic transistor;
the upper portion of the middle gate strip is electrically coupled to the first power supply line; and
the lower portion of the middle gate strip is electrically coupled to the second power supply line.
7. The set of masks of claim 1, wherein:
the first cell further comprises a first dummy gate strip along the side cell boundary opposite to the middle gate strip and the second cell further comprises a second dummy gate strip along the side cell boundary opposite to the middle gate strip.
8. The set of masks of claim 1, wherein:
the first continuous active region extends to the side cell boundaries of the first cell, and the second continuous active region extends to the side cell boundaries of the second cell.
9. A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
a first cell comprising a first active region and a first side boundary;
a second cell comprising a second active region and a second side boundary along the first side boundary;
a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;
a second gate strip in the second cell parallel to the second side boundary and overlying the second active region; and
a dummy gate strip parallel to and between the first gate strip and the second gate strip,
wherein the dummy gate strip overlies one of the first active region or the second active region,
wherein the set of masks is formed based on the integrated circuit layout.
10. The set of masks of claim 9, wherein:
the first cell further comprises a third active region,
the second cell further comprises a fourth active region,
when the dummy gate strip overlies the first active region, the dummy gate strip also overlies the third active region, and
when the dummy gate strip overlies the second active region, the dummy gate strip also overlies the fourth active region.
11. The set of masks of claim 9, wherein the integrated circuit layout further comprises a first power supply line along a direction perpendicular to the dummy gate strip, wherein the first active region comprises a first source region electrically coupled to the first power supply line.
12. The set of masks of claim 11, wherein the integrated circuit layout further comprises a second power supply line along the direction perpendicular to the dummy gate strip, wherein the second active region comprises a second source region electrically coupled to the second power supply line.
13. The set of masks of claim 12, wherein the first power supply line is electrically coupled to the second power supply line.
14. The set of masks of claim 12, wherein the first power supply line is electrically separate from the second power supply line.
15. A set of masks corresponding to an integrated circuit layout, the integrated circuit layout comprising:
a first cell comprising a first active region and a first side boundary;
a second cell comprising a second active region and a second side boundary along the first side boundary;
a first gate strip in the first cell parallel to the first side boundary and overlying the first active region;
a second gate strip in the second cell parallel to the second side boundary and overlying the second active region;
a blank region abutting the first active region and the second active region;
a first dummy gate strip in the first cell between the first gate strip and the first side boundary, and overlying the first active region and the blank region; and
a second dummy gate strip in the second cell between the second gate strip and the second side boundary, and overlying the second active region and the blank region,
wherein the set of masks is formed based on the integrated circuit layout.
16. The set of masks of claim 15, wherein the first dummy gate strip overlies a border between the first active region and the blank region.
17. The set of masks of claim 15, wherein:
the first cell further comprises a third active region,
the second cell further comprises a fourth active region,
the first dummy gate strip overlies the third active region, and
the second dummy gate strip overlies the fourth active region.
18. The set of masks of claim 17, wherein:
the first dummy gate strip overlies a first edge of the blank region, and
the first active region and the third active region abut the first edge of the blank region.
19. The set of masks of claim 18, wherein:
the second dummy gate strip overlies a second edge of the blank region, and
the second active region and the fourth active region abut the second edge of the blank region.
20. The set of masks of claim 15, wherein the second side boundary is along the first side boundary in the blank region.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10090289B1 (en) 2017-09-18 2018-10-02 United Microelectronics Corp. Integrated circuits with standard cell
US10236302B2 (en) 2016-06-22 2019-03-19 Qualcomm Incorporated Standard cell architecture for diffusion based on fin count
US10249605B2 (en) 2016-12-07 2019-04-02 Samsung Electronics Co., Ltd. Integrated circuit devices
US10262982B2 (en) 2017-09-15 2019-04-16 United Microelectronics Corp. Integrated circuits with standard cell
US10361198B2 (en) 2016-10-06 2019-07-23 Samsung Electronics Co., Ltd. Integrated circuit devices and method of manufacturing the same
US11094695B2 (en) * 2019-05-17 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device and method of forming the same
US11386254B2 (en) 2018-12-13 2022-07-12 Samsung Electronics Co., Ltd. Semiconductor circuit and semiconductor circuit layout system
US11955486B2 (en) * 2021-08-12 2024-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device and method of forming the same

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102152772B1 (en) * 2013-11-18 2020-09-08 삼성전자 주식회사 Layout design system, layout design method, and semiconductor device fabricated by using the same
US9306570B1 (en) * 2015-01-22 2016-04-05 Qualcomm Incorporated Continuous diffusion configurable standard cell architecture
US9337099B1 (en) * 2015-01-30 2016-05-10 Globalfoundries Inc. Special constructs for continuous non-uniform active region FinFET standard cells
JP6396834B2 (en) 2015-03-23 2018-09-26 ルネサスエレクトロニクス株式会社 Semiconductor device
WO2016201022A1 (en) * 2015-06-09 2016-12-15 Valent U.S.A. Corporation Gibberellin formulations
US9431300B1 (en) * 2015-08-27 2016-08-30 Globalfoundries Inc. MOL architecture enabling ultra-regular cross couple
KR102452195B1 (en) * 2016-02-16 2022-10-06 삼성전자주식회사 Semiconductor device
US11302694B2 (en) * 2016-02-16 2022-04-12 Samsung Electronics Co., Ltd. Semiconductor device without a break region
US10062697B2 (en) * 2016-02-16 2018-08-28 Samsung Electronics Co., Ltd. Semiconductor device without a break region
US10163880B2 (en) 2016-05-03 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit and method of fabricating the same
US20170323902A1 (en) * 2016-05-06 2017-11-09 Globalfoundries Inc. Method, apparatus, and system for improved cell design having unidirectional metal layout architecture
US20170358565A1 (en) * 2016-06-09 2017-12-14 Globalfoundries Inc. Standard cell layout and method of arranging a plurality of standard cells
US9893070B2 (en) 2016-06-10 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method therefor
US10163883B2 (en) * 2016-06-15 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Layout method for integrated circuit and layout of the integrated circuit
US9960231B2 (en) 2016-06-17 2018-05-01 Qualcomm Incorporated Standard cell architecture for parasitic resistance reduction
US10846452B2 (en) * 2016-07-01 2020-11-24 Globalfoundries Inc. Method, apparatus and system for wide metal line for SADP routing
US9634026B1 (en) * 2016-07-13 2017-04-25 Qualcomm Incorporated Standard cell architecture for reduced leakage current and improved decoupling capacitance
FR3056371B1 (en) * 2016-09-19 2018-10-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives INTEGRATED CIRCUIT COMPRISING BALANCED CELLS IN ACTIVE ZONE BORDER
FR3056372B1 (en) * 2016-09-19 2018-10-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives INTEGRATED CIRCUIT COMPRISING BALANCED CELLS IN ACTIVE ZONE BORDER
US10777508B2 (en) * 2016-11-09 2020-09-15 United Microelectronics Corp. Semiconductor device
US10157840B2 (en) * 2016-12-02 2018-12-18 Taiwan Semiconductor Manufacturing Company Limited Integrated circuit having a high cell density
US10354947B2 (en) 2017-02-06 2019-07-16 Samsung Electronics Co., Ltd. Integrated circuit including standard cell
KR102360212B1 (en) * 2017-02-06 2022-02-09 삼성전자주식회사 Integrated circuit including standard cell
US10181522B2 (en) 2017-02-21 2019-01-15 Globalfoundries Inc. Simplified gate to source/drain region connections
KR102358481B1 (en) * 2017-06-08 2022-02-04 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US10692808B2 (en) 2017-09-18 2020-06-23 Qualcomm Incorporated High performance cell design in a technology with high density metal routing
US10685982B2 (en) * 2017-11-29 2020-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure
US10867104B2 (en) 2018-08-31 2020-12-15 Taiwan Semiconductor Manufacturing Company Ltd. Isolation circuit between power domains
US11562953B2 (en) * 2018-10-23 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Cell having stacked pick-up region

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5723883A (en) 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US6528841B2 (en) 2001-01-09 2003-03-04 Samsung Electronics Co., Ltd. NAND type flash memory device having dummy region
US6635935B2 (en) 2000-07-10 2003-10-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device cell having regularly sized and arranged features
US6958939B2 (en) 2003-09-15 2005-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Flash memory cell having multi-program channels
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US20060190893A1 (en) * 2005-02-24 2006-08-24 Icera Inc. Logic cell layout architecture with shared boundary
US20070020858A1 (en) * 2005-07-22 2007-01-25 Samsung Electronics Co., Ltd. Layout structure of MOS transistors and methods of disposing MOS transistors on an active region
US20080186059A1 (en) 2007-02-05 2008-08-07 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US7679106B2 (en) * 2007-05-15 2010-03-16 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US20100269081A1 (en) 2009-04-15 2010-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Standard Cells Having Flexible Layout Architecture/Boundaries
US7821039B2 (en) 2008-06-23 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Layout architecture for improving circuit performance
US8026536B2 (en) 2005-03-30 2011-09-27 Elpida Memory, Inc. Semiconductor device having a dummy gate
US8115511B2 (en) * 2009-04-14 2012-02-14 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8129750B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length
US20120106225A1 (en) 2010-10-27 2012-05-03 Texas Instruments Incorporated Array-Based Integrated Circuit with Reduced Proximity Effects

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8324668B2 (en) * 2009-12-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for isolating devices in integrated circuits
WO2011077664A1 (en) * 2009-12-25 2011-06-30 パナソニック株式会社 Semiconductor device
US8661389B2 (en) * 2011-04-12 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods of designing integrated circuits
US8836040B2 (en) * 2012-11-07 2014-09-16 Qualcomm Incorporated Shared-diffusion standard cell architecture

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5723883A (en) 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US6635935B2 (en) 2000-07-10 2003-10-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device cell having regularly sized and arranged features
US6528841B2 (en) 2001-01-09 2003-03-04 Samsung Electronics Co., Ltd. NAND type flash memory device having dummy region
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US6958939B2 (en) 2003-09-15 2005-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Flash memory cell having multi-program channels
US20060190893A1 (en) * 2005-02-24 2006-08-24 Icera Inc. Logic cell layout architecture with shared boundary
US8026536B2 (en) 2005-03-30 2011-09-27 Elpida Memory, Inc. Semiconductor device having a dummy gate
US20070020858A1 (en) * 2005-07-22 2007-01-25 Samsung Electronics Co., Ltd. Layout structure of MOS transistors and methods of disposing MOS transistors on an active region
US8129750B2 (en) 2006-03-09 2012-03-06 Tela Innovations, Inc. Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length
US20080186059A1 (en) 2007-02-05 2008-08-07 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US7679106B2 (en) * 2007-05-15 2010-03-16 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US7821039B2 (en) 2008-06-23 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Layout architecture for improving circuit performance
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US8115511B2 (en) * 2009-04-14 2012-02-14 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US20100269081A1 (en) 2009-04-15 2010-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Standard Cells Having Flexible Layout Architecture/Boundaries
US8504972B2 (en) 2009-04-15 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cells having flexible layout architecture/boundaries
US20120106225A1 (en) 2010-10-27 2012-05-03 Texas Instruments Incorporated Array-Based Integrated Circuit with Reduced Proximity Effects

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10236302B2 (en) 2016-06-22 2019-03-19 Qualcomm Incorporated Standard cell architecture for diffusion based on fin count
US10366196B2 (en) 2016-06-22 2019-07-30 Qualcomm Incorporated Standard cell architecture for diffusion based on fin count
US10361198B2 (en) 2016-10-06 2019-07-23 Samsung Electronics Co., Ltd. Integrated circuit devices and method of manufacturing the same
US10903213B2 (en) 2016-10-06 2021-01-26 Samsung Electronics Co., Ltd. Integrated circuit devices
US10249605B2 (en) 2016-12-07 2019-04-02 Samsung Electronics Co., Ltd. Integrated circuit devices
US10262982B2 (en) 2017-09-15 2019-04-16 United Microelectronics Corp. Integrated circuits with standard cell
US10319709B2 (en) 2017-09-15 2019-06-11 United Microelectronics Corp. Integrated circuits with standard cell
US10090289B1 (en) 2017-09-18 2018-10-02 United Microelectronics Corp. Integrated circuits with standard cell
US11386254B2 (en) 2018-12-13 2022-07-12 Samsung Electronics Co., Ltd. Semiconductor circuit and semiconductor circuit layout system
US11094695B2 (en) * 2019-05-17 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device and method of forming the same
US20210375866A1 (en) * 2019-05-17 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated Circuit Device and Method of Forming the Same
US11955486B2 (en) * 2021-08-12 2024-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device and method of forming the same

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US20150356225A1 (en) 2015-12-10

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