US9271344B2 - Dynamic LED display screen with increased frequency of input clock signals - Google Patents
Dynamic LED display screen with increased frequency of input clock signals Download PDFInfo
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- US9271344B2 US9271344B2 US14/000,508 US201214000508A US9271344B2 US 9271344 B2 US9271344 B2 US 9271344B2 US 201214000508 A US201214000508 A US 201214000508A US 9271344 B2 US9271344 B2 US 9271344B2
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- 238000011084 recovery Methods 0.000 claims description 4
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 229910000859 α-Fe Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000003068 static effect Effects 0.000 description 3
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 2
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
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Classifications
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- H05B33/0809—
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- H05B33/0815—
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- H05B37/0281—
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
- H05B45/32—Pulse-control circuits
- H05B45/325—Pulse-width modulation [PWM]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/16—Controlling the light source by timing means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
Definitions
- the application relates to the field of Light Emitting Diode (LED) display screens, and particularly to a Pulse Width Modulation (PWM) circuit and an LED drive circuit.
- LED Light Emitting Diode
- PWM Pulse Width Modulation
- PWM is an effective technique to control an analog circuit using digital outputs of a microprocessor, and it is widely used in many fields, such as fields of measurement, communication, power control and conversion.
- a PWM circuit 10 generally includes: a PWM counter 11 adapted to perform up/down counting for a clock signal; a reference value setting register 12 adapted to set a comparison reference value which determines the duty cycle of a PWM signal; and a comparator 13 adapted to compare the count value of the PWM counter with the comparison reference value set by the reference value setting register and generate an effective PWM signal.
- the PWM technique is adopted in order to improve the display resolution.
- the PWM is 16 bit.
- a serial bus including SDI (Serial Digital Input), DCLK (Serial Data Input Clock), LE (Latch Enable), GCLK (Graph Clock Input) and SDO (Serial Data Output) is usually adopted, in which the GCLK is an input clock of the PWM and the frequency of the GCLK is less than 30 MHz.
- SDI Serial Digital Input
- DCLK Serial Data Input Clock
- LE Latch Enable
- GCLK Graph Clock Input
- SDO Serial Data Output
- the GCLK is an input clock of the PWM and the frequency of the GCLK is less than 30 MHz.
- dynamic display screen each LED pixel is driven by a separate constant current source; whereas for the dynamic display, time-sharing driving is adopted, in which LEDs of each column share the same constant current source for driving.
- the display brightness of the LED is determined by the duty cycle output by the PWM
- a display refresh frequency greater than 2 KHz is required.
- the dynamic refresh frequency In order to meet practical requirements of application and increase the dynamic refresh frequency, it can only reduce the cycle length of the PWM, i.e., reduce the bit length of PWM. For example, if the bit length of the PWM is 12 bit, the refresh frequency may be 1824 Hz. However, the reduction of the bit length may cause a decrease in resolution, therefore the contradiction between the refresh frequency and the resolution of the dynamic display screen can not be solved in the conventional solution.
- a PWM circuit and an LED drive circuit applied to an LED display screen are provided according to the application.
- the refresh frequency can be improved while the original resolution is maintained.
- a PWM circuit which includes:
- a PWM counter adapted to count a clock signal
- a reference value setting register adapted to set a comparison reference value which determines the duty cycle of a PWM signal
- a frequency multiplier adapted to increase the frequency of an clock signal input and to output the clock signal with the increased frequency to the PWM counter
- a comparator adapted to generate a PWM signal based on a comparison between the comparison reference value and the count value of the PWM counter.
- the frequency multiplier is one of a transistor frequency multiplier, a varactor diode frequency multiplier, a step recovery diode frequency multiplier, a ferrite frequency multiplier, a phase-locked loop frequency multiplier and a synchronous frequency multiplier.
- the PWM circuit further includes a count value upper-limit setting register, for setting a count value upper-limit which determines the pulse width of the PWM signal in the PWM counter.
- the comparator is adapted to output an “L” level as the PWM signal when the count value of the PWM counter is lower than the comparison reference value, and to output an “H” level as the PWM signal when the count value of the PWM counter is higher than the comparison reference value.
- the comparator is adapted to output an “H” level as the PWM signal when the count value of the PWM counter is lower than the comparison reference value, and to output an “L” level as the PWM signal when the count value of the PWM counter is higher than the comparison reference value.
- LED drive circuit is also provided according to the application, and the LED drive circuit includes:
- a drive module connected between the PWM circuit and the LED light source, for supplying stable current to the LED light source.
- the frequency multiplier is one of a transistor frequency multiplier, a varactor diode frequency multiplier, a step recovery diode frequency multiplier, a ferrite frequency multiplier, a phase-locked loop frequency multiplier and a synchronous frequency multiplier.
- the PWM circuit further includes a count value upper-limit setting register, for setting a count value upper-limit which determines the pulse width of the PWM signal in the PWM counter.
- the comparator is adapted to output an “L” level as the PWM signal when the count value of the PWM counter is lower than the comparison reference value, and to output an “H” level as the PWM signal when the count value of the PWM counter is higher than the comparison reference value.
- the comparator is adapted to output an “H” level as the PWM signal when the count value of the PWM counter is lower than the comparison reference value, and to output an “L” level as the PWM signal when the count value of the PWM counter is higher than the comparison reference value.
- the PWM circuit provided by the application includes: a PWM counter, a reference value setting register, a frequency multiplier and a comparator, where the frequency multiplier is used to increase the frequency of a clock signal and output the clock signal with the increased frequency to the PWM counter.
- the frequency of the PWM input clock signal is increased to N times of the original frequency of the PWM input clock signal by the frequency multiplier, so that the counting cycle of the PWM counter is shortened to 1/N of the original counting cycle of the PWM counter. Therefore, in the dynamic LED display screen, the refresh frequency can be increased to N times of the original refresh frequency while the original resolution is maintained.
- FIG. 1 is a block diagram illustrating the basic structure of a PWM circuit in the prior art
- FIG. 2 is a block diagram illustrating the basic structure a PWM circuit in a specific embodiment according to the application;
- FIG. 3 is an operation time sequence diagram of the PWM circuit shown in FIG. 2 ;
- FIG. 4 shows an LED drive circuit in a specific embodiment according to the application.
- a PWM circuit is provided according to an embodiment of the application.
- the PWM circuit includes:
- a PWM counter adapted to count a clock signal
- a reference value setting register adapted to set a comparison reference value which determines the duty cycle of a PWM signal
- a frequency multiplier adapted to increase the frequency of an clock signal and output the clock signal with the increased frequency to the PWM counter
- a comparator adapted to generate a PWM signal based on a comparison between the comparison reference value and the count value of the PWM counter
- the frequency multiplier is used to increase the frequency of an input pulse signal to N times of the original frequency of the input pulse signal, where N may be an integer greater than 1 or a decimal greater than 1.
- the frequency multiplier may be a transistor frequency multiplier, a varactor diode frequency multiplier, a step recovery diode frequency multiplier, etc.; the frequency multiplier may also be a frequency multiplier constituted by non-linear resistors, inductors and capacitors, such as a ferrite frequency multiplier; in a device requiring small frequency multiplication noise, the frequency multiplier may also be a phase-locked loop frequency multiplier and a synchronous frequency multiplier formed according to the principle of a phase-locked loop.
- the frequency multiplier is preferably a phase-locked loop.
- the frequency multiplication of the input counting frequency of the PWM counter may be achieved by the DCLK on a serial bus.
- the phase-locked loop is constituted by a phase detector, a loop filter and a voltage controlled oscillator.
- the phase detector is used to detect a phase difference between an input signal and an output signal and output an error voltage.
- the noise and interference components in the error voltage are filtered by the loop filter which is a low-pass one, so as to form a control voltage for the voltage controlled oscillator.
- the result of applying the control voltage to the voltage controlled oscillator is to pull the output oscillation frequency of the voltage controlled oscillator to the input signal frequency of the loop, and when the output oscillation frequency and the input signal frequency are equal, the loop is locked, which is referred to as in-lock.
- the DC control voltage for maintaining the locking is provided by the phase detector, therefore, a certain phase difference is retained between the two input signals of the phase detector.
- the comparator is a circuit for comparing an analog voltage signal and a reference voltage.
- the two inputs of the comparator are both analog signals, while the output of the comparator is a binary signal. When the difference between the input voltages increases or decreases, the output of the comparator remains constant.
- the PWM circuit further includes a count value upper-limit setting register, for setting a count value upper-limit which determines the pulse width of the PWM signal in the PWM counter.
- the LED drive circuit includes:
- a drive module connected between the PWM circuit and the LED light source.
- the frequency of the PWM input clock signal is increased to N times of the original frequency of the PWM input clock signal by the frequency multiplier, so that the counting cycle of the PWM counter is shortened to 1/N of the original counting cycle of the PWM counter. Therefore, in the dynamic LED display screen, the refresh frequency can be increased to N times of the original refresh frequency while the original resolution is maintained.
- the frequency multiplier is preferably a phase-locked loop.
- the PWM circuit further includes a count value upper-limit setting register, for setting a count value upper-limit which determines the pulse width of the PWM signal in the PWM counter.
- FIG. 2 the basic structure of a PWM circuit of the application is shown.
- the PWM circuit 20 includes: a PWM counter 21 , a reference value setting register 22 , a frequency multiplier 23 , a comparator 24 and a count value upper-limit setting register 25 .
- the PWM counter 21 is adapted to count a clock signal GCLK.
- the reference value setting register 22 is adapted to set a comparison reference value S 1 which determines the duty cycle of a PWM signal Sp;
- the frequency multiplier 23 is adapted to increase the frequency of the clock signal GCLK and output the clock signal GCLK with the increased frequency to the PWM counter 21 ;
- the comparator 24 is adapted to compare the count value S 2 of the PWM counter 21 with the comparison reference value S 1 in the reference value setting register 22 , and generate the PWM signal Sp.
- the count value upper-limit setting register 25 is adapted to input a count value upper-limit which determines the pulse width of the PWM signal to the PWM counter 21 .
- FIG. 3 shows an operation time sequence diagram of the PWM circuit 20 .
- the frequency multiplier 23 multiplies the frequency f of the input clock signal GCLK, and the frequency of the multiplied clock signal GCLK is Nf, where N is an integer greater than 1.
- the input clock signal GCLK with the frequency Nf is counted by the PWM counter 21 .
- a count value upper-limit S 3 from the count value upper-limit setting register 25 is input to the PWM counter 21 . Up/down counting between “0” and the count value upper-limit S 3 is performed by the PWM counter 21 .
- the count value S 2 of the PWM counter 21 is input to one input terminal of the comparator 24 .
- a comparison reference value S 1 in the reference value setting register 22 is input to another input terminal of the comparator 24 .
- the comparator 24 compares the count value S 2 with the comparison reference value S 1 , and when the count value S 2 is lower than the comparison reference value S 1 , an “L” level is output from the comparator 24 as the PWM signal Sp, and when the count value S 2 is higher than the comparison reference value S 1 , an “H” level is output from the comparator 24 as the PWM signal Sp, and when the count value S 2 is lower than the comparison reference value S 1 again, the “L” level is output from the comparator 24 as the PWM signal Sp.
- the comparator may also output an “H” level as the PWM signal when the count value of the PWM counter is lower than the comparison reference value, and output an “L” level as the PWM signal when the count value of the PWM counter is higher than the comparison reference value.
- FIG. 4 an LED drive circuit in a specific embodiment of the application is shown.
- the LED drive circuit 30 includes a PWM circuit 20 , an LED light source 31 and a drive module 32 .
- the drive module 32 is connected between the PWM circuit and the LED light source, for supplying stable current to the LED light source 31 .
- the refresh frequency of the LED display screen is relatively low due to the frequency limitation of the GCLK on the bus, therefore a static display screen is usually adopted, which results in a high cost.
- the frequency multiplier is adopted, the input frequency for the PWM counting is increased, thus a dynamic display screen solution can be adopted to achieve a refresh frequency higher than 2 KHz while with a resolution of 16 bit.
- the number of the used LED drivers can be decreased. For example, with fours groups of scanning, the number of the LED drivers can be decreased to 1 ⁇ 4 of the number of the originally used LED drivers, thereby saving a lot of hardware overhead.
- the frequency of GCLK on the bus is Fclk
- the refresh frequency is Fs
- the resolution is K (Bit)
- the PWM counting clock frequency is Fct;
- Fct Fs* 2 K;
- Fs Fct /(2 K );
- the PWM circuit includes: a PWM counter, a reference value setting register, a frequency multiplier and a comparator, in which the frequency multiplier is adapted to increase the frequency of the clock signal and output the clock signal with the increased frequency to the PWM counter.
- the frequency of the PWM input clock signal is increased to N times of the original frequency of the PWM input clock by the frequency multiplier, so that the counting cycle of the PWM counter is shortened to 1/N of the original counting cycle of the PWM counter. Therefore, in the dynamic LED display screen, the refresh frequency can be increased to N times of the original refresh frequency while the original resolution is maintained.
Abstract
Description
Fct=Fs*2K;
Fs=Fct/(2K);
Fs=Fclk/(2K); (I)
Fs=N*Fclk/(2K); (II)
Claims (5)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2012100993250A CN102629863A (en) | 2012-04-06 | 2012-04-06 | PWM (Pulse Width Modulation) circuit and LED drive circuit |
CN201210099325 | 2012-04-06 | ||
CN201210099325.0 | 2012-04-06 | ||
PCT/CN2012/080075 WO2013149450A1 (en) | 2012-04-06 | 2012-08-14 | Pwm circuit and led drive circuit |
Publications (2)
Publication Number | Publication Date |
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US20150163870A1 US20150163870A1 (en) | 2015-06-11 |
US9271344B2 true US9271344B2 (en) | 2016-02-23 |
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US14/000,508 Active US9271344B2 (en) | 2012-04-06 | 2012-08-14 | Dynamic LED display screen with increased frequency of input clock signals |
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US (1) | US9271344B2 (en) |
CN (1) | CN102629863A (en) |
WO (1) | WO2013149450A1 (en) |
Families Citing this family (9)
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CN103390387B (en) * | 2013-07-23 | 2015-10-21 | 深圳市明微电子股份有限公司 | A kind of frequency multiplication display control method and system |
CN103839529B (en) * | 2014-02-25 | 2017-05-03 | 青岛海信电器股份有限公司 | Driving system and method of backlight source |
CN104183218A (en) * | 2014-08-21 | 2014-12-03 | 深圳市信立方科技有限公司 | LED display screen driving circuit and display screen |
CN107294526A (en) * | 2016-04-11 | 2017-10-24 | 苏州超锐微电子有限公司 | A kind of improved digital clock and data recovery method |
CN110244588B (en) * | 2018-03-09 | 2022-04-05 | 华大半导体有限公司 | Multifunctional timer |
CN108566183A (en) * | 2018-05-08 | 2018-09-21 | 南京矽力杰半导体技术有限公司 | Pulse width modulator and method for generating pulse width modulation signal |
CA3129962A1 (en) * | 2019-02-21 | 2020-08-27 | Dialight Corporation | Lifi network and associated method |
CN114724501A (en) * | 2022-03-23 | 2022-07-08 | 厦门凌阳华芯科技有限公司 | LED display and pulse width modulation system thereof |
CN115664397B (en) * | 2022-12-22 | 2023-04-21 | 无锡麟聚半导体科技有限公司 | PWM regulating circuit and chip |
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US20030093607A1 (en) * | 2001-11-09 | 2003-05-15 | Main Kevin K. | Low pin count (LPC) I/O bridge |
US20060214603A1 (en) * | 2005-03-22 | 2006-09-28 | In-Hwan Oh | Single-stage digital power converter for driving LEDs |
CN201007902Y (en) | 2007-02-06 | 2008-01-16 | 深圳市灵星雨科技开发有限公司 | Display unit control driving module with phase-locked loop |
US20090085845A1 (en) | 2007-10-01 | 2009-04-02 | Samsung Electronics Co., Ltd. | Method and apparatus for driving led dot matrix |
CN102006696A (en) | 2009-09-02 | 2011-04-06 | 北京京东方光电科技有限公司 | Light-emitting diode backlight drive circuit, method and constant current source thereof |
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2012
- 2012-04-06 CN CN2012100993250A patent/CN102629863A/en active Pending
- 2012-08-14 US US14/000,508 patent/US9271344B2/en active Active
- 2012-08-14 WO PCT/CN2012/080075 patent/WO2013149450A1/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20030093607A1 (en) * | 2001-11-09 | 2003-05-15 | Main Kevin K. | Low pin count (LPC) I/O bridge |
US20060214603A1 (en) * | 2005-03-22 | 2006-09-28 | In-Hwan Oh | Single-stage digital power converter for driving LEDs |
CN201007902Y (en) | 2007-02-06 | 2008-01-16 | 深圳市灵星雨科技开发有限公司 | Display unit control driving module with phase-locked loop |
US20090085845A1 (en) | 2007-10-01 | 2009-04-02 | Samsung Electronics Co., Ltd. | Method and apparatus for driving led dot matrix |
CN102006696A (en) | 2009-09-02 | 2011-04-06 | 北京京东方光电科技有限公司 | Light-emitting diode backlight drive circuit, method and constant current source thereof |
Non-Patent Citations (1)
Title |
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International Search Report and Written Opinion dated Dec. 27, 2012 from corresponding PCT/CN2012/080075, 11 pp. |
Also Published As
Publication number | Publication date |
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CN102629863A (en) | 2012-08-08 |
WO2013149450A1 (en) | 2013-10-10 |
US20150163870A1 (en) | 2015-06-11 |
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