US9219011B2 - Separation of chips on a substrate - Google Patents

Separation of chips on a substrate Download PDF

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US9219011B2
US9219011B2 US14/013,822 US201314013822A US9219011B2 US 9219011 B2 US9219011 B2 US 9219011B2 US 201314013822 A US201314013822 A US 201314013822A US 9219011 B2 US9219011 B2 US 9219011B2
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substrate
metallization
dicing
parts
partially
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US20150064879A1 (en
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Manfred Engelhardt
Gudrun Stranzl
Markus Zundel
Hubert Maier
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Infineon Technologies AG
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Infineon Technologies AG
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Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ENGELHARDT, MANFRED, STRANZL, GUDRUN, ZUNDEL, MARKUS, MAIER, HUBERT
Priority to DE102014111977.0A priority patent/DE102014111977A1/de
Publication of US20150064879A1 publication Critical patent/US20150064879A1/en
Priority to US14/977,625 priority patent/US9490103B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Definitions

  • the present application relates to the separation of a substrate, for example, to obtain separate chip dies.
  • a plurality of chips is manufactured on a single wafer.
  • typical semiconductor wafers used as substrates in a manufacturing process may have a diameter of 100 mm or more, e.g., 300 mm or more, and typical chip dimensions may be in the order of 100 ⁇ m up to some millimeters. Therefore, a plurality of chips can be formed on a single wafer, increasing manufacturing yield.
  • the chips on the wafer have to be separated from each other, resulting in a plurality of chip dies, also simply referred to as dies. These dies may then, for example, be individually packaged and contacted electrically to obtain final products.
  • metallization of the wafer may cause problems.
  • metallizations often comprise a stack of different metals which may require the use of different etchants in addition to plasma dicing applied to semiconductor material of the substrate, thus making the process difficult.
  • FIG. 1 is a block diagram illustrating an apparatus according to an embodiment
  • FIG. 2 is a flowchart illustrating a method according to an embodiment
  • FIG. 3 is a block diagram illustrating an apparatus according to an embodiment
  • FIG. 4 is a flowchart illustrating a method according to an embodiment
  • FIGS. 5A-5F are schematic representations of a substrate in various stages of processing, for illustrating embodiments
  • FIG. 6 is a block diagram illustrating an apparatus according to an embodiment
  • FIG. 7 is a flowchart illustrating a method according to an embodiment.
  • FIGS. 8A-8E are schematic representations of a substrate in various stages of processing, for illustrating embodiments.
  • substrate may refer to a processed substrate, for example, a substrate where semiconductor structures are formed on the substrate and/or metallization layers have been applied to the substrate, or to an unprocessed substrate.
  • embodiments described in the following relate to separation of a substrate into a plurality of dies. This separation is also referred to as dicing herein.
  • Partial dicing refers to techniques, devices or operations where only part of material(s) between dies to be formed from the substrate is removed. For example, grooves or trenches may be formed between chips which do not extend all the way through the material between the chips, for example, a semiconductor material like a wafer and/or a metallization.
  • FIG. 1 a block diagram illustrating an apparatus according to an embodiment is shown.
  • the apparatus of FIG. 1 in some embodiments is part of a system or apparatus for substrate processing.
  • additional devices, apparatuses etc. may be employed to perform additional substrate processing to the substrate processing performed by the apparatus of FIG. 1 discussed in the following.
  • the term “apparatus” does not imply any specific spatial relationship between the various devices forming the apparatus. For example, different devices may be provided in different rooms, different buildings or other kinds of different locations, substrates being transported between the devices.
  • a device may comprise several sub-devices which may be located adjacent to each other or remote from each other.
  • Various devices of the embodiments may be combined into a single device. In other words, depicting two or more devices as separate blocks does not imply that these devices have to be implemented in a spatially separate manner.
  • the apparatus comprises a partial dicing device 10 and a complete separation device 11 .
  • substrates for example substrates comprising semiconductor wafers like silicon wafers
  • substrates are first partially diced by partial dicing device 10 .
  • the individual chip dies or other substrate parts are completely separated in complete separation device 11 .
  • devices 10 and 11 further devices to perform substrate processing, for example, any conventional kind of semiconductor substrate processing, may be provided.
  • Partial dicing apparatus 10 may, for example, use a plasma dicing technique or a mechanical sawing technique to perform the partial dicing.
  • Complete separation device 11 may, for example, mechanically separate the chip dies or other desired substrate parts from each other.
  • the partially diced substrate may be mounted to an expansion tape. The tape may then be expanded, resulting in a mechanical separation.
  • Other kinds of mechanical separation for example water beams, or other techniques like laser beam techniques may also be employed to perform the complete separation.
  • FIG. 2 a flowchart illustrating a method according to an embodiment is shown.
  • the method of FIG. 2 may be implemented using the apparatus of FIG. 1 , but may also be implemented using other apparatuses or devices. It should be noted that further to the operations and techniques described with reference to FIG. 2 , further techniques or operations may be employed before, after or between the operations and techniques explicitly described.
  • a partial dicing of a substrate is performed, that is material between chips or other substrate parts to be separated is partially removed.
  • the partial dicing is performed by sawing or plasma dicing.
  • partially removing the material involves partially removing semiconductor material, leaving semiconductor material “bridges” between the chips.
  • partially removing the material involves completely removing semiconductor material between the chip leaving, for example, only a metallization like a backside metallization connecting the chips.
  • a complete separation of the chips into chip dies is performed, for example, by a mechanical treatment, a particle beam treatment like a water beam treatment or by a laser beam treatment.
  • the partially diced substrate may, e.g., be mounted to an expansion tape which then is expanded to mechanically separate the chip dies from each other.
  • FIG. 3 a block diagram illustrating a substrate processing apparatus according to an embodiment is shown. As for the embodiment of FIG. 1 , while a plurality of devices are shown in FIG. 3 , additional devices may be provided to process substrates prior to being provided to the apparatus of FIG. 3 , after leaving the apparatus of FIG. 3 or in between being processed by various devices shown in FIG. 3 .
  • the apparatus of FIG. 3 comprises a partial dicing device 30 for partially dicing substrates to be processed, i.e., partially removing material between chips or other relevant parts on the substrate.
  • the partial dicing may comprise forming grooves or trenches in comparatively thick semiconductor wafers, for example wafers being about 600-700 ⁇ m thick.
  • the partial dicing may be performed, for example, employing plasma dicing or mechanical methods like sawing using a wire saw. Trenches or grooves formed in this way may have a depth between 20 ⁇ m and 100 ⁇ m, for example, between 30 ⁇ m and 40 ⁇ m, but are not limited thereto.
  • the substrates are provided to a thinning device 31 thinning the substrate.
  • a thinning device 31 thinning the substrate.
  • any conventional grinding and/or polishing techniques used in semiconductor processing may be used.
  • the thinning may involve removing material from a side of the wafer opposite to the side where the grooves or trenches are formed in partial dicing device 30 .
  • the substrate in the embodiment of FIG. 3 is provided to a metallization device which may be used to provide a backside metallization to the substrate.
  • the metallization may be applied to the side of the substrate opposite the side where the grooves or trenches are formed in partial dicing device 30 .
  • the substrate is provided to a metallization structuring device 33 which structures the metallization corresponding to the partial dicing, in particular removes metallization corresponding to the location of the trenches or grooves provided by partial dicing device 30 .
  • metallization structuring device 33 may be omitted.
  • the substrate is provided to a separation device 34 where a complete separation of the chip dies or other desired parts of the substrate is performed, for example by mechanical means like the use of an expansion tape, by a particle beam like a water beam or by radiation like laser radiation.
  • FIG. 4 a flowchart illustrating a method according to an embodiment is shown.
  • the method of FIG. 4 may, for example, be implemented using the apparatus of FIG. 3 , but may also be implemented using other apparatuses or devices.
  • other operations or techniques may be applied to the substrate.
  • the substrate may comprise a comparatively thick semiconductor wafer, for example with a thickness between 600 ⁇ m and 700 ⁇ m or more, and may comprise providing trenches or grooves in one side of the substrate.
  • a depth of the trenches or grooves may be between 20 ⁇ m and 100 ⁇ m, for example between 30 ⁇ m and 40 ⁇ m.
  • the substrate is thinned, for example, by material removal from a side opposite the trenches or grooves formed at 40 .
  • any conventional technique like grinding and/or polishing may be applied.
  • a metallization is applied to the thinned substrate, for example, a metallization comprising a plurality of metal layers.
  • the metallization may be provided on a side of the substrate opposing the trenches or grooves formed at 40 .
  • the metallization is structured. For example, portions of a blanket metallization are removed at locations corresponding to the positions of the trenches or grooves formed at 40 . Structuring the metallization may, for example, comprise etching the metallization with one or more etchants, with a plasma treatment or any other conventional metal removal techniques.
  • the chip dies or other relevant parts of the substrate are completely separated from each other, for example by applying mechanical force, for example, using an expansion tape, by using a particle beam like a water beam or by using laser radiation.
  • FIGS. 3 and 4 merely serve as one implementation example of an embodiment, and other implementations may equally be used.
  • a backside to be metallized may be covered with imide or photoresist, which imide or photoresist may be structured such that imide or photoresist remains in a kerf area, i.e., an area where the separation should be performed and where the trenches or grooves are provided, for example at 40 .
  • a metal may be sputtered on the backside, and the metal may be planarized stopping at the imide or photoresist such that no metal remains in the kerf area.
  • the imide or photoresist may then be removed.
  • a metal lift-off process may be performed in the kerf region.
  • imide and metal may remain on the substrate, and the separation at 44 may separate remaining substrate material, metallization and imide.
  • FIGS. 3 and 4 in some cases may result in side walls of higher quality than conventional methods, in particular as the partial dicing is performed prior to the thinning which reduces vibrations etc. during sawing or other dicing techniques.
  • the thinning at 41 may be performed prior to the partial dicing at 40 .
  • FIGS. 5A-5F show schematic cross-sectional views of substrates as they may occur in different devices of the embodiment of FIG. 3 or at different instances of the method of FIG. 4 .
  • FIGS. 5A-5F show schematic cross-sectional views of substrates as they may occur in different devices of the embodiment of FIG. 3 or at different instances of the method of FIG. 4 .
  • these cross-sectional views are merely illustrative examples, and in other implementations other structures than the ones shown may result.
  • various elements in FIGS. 5A-5F are not drawn to scale with each other, but are provided to clearly illustrate some features of some implementations of the embodiments of FIGS. 3 and 4 .
  • FIG. 5A a part of a semiconductor wafer 15 , for example, a processed semiconductor wafer with semiconductor structures or devices formed thereon, is shown.
  • Semiconductor wafer 15 may have a thickness of about 600-700 ⁇ m, but is not limited thereto.
  • a partial dicing is performed, resulting in grooves like groove 51 of FIG. 5A .
  • material is removed up to a certain depth, e.g., a depth between 20 ⁇ m and 100 ⁇ m, for example, between 30 ⁇ m and 40 ⁇ m, from wafer 50 .
  • the locations where the material is removed may correspond to scribe lines or kerf regions of the wafer.
  • the kerf area may be completely free of structures and other materials like metals and therefore consist of pure semiconductor material, for example pure silicon.
  • the removal of material may, for example, be performed using partial dicing device 30 of FIG. 3 or may be performed at 40 of FIG. 4 and may be performed, for example, using plasma dicing or mechanical sawing.
  • the direction of groove or trench 51 may be selected such that the kerf regions break in the direction of a natural break of the respective substrate material, for example silicon.
  • the wafer 50 is mounted to a carrier 52 , for example using an adhesive tape or other conventional mounting technique.
  • the backside of wafer 50 (the side opposite the side of groove 51 ) is thinned, for example down to a thickness of 50 ⁇ m substrate thickness, and metallized.
  • These operations may, for example, be performed in thinning device 31 and metallization device 32 of FIG. 3 or at 41 and 42 in FIG. 4 .
  • FIG. 5C where compared to the representation of FIG. 5B the wafer is shown “upside down,” i.e., with the carrier 52 below wafer 50 .
  • the actual orientation of the wafer 50 or other substrate may depend on the actual implementation of the various devices used.
  • FIG. 5C The result is shown in FIG. 5C .
  • a metallization 53 is provided on thinned wafer 50 to form a metallized substrate.
  • the metallization is structured, leading in particular to a removal of the metal in the region of groove 51 .
  • This may, for example, be performed using metallization structuring device 33 of FIG. 3 or may be performed at 43 of FIG. 4 .
  • a structured material 54 like a photoresist is applied to metallization 53 and removed at the regions of groove 51 .
  • a subsequent etching removes metallization 53 at the groove 51 , whereas the remaining metallization is protected by material 54 .
  • Various kinds of wet etching or plasma etching may, for example, be used to structure metallization 53 .
  • material 54 may be removed, for example, by using a corresponding solvent, and for the final separation, substrate 50 is, for example, mounted to an expansion tape 55 , as shown in FIG. 5E .
  • expansion tape 55 is expanded as indicated by arrows 56 , leading to a breaking of the “bridge” of wafer material above groove 51 in FIG. 5E .
  • the bridges of semiconductor material in some embodiments may be slightly slit, for example to a depth of 2-5 ⁇ m, using a plasma etch or a mechanical sawing to facilitate breaking of the bridges when expanding the expansion tape. As shown in FIG.
  • part of the “bridge” mentioned above may adhere to one of the chips and may be removed for example using a material removal technique as will be described later with reference to FIG. 8E .
  • the bridge easily breaks in embodiments where the grooves like groove 51 are orientated corresponding to preferred breaking directions of the respective wafer used, for example a silicon wafer.
  • FIG. 6 shows a block diagram of an apparatus according to an embodiment comprising various devices. It is to be noted that prior to being processed by the devices of FIG. 6 , after being processed by the devices of FIG. 6 or between being processed by various devices of FIG. 6 substrates may be processed by additional devices which are not shown in FIG. 6 , for example conventional devices used for semiconductor processing. For example, prior to being processed by the devices of FIG. 6 , semiconductor structures or devices may be formed on a substrate like a semiconductor wafer by any conventional techniques.
  • a substrate for example, a processed semiconductor wafer like a processed silicon wafer
  • a thinning device 60 where the wafer is thinned to a target thickness, for example a thickness of about 50-70 ⁇ m, although other thicknesses are also possible depending on the application.
  • the thinning may, for example, be performed by applying conventional grinding and/or polishing techniques.
  • the substrate is provided to a metallization device 61 where a backside metallization is applied to the substrate, i.e., a metallization on a side of the substrate opposite a side where, for example, semiconductor structures or semiconductor devices are formed.
  • a backside metallization is applied to the substrate, i.e., a metallization on a side of the substrate opposite a side where, for example, semiconductor structures or semiconductor devices are formed.
  • Applying a metallization as already discussed may comprise subsequently applying a plurality of metal layers to the backside of the substrate.
  • the substrate is provided to a partial dicing device performing a partial dicing.
  • the partial dicing may comprise a complete removal of semiconductor materials between chips to be formed, leaving only the metallization formed in metallization device 61 connecting the chips with each other.
  • a thin bridge of semiconductor material as discussed with reference to FIGS. 5A-5F may be left.
  • the substrate is provided to a separation device 63 to perform a complete separation of the chip dies or other relevant parts of the substrate.
  • the substrate may be mounted to an expansion tape, which is then expanded.
  • the substrate may be provided to a material removal device 64 which is used to remove excess material, for example excess metal, as will be described using an example later with reference to FIG. 8E .
  • FIG. 7 may be implemented using the apparatus shown in FIG. 6 , but may also be implemented using other apparatuses or devices.
  • a substrate for example a semiconductor like a silicon wafer, is thinned to a desired target thickness.
  • the substrate may be a preprocessed substrate, for example a semiconductor wafer with semiconductor structures or devices formed thereon.
  • a metallization is applied to a backside of a substrate, i.e., a side opposite a side where semiconductor structures or other elements are formed on the substrate.
  • the metallization may comprise several layers, each layer comprising a metal or a metal alloy.
  • a partial dicing of the metallized substrate is performed.
  • semiconductor material between chip dies to be formed may be completely removed, for example using plasma dicing, such that the chip dies remain interconnected only via the metallization applied at 71 .
  • the chip dies or other relevant parts of the substrate are then completely separated from each other.
  • the substrate may be mounted to an expansion tape, and an expansion of the expansion tape may then tear the metallizations between the dies, thus completely separating the dies from each other.
  • excess material in particular excess metal, is removed for example using a so-called CO 2 snow-jet, which ejects small particles of dry ice, i.e., frozen CO 2 .
  • FIGS. 8A-8E various schematic cross-sectional views of a substrate in various stages of processing are shown.
  • the representations of FIGS. 8A-8E are to be regarded as schematic only, and various elements of these Figures are not necessarily drawn to scale with each other, but are depicted in a manner to give a clear understanding of the respective illustrated substrate.
  • the schematic representations of FIGS. 8A-8E illustrate merely one of numerous possibilities how substrates may look like in various stages of processing, and in other implementations of the embodiments of FIGS. 6 and 7 other substrates may be obtained.
  • FIG. 8A a schematic cross-sectional view of a substrate after a thinning and applying a metallization is shown, for example a substrate after having been processed by thinning device 60 and metallization device 61 of FIG. 6 or after having undergone the operations described with reference to 70 and 71 of FIG. 7 .
  • the substrate comprises a semiconductor wafer 80 having a metallization 81 on a backside thereof.
  • the substrate is mounted to a carrier 83 via an adhesive tape 82 .
  • a mask 84 has been applied to a front side of the wafer 80 , for example using conventional photolithography.
  • wafer 80 has been thinned prior to applying metallization 81 , for example thinned to a thickness of between 50 and 150 ⁇ m, for example about 50 ⁇ m.
  • FIG. 8B shows a schematic cross-sectional view of the arrangement of FIG. 8 after a partial dicing has been performed, for example using partial dicing device 62 of FIG. 6 or at 72 of FIG. 7 .
  • a partial dicing has been performed, for example using partial dicing device 62 of FIG. 6 or at 72 of FIG. 7 .
  • the material of semiconductor wafer 80 has been completely removed, for example using plasma dicing. Therefore, the various chip dies of wafer 80 remain only connected via backside metallization 81 .
  • the substrate is mounted to an expansion tape 86 as shown in FIG. 8C , for example in separation device 63 of FIG. 6 or at 73 of FIG. 7 .
  • holders for expansion tape 86 are denoted.
  • the expansion tape is then expanded as indicated by arrows 810 in FIG. 8D , thus tearing metallization 81 which results in a plurality of separated chip dies. While four such chip dies are shown in FIG. 8D for illustrative purposes, any number of chip dies can result, in particular significantly greater numbers than four, depending on the size of the wafer 80 and the size of the individual chips to be formed thereon.
  • metallization 81 may have portions overhanging the chip dies formed by wafer 80 . To remedy this, overhanging metallization may be removed, for example, in material removal device 64 of FIG. 6 or at 74 of FIG. 7 .
  • FIG. 8E An example for such a material removal is shown in FIG. 8E .
  • a so-called CO 2 snow-jet 88 which emits a beam of frozen dry ice particles (i.e., frozen CO 2 ) 89 is used for material removal, resulting in metallized chip dies without overhanging metallization which are then ready for further processing, for example electrical contacting, packaging or the like.
  • frozen CO 2 frozen dry ice particles

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US14/013,822 2013-08-29 2013-08-29 Separation of chips on a substrate Active 2033-10-17 US9219011B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US14/013,822 US9219011B2 (en) 2013-08-29 2013-08-29 Separation of chips on a substrate
DE102014111977.0A DE102014111977A1 (de) 2013-08-29 2014-08-21 Trennen von Chips auf einem Substrat
US14/977,625 US9490103B2 (en) 2013-08-29 2015-12-21 Separation of chips on a substrate

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