US8824269B2 - Method and system for a reference signal (RS) timing loop for OFDM symbol synchronization and tracking - Google Patents

Method and system for a reference signal (RS) timing loop for OFDM symbol synchronization and tracking Download PDF

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US8824269B2
US8824269B2 US13920947 US201313920947A US8824269B2 US 8824269 B2 US8824269 B2 US 8824269B2 US 13920947 US13920947 US 13920947 US 201313920947 A US201313920947 A US 201313920947A US 8824269 B2 US8824269 B2 US 8824269B2
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signal
timing
rs
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US20130279637A1 (en )
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Mark Kent
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Avago Technologies General IP Singapore Pte Ltd
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Broadcom Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver
    • H04L27/2655Synchronisation arrangements
    • H04L27/2662Symbol synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver
    • H04L27/2655Synchronisation arrangements
    • H04L27/2662Symbol synchronisation
    • H04L27/2663Coarse synchronisation, e.g. by correlation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver
    • H04L27/2655Synchronisation arrangements
    • H04L27/2662Symbol synchronisation
    • H04L27/2665Fine synchronisation, e.g. by positioning the FFT window
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver
    • H04L27/2655Synchronisation arrangements
    • H04L27/2666Acquisition of further OFDM parameters, e.g. bandwidth, subcarrier spacing, or guard interval length
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems
    • H04L27/2647Arrangements specific to the receiver
    • H04L27/2655Synchronisation arrangements
    • H04L27/2668Details of algorithms
    • H04L27/2673Details of algorithms characterised by synchronisation parameters
    • H04L27/2675Pilot or known symbols
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0054Detection of the synchronisation error by features other than the received signal transition

Abstract

Aspects of a method and system for a reference signal (RS) timing loop for OFDM symbol synchronization and tracking may include tracking symbol timing in an Orthogonal Frequency Division Multiplexing (OFDM) signal based on at least a reference symbol set. A receiver timing may be adjusted based on at least the symbol timing. The symbol timing may be tracked by generating an output signal as a function of a guard time Δtg in a phase discrimination feedback loop. The reference symbol (RS) set may be generated in an RS extraction module or circuit, from at least a fast Fourier transform of the received OFDM signal. The receiver timing may be coarsely adjusted and then finely adjusted. The coarse receiver timing adjustment may be based on processing at least a primary synchronization signal and a secondary synchronization signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application is a continuation of U.S. application Ser. No. 13/465,451, filed on May 7, 2012, now U.S. Pat. No. 8,498,197, which is a continuation of U.S. application Ser. No. 12/184,383, now U.S. Pat. No. 8,174,958, filed on Aug. 1, 2008, and makes reference to:

    • U.S. application Ser. No. 12/184,353, now U.S. Pat. No. 8,559,296, filed on Aug. 1, 2008; and
    • U.S. application Ser. No. 12/184,410, now U.S. Pat. No. 8,223,891, filed on Aug. 1, 2008. Each of the above referenced applications is hereby incorporated herein by reference in its entirety.
FIELD OF THE INVENTION

Certain embodiments of the invention relate to signal processing for communication systems. More specifically, certain embodiments of the invention relate to a method and system for a reference signal (RS) timing loop for OFDM symbol synchronization and tracking.

BACKGROUND OF THE INVENTION

Mobile communications have changed the way people communicate and mobile phones have been transformed from a luxury item to an essential part of everyday life. The use of mobile phones is today dictated by social situations, rather than hampered by location or technology. While voice connections fulfill the basic need to communicate, and mobile voice connections continue to filter even further into the fabric of everyday life, the mobile Internet is the next step in the mobile communication revolution. The mobile Internet is poised to become a common source of everyday information, and easy, versatile mobile access to this data will be taken for granted.

Third generation (3G) cellular networks have been specifically designed to fulfill these future demands of the mobile Internet. As these services grow in popularity and usage, factors such as cost efficient optimization of network capacity and quality of service (QoS) will become even more essential to cellular operators than it is today. These factors may be achieved with careful network planning and operation, improvements in transmission methods, and advances in receiver techniques. To this end, carriers need technologies that will allow them to increase throughput and, in turn, offer advanced QoS capabilities and speeds that rival those delivered by cable modem and/or DSL service providers. Recently, advances in multiple antenna technology and other physical layer technologies have started to significantly increase available communications data rates.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A method and/or system for reference signal (RS) timing loop for OFDM symbol synchronization and tracking, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a diagram illustrating exemplary cellular multipath communication between a base station and a mobile computing terminal, in connection with an embodiment of the invention.

FIG. 1B is a diagram illustrating an exemplary MIMO communication system, in accordance with an embodiment of the invention.

FIG. 2 is a diagram illustrating an exemplary OFDM symbol stream, in accordance with an embodiment of the invention.

FIG. 3A is a diagram of an exemplary OFDM timing acquisition and tracking system, in accordance with an embodiment of the invention.

FIG. 3B is a diagram illustrating phase offsets for exemplary timing offsets, in accordance with various embodiments of the invention.

FIG. 3C is a diagram illustrating phase offsets for exemplary timing offsets by subcarrier, in accordance with various embodiments of the invention.

FIG. 4 is a flow chart illustrating an exemplary timing acquisition and tracking process, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for RS timing loop for OFDM symbol synchronization and tracking. Aspects of the method and system for a reference signal (RS) timing loop for OFDM symbol synchronization and tracking may comprise tracking symbol timing in an Orthogonal Frequency Division Multiplexing (OFDM) signal based on at least a reference symbol set. A receiver timing may be adjusted based on at least the symbol timing.

The symbol timing may be tracked by generating an output signal as a function of a guard time Δtg in a phase discrimination feedback loop. The reference symbol (RS) set may be generated in an RS extraction module or circuit, from at least a fast Fourier transform of the received OFDM signal. The receiver timing may be coarsely adjusted and then finely adjusted. The coarse receiver timing adjustment may be achieved based on processing at least a primary synchronization signal and a secondary synchronization signal. The reference symbol set may comprise a plurality of time-frequency slots. The plurality of time-frequency slots may change according to a frequency shift and PN sequence that may modulate the reference symbols. The PN generated sequences may be determined by base station identifier. This base station identifier may be determined by the primary synchronization signal (PSS) and secondary synchronization signal (SSS). The OFDM signal may conform to a Universal Mobile Telecommunications Standards (UMTS) long-term evolution (LTE) signal. The adjustment of the receiver timing may be controlled via a receiver timing generator.

FIG. 1A is a diagram illustrating exemplary cellular multipath communication between a base station and a mobile computing terminal, in connection with an embodiment of the invention. Referring to FIG. 1A, there is shown a budding 140 such as a house or office, a mobile terminal 142, a factory 124, a base station 126, a car 128, and communication paths 130, 132 and 134.

The base station 126 and the mobile terminal 142 may comprise suitable logic, circuitry and/or code that may be enabled to generate and process MIMO communication signals.

Wireless communications between the base station 126 and the mobile terminal 142 may take place over a wireless channel. The wireless channel may comprise a plurality of communication paths, for example, the communication paths 130, 132 and 134. The wireless channel may change dynamically as the mobile terminal 142 and/or the car 128 moves. In some cases, the mobile terminal 142 may be in line-of-sight (LOS) of the base station 126. In other instances, there may not be a direct line-of-sight between the mobile terminal 142 and the base station 126 and the radio signals may travel as reflected communication paths between the communicating entities, as illustrated by the exemplary communication paths 130, 132 and 134. The radio signals may be reflected by man-made structures like the building 140, the factory 124 or the car 128, or by natural obstacles like hills. Such a system may be referred to as a non-line-of-sight (NLOS) communications system.

Signals communication by the communication system may comprise both LOS and NLOS signal components. If a LOS signal component is present, it may be much stronger than NLOS signal components. In some communication systems, the NLOS signal components may create interference and reduce the receiver performance. This may be referred to as multipath interference. The communication paths 130, 132 and 134, for example, may arrive with different delays at the mobile terminal 142. The communication paths 130, 132 and 134 may also be differently attenuated. In the downlink, for example, the received signal at the mobile terminal 142 may be the sum of differently attenuated communication paths 130, 132 and/or 134 that may not be synchronized and that may dynamically change. Such a channel may be referred to as a fading multipath channel.

A fading multipath channel may introduce interference but it may also introduce diversity and degrees of freedom into the wireless channel. Communication systems with multiple antennas at the base station and/or at the mobile terminal, for example MIMO systems, may be particularly suited to exploit the characteristics of wireless channels and may extract large performance gains from a fading multipath channel that may result in significantly increased performance with respect to a communication system with a single antenna at the base station 126 and at the mobile terminal 142, in particular for NLOS signals. Furthermore, Orthogonal Frequency Division Multiplexing (OFDM) systems may be suitable for wireless systems with multipath.

FIG. 1B is a diagram illustrating an exemplary MIMO communication system, in accordance with an embodiment of the invention. Referring to FIG. 1B, there is shown a MIMO transmitter 102 and a MIMO receiver 104, and antennas 106, 108, 110, 112, 114 and 116. The MIMO transmitter 102 may comprise a processor block 118, a memory block 120, and a signal processing block 122. The MIMO receiver 104 may comprise a processor block 124, a memory block 126, and a signal processing block 128. There is also shown a wireless channel comprising communication paths h11, h12, h22, h21, h2 NTX, h1 NTX, hNRX 1, hNRX 2, hNRX NTX, where hmn may represent a channel coefficient from transmit antenna n to receiver antenna m. There may be NTX transmitter antennas and NRX receiver antennas. There is also shown transmit symbols x1, x2 and xNTX, and receive symbols y1, y2 and yNRX.

The MIMO transmitter 102 may comprise suitable logic, circuitry and/or code that may be enabled to generate transmit symbols xi i ε {1, 2, . . . NTX} that may be transmitted by the transmit antennas, of which the antennas 106, 108 and 110 may be depicted in FIG. 1B. The processor block 118 may comprise suitable logic, circuitry, and/or code that may be enabled to process signals. The memory block 120 may comprise suitable logic, circuitry, and/or code that may be enabled to store and/or retrieve information for processing in the MIMO transmitter 102. The signal processing block 122 may comprise suitable logic, circuitry and/or code that may be enabled to process signals, for example in accordance with one or more MIMO transmission protocols. The MIMO receiver 104 may comprise suitable logic, circuitry and/or code that may be enabled to process the receive symbols yi i ε {1, 2, . . . NRX} that may be received by the receive antennas, of which the antennas 112, 114 and 116 may be shown in FIG. 1B. The processor block 124 may comprise suitable logic, circuitry, and/or code that may be enabled to process signals. The memory block 126 may comprise suitable logic, circuitry, and/or code that may be enabled to store and/or retrieve information for processing in the MIMO receiver 104. The signal processing block 128 may comprise suitable logic, circuitry and/or code that may be enabled to process signals, for example in accordance with one or more MIMO protocols. An input-output relationship between the transmitted and the received signal in a MIMO system may be written as:
y=Hx+n
where y=[y1, y2, . . . yNRX]T may be a column vector with NRX elements, .T may denote a vector transpose, H=[hij]: i ε {1, 2, . . . NRX}; j ε {1, 2, . . . NRX} may be a channel matrix of dimensions NRX by NTX, x=[xi, x2, . . . xNTX]T is a column vector with NTX elements and n is a column vector of noise samples with NRX elements.

The system diagram in FIG. 1B may illustrate an exemplary multi-antenna system as it may be utilized in a Universal Mobile Telecommunication System (UMTS) Long-Term Evolution (LTE) system. Over each of the NTX transmit antennas, a symbol stream, for example x1(t) over antenna 106, may be transmitted. A symbol stream, for example x1(t), may comprise one or more symbols, wherein each symbol may be modulated onto a different sub-carrier. OFDM systems may generally use a relatively large number of subcarriers in parallel, for each symbol stream. For example, a symbol stream x1(t) may comprise symbols on carriers fm: m ε {1, 2, . . . M}, and M may be a subset of the FFT size that may be utilized at the receiver. For instance, with FFT sizes of N, M<N and may create guard-tones that may allow utilization of variable bandwidth when deployed. The M sub-carriers may comprise a symbol stream x1(t), for example, that may occupy a bandwidth of a few kilohertz to a few megahertz. Common bandwidth may be between 1 MHz and up to 100 MHz, for example. Thus, each symbol stream may comprise one or more sub-carriers, and for each sub-carrier a wireless channel may comprise multiple transmission paths. For example, a wireless channel h12 from transmit antenna 108 to receive antenna 112, as illustrated in the figure, may be multi-dimensional. In particular, the wireless channel h12 may comprise a temporal impulse response, comprising one or more multipath components. The wireless channel h12 may also comprise a different temporal impulse response for each sub-carrier fm of the symbol stream, for example x2(t). Finally, the wireless channels as illustrated in FIG. 1B depict a spatial dimension of the wireless channel because the transmitted signal from each transmit antenna may be received differently at each receiver antenna. Thus, a channel impulse response may be measured and/or estimated for each sub-carrier.

FIG. 2 is an illustration of an exemplary OFDM symbol stream, in accordance with an embodiment of the invention. Referring to FIG. 2, there is shown a time axis 210; a time domain symbol 0 comprising a cyclic prefix CP(0) 202 a, an Inverse Fast Fourier Transform (IFFT) symbol less CP(0) (IFFT(0)) 202 b, and a cyclic prefix CP(0) 202 c; a time domain symbol 1 comprising a cyclic prefix CP(1) 204 a, an IFFT symbol less CP(1) (IFFT(0)) 204 b, and a cyclic prefix CP(1) 204 c. The IFFT(0) 202 b and the CP(0) 202 c may together form a complete IFFT symbol for time domain symbol 0. The CP(0) 202 a may be substantially similar to CP(0) 202 c. Similarly, the IFFT(1) 204 b and the CP(1) 204 c may together form a complete IFFT symbol for time domain symbol 1, and CP(1) 202 a may be substantially similar to CP(1) 202 c. There is also shown an FFT input window 206, a guard time Δtg, and a slot marker 208. An LTE slot structure, for example, may comprise 3, 6, or 7 OFDM symbols per slot (two of which may be illustrated in FIG. 2).

To generate an Orthogonal Frequency Division Multiplexing (OFDM) symbol, an output of an IFFT comprising of IFFT(0) 202 b and CP(0) 202 c may be used to generate CP(0) 202 a from CP(0) 202 c, and append it to IFFT(0) 202 b. The cyclic prefix CP(0) 202 may be utilized to avoid inter-symbol interference at an OFDM receiver, in the presence of multi-path propagation in the wireless channel.

At an OFDM receiver, for example MIMO receiver 104, a sampled input signal may be processed for each received symbol, for example over an FFT input window 206. In order to decode the received symbols, it may be desirable that the FFT input window 206 may be located in a time domain symbol time slot, for example in time domain symbol 0. In particular, it may be desirable that the FFT input window 206 may not extend into a neighboring symbol, to avoid inter-symbol interference. Thus, the slot marker may indicate the beginning of a slot, for example time domain symbol slot 0, as illustrated in FIG. 2. The slot marker 208 together with Δtg may define the position of the FFT input window 206 within a symbol slot. In most instances, to keep interference due to the multipath channel as low as possible at the receiver, it may be desirable to keep Δtg small.

Thus, it may be desirable to acquire symbol level timing, and maintain it as it may drift, for example, because of changes in propagation due to mobility. In some instances, this may be combined with other timing level acquisition and tracking, for example frame synchronization. In many instances, synchronization via the Primary Synchronization Signal (PSS) and the Secondary Synchronization Signal (SSS) may be obtained by other means. Symbol timing may be acquired by a timing acquisition and tracking system, which may exploit reference signals (RS) embedded in an OFDM signal. Reference symbols may be known symbols that may be transmitted according to a known pattern over the time, frequency and spatial resources in an OFDM system. In other words, reference symbols may be transmitted at known timing instances, on known OFDM carriers over certain antennas. By decoding and processing RS symbols, the receiver may determine correct timing information, for example, through coherent demodulation. RS symbols may be transmitted from each antenna in a multiple antenna OFDM system.

In the Enhanced Universal Terrestrial Radio Access (EUTRA) interface, RS symbols may be generated based on cell-specific hopping pattern, and may comprise pseudo-noise (PN) covered sequences of Reference symbols. In accordance with an embodiment of the invention, the RS tone spacing may be 6 carriers, per transmit antenna, for example. In accordance with various embodiments of the invention, the RS tone spacing may be 2, or 4 carriers, for example. The RS sequence may not be known to the mobile terminal (user equipment, UE) during initial acquisition, for example through the synchronization signals. In some instances, after acquiring the primary synchronization signal (PSS) and the secondary synchronization signal (SSS), the UE may have obtained the cell-specific hopping pattern for the RS symbols, and the PN covering sequence. This information may be used to obtain a coarse frame timing. In accordance with various embodiments of the invention, the RS symbols may then be decoded in a timing acquisition and tracking block to provide fine timing and tracking. Thus, for example Universal Mobile Telecommunication System (UMTS) Long-term evolution (LTE) may employ a three step process for timing recovery. The three step process may comprise: a) recovering slot timing from the PSS; b) recovering frame timing from the SSS; and c) obtaining an estimation of estimation of timing offset and tracking from the RS symbols.

FIG. 3A is a diagram of an exemplary OFDM timing acquisition and tracking system, in accordance with an embodiment of the invention. Referring to FIG. 3A, there is shown a common receiver part 342, and a timing part 340. The timing part 340 may comprise an RS phase discriminator 302, an adder 304, a delay block 306, an integrator 308, and a threshold block 310. There is also shown an RS set input, an error signal ek, an accumulator signal tt_loop_accum, a threshold input signal, a reset control signal reset_cntrl, and an output signal to_accum. The common receiver part 342 may comprise a timing generator 312, an RS extraction module or circuit 314, a channel estimation block 316, a receiver operations block (RXCVR) 318, a fast Fourier transform (FFT) block 320, a buffering block 330, a sampling bandwidth (BW) filter 332, and an analog-to-digital block 334. There is also shown an RF filter input, a slot timing input from PSS, an RS set output, a to_accum signal, an rs_strb signal, and a slot_strb signal.

The timing part 340 may comprise suitable logic, circuitry and/or code that may be enabled to extract timing information by processing an RS set of signals, which may generate an output to_accum that may control the timing generator 312, for example. The RS phase discriminator 302 may comprise suitable logic, circuitry and/or code that may be enabled to compare the timing of the RS set input signal with, for example, an input clock signal and may generate an error signal ek.

The adder 304 may comprise suitable logic, circuitry and/or code that may be enabled to generate a weighted sum signal at its output, from a plurality of inputs. The delay block 306 may comprise suitable logic, circuitry and/or code that may be enabled to delay an input signal by a certain time interval, for example one or more sample periods. The delay block 306 may comprise suitable logic, circuitry and/or code that may be enabled to delay an input signal by a certain time interval, for example one or more sample periods.

The integrator 308 may comprise suitable logic, circuitry and/or code that may be enabled to generate an output that may be the integration of one or more input signals, and the integrator 308 may be reset by the reset_cntrl signal. The threshold block 310 may comprise suitable logic, circuitry and/or code that may be enabled to compare a threshold input signal with the tt_loop_accum input signal, and generate output signals reset_cntrl and to_accum. For example, when the tt_loop_accum signal may exceed the threshold level, the reset cntrl signal may activate and reset, for example, the integrator 308.

The common receiver part 342 may comprise suitable logic, circuitry and/or code that may be enabled to receive radio frequency signals, and process these signals. The processing may comprise FFT computation, RS symbol extraction, channel estimation and other receiver signal processing. The timing generator 312 may comprise suitable logic, circuitry and/or code that may be enabled to generate timing signals for RS extraction, rs_strb, and slot timing, slot_strb. The signal slot_strb may be used to control FFT timing in the buffering block 330, for example. The module or circuit 314 may comprise suitable logic, circuitry and/or code that may be enabled to extract the RS symbols from the FFT module or circuit 320 output.

The channel estimation module or circuit 316 may comprise suitable logic, circuitry and/or code that may be enabled to estimate the wireless channel response for RS symbols, which may be desirable for receiver operations. The receiver operations module or circuit (RXCVR) 318 may comprise suitable logic, circuitry and/or code that may be enabled to measure and/or verify performance during receiver operations. The fast Fourier-transform (FFT) module or circuit 320 may comprise suitable logic, circuitry and/or code that may be enabled to generate a Fast Fourier Transform for an input signal. The buffering module or circuit 330 may comprise suitable logic, circuitry and/or code that may be enabled to interface with, for example, the FFT engine. The buffering module or circuit 330 may assist in, for example, dedicated processes, measurement processes, multimedia broadcast multicast services (MBMS), and/or SSS processing for hopping pattern determination. In some instances, each of the processes may be performed in parallel. The sample BW filter 332 may comprise suitable logic, circuitry and/or code that may be enabled to filter the signal at its input, and generate an output signal with limited bandwidth.

The analog-to-digital (A2D) module or circuit 334 may comprise suitable logic, circuitry and/or code that may be enabled to receive an analog RF-filtered signal and convert it to a digital signal representation at the output, with an arbitrary number of bits. The master timer 336 may comprise suitable logic, circuitry and/or code that may be enabled to provide basic timing functionality in the receiver. In some instances, the master timer 336 may count over 10 ms periods, and may be clocked at 30.72 MHz, for example. The master timer 336 may comprise a slot counter, and a sample counter. The input to the master timer 336 may be provided by an operating RF crystal, referred to as a TXCO, for example.

The common receiver part 342 may receive radio frequency signals, and process these signals. Processing may comprise FFT computation, RS symbol extraction, channel estimation and other receiver signal processing. Some timing aspects of the common receiver part 342 may be controlled by the timing part 340. For example, the symbol timing on one or more receiver subcarrier/carrier frequency, for example f1 and/or f2 as illustrated in FIG. 2, may be determined.

The RS phase discriminator 302 may receive at its input, a set of RS symbols, which may be extracted in the RS extraction module or circuit 314 to determine timing information about the RS carrying-carrier. The output of the RS phase discriminator 302 may be communicatively coupled to a first input of the adder 304. A second input of the adder 304 may be coupled to the output of the delay module or circuit 306, and the output of the adder 304 may be a weighted sum of its inputs. The delay module or circuit 306 may delay an input signal by a certain time interval, for example one or more sample periods. The delay module or circuit 306 may provide appropriate delay for the feedback signal provided to the adder 304 from the integrator 308.

An output of the adder 304, tt_loop_accum, may be communicatively coupled to a first input of the threshold module or circuit 310, and a first input of the integrator 308. A second input of the threshold module or circuit 310 may be coupled to a threshold-level defining signal. The threshold module or circuit 310 may compare a threshold signal with the tt_loop_accum signal, and generate output signals reset_cntrl and to_accum. For example, when the tt_loop_accum signal may exceed the threshold level, the reset_cntrl signal may activate and reset, for example, the integrator 308. In accordance with an embodiment of the invention, the to_accum signal, may increase at a rate that is a function of Δt, and may thus allow information about Δt to be communicated to, for example, the timing generator 312, which in turn may control the FFT input window's position in the time domain. A second input to the integrator 308 may be set to a known, constant level, for example zero. The integrator 308 may integrate one or more input signals, and the integrator 308 may be reset by the reset_cntrl signal.

The analog-to-digital (A2D) module or circuit 334 may receive an analog RF-filtered signal and convert it to a digital signal representation at the output, with an arbitrary number of bits. The A2D 334 output may be communicatively coupled to an input of the sample BW filter 332. The sample BW filter 332 may filter the signal at its input, and generate an output signal with limited bandwidth and/or attenuate certain frequency bands. The output of the sample BW filter 332 may be communicatively coupled to a first input of the buffering module or circuit 330. A second input to the buffering module or circuit 330 may be communicatively coupled to the output signal slot_strb from the timing generator 312. The buffering module or circuit 330 may interface with, for example, the FFT engine. The buffering module or circuit 330 may assist in dedicated processes, measurement processes, multimedia broadcast multicast services (MBMS), and/or SSS processing for RS PN sequence determination. In some instances, each of the processes may be performed in parallel. The output of the buffering module or circuit 330 may be communicatively coupled to the FFT module or circuit 320.

The FFT module or circuit 320 may generate a Fast Fourier Transform for an input signal communicatively coupled from the buffering module or circuit 330. Similar to the buffering module or circuit 330, the FFT module or circuit 320 may assist in signal processing for dedicated processes, measurement processes, multimedia broadcast multicast services (MBMS), and/or SSS processing for radio time framing and RS PN sequence determination. A first output of the FFT module or circuit 320 may be communicatively coupled to a first input of the RS extraction module or circuit 314. The RS extraction module or circuit 314 may extract the RS symbols from the FFT module or circuit 320 output. In some instances, it may be desirable to use a generated hopping sequence from the demodulated base station signal and/or pseudo-noise (PN) covering for RS decoding. The RS symbols extracted and output at the RS extraction module or circuit 314 may be communicatively coupled to the input of the timing part 340, and a channel estimation module or circuit 316. The hopping pattern may be fed to the RS extraction module or circuit 314 via the rs_hopping_pattern signal on a second input, as illustrated in FIG. 3A. The RS extraction module or circuit 314 timing may be controlled via a third input signal rs_strb, communicatively coupled to an output of the timing generator 312.

The timing generator 312 may generate timing signal for RS extraction, rs_strb, and slot timing, slot_strb. The signal slot_strb may be used to control FFT timing in the buffering module or circuit 330. The timing generator 312 may generate the output timing signals for timing corrections and tracking. The master timer input signal may be communicatively coupled to the master timer 336 output. The master timer 336 may provide basic timing functionality in the receiver. In some instances, the master timer 336 may count over 10 ms periods, and may be clocked at 30.72 MHz, for example. The master timer 336 may comprise a slot counter, and a sample counter. The input to the master timer 336 may be provided by an operating RF crystal, a temperature-controlled crystal oscillator (TXCO), for example.

The channel estimation module or circuit 316 may estimate the wireless channel response for RS symbols, which may be desirable for receiver operations. The channel estimation output may be communicatively coupled to the RXCVR 318. The RXCVR 318 may measure and/or verify receiver performance functionality.

FIG. 3B is a diagram illustrating phase offsets for exemplary timing offsets, in accordance with various embodiments of the invention. Referring to FIG. 3B, there is shown a timing offset plot 350 a, which may correspond to Δtg=1; a timing offset plot 350 b, which may correspond to Δtg=2; a timing offset plot 350 c, which may correspond to Δtg=3; and a timing offset plot 350 d, which may correspond to Δtg=4.

From PSS and SSS slot markers may be obtained for the received signal to within the bandwidth of the PSS processing, for example. For the FFT to equalize channel selectivity, it may be desirable that the Cyclic Prefix (CP) may cover the delay spread of the channel. It may also be desirable to minimize the value of Δtg to avoid that the sampled input to FFT processing may comprise adjacent symbols (intersymbol interference—ISI) as this may degrade performance. However, Δtg may be tracked, and may provide guard against timing shifts due to mobility, for example.

It may be shown that for Δtg unequal to 1, a phase offset may be introduced into the FFT output, Δtg=1 may correspond to no phase offset. This phase offset may be manifested by a complex multiplicative factor, z(k), applied to a subcarrier, and may be given by the following relationship, for a subcarrier k:
z(k)=e j(Δtg−1)·(k−1)·2π1N
where N may be the FFT size. When sampling the cyclic prefix, a timing offset may be manifested by a growing phase offset when indexed by tone frequency. For a RS tone, a received channel coefficient may be given by the following relationship:
hrx k =z k ·h k +n k
where hrxk may be a received channel coefficient affected by a phase offset z(k), hk may be a channel coefficient without phase offset, and nk may be a noise term. In FIG. 3B, various plots may illustrate a plurality of z(k), for different values of Δtg, where timing offset plot 350 a may correspond to Δtg=1, timing offset plot 350 b may correspond to Δtg=2, timing offset plot 350 c may correspond to Δtg=3, and timing offset plot 350 d may correspond to Δtg=4. As illustrated in FIG. 3B, timing offset may introduce linearly decreasing phase as a function of frequency.

FIG. 3C is a diagram illustrating phase offsets for exemplary timing offsets by subcarrier, in accordance with various embodiments of the invention. Referring to FIG. 3C, there is shown a timing offset plot 352 a, which may correspond to Δtg=0; a timing offset plot 352 b, which may correspond to Δtg=1 for subcarrier 512; a timing offset plot 352 c, which may correspond to Δtg=2 for subcarrier 511; and a timing offset plot 350 d, which may correspond to Δtg=3 for subcarrier 510.

For Δtg>0, the FFT may be sampled late, and a sampling timing adjustment may be desirable. As illustrated in FIG. 3C, for late sampling, timing offset may manifest phase offset across the bandwidth of the channel, as illustrated for a plurality of subcarriers by the plots 352 a-352 d. In some instances, the slope of the phase offset in function of the frequency may be linear with a positive slope for early sampled FFT, and a negative slope for late sampled FFTs, for example. An exemplary phase detector that may use adjacent RS tones per OFDM symbol may be given by the following relationship:

e k = 1 N t · all tones ( l ) , all antennas imag ( hr x l · hr x l + 6 * )
where a phase change between hrx1 and hrx1+6 (another RS tone, spaced 6 subcarriers apart, for example), may be averaged over all desirable tones, and all desirable antennas, which may be Nt terms.

FIG. 4 is a flow chart illustrating an exemplary timing acquisition and tracking process, in accordance with an embodiment of the invention. After initialization in step 402, the primary and secondary synchronization signals, (PSS) and (SSS), may be decoded in step 404. The decoding of the PSS and SSS may provide coarse timing information for frame and slot synchronization, for example. Using the timing information, the FFT block 320, for example, may generate an FFT of a received signal. From this FFT, in step 406, the RS extraction block 314, for example, may extract an RS set in the RS extraction block 314. This RS set may be fed to the timing part 340. In step 408, the timing part 340 may track Δtg using the feedback loop depicted in FIG. 3A. Since the output signal to_accum may be generated as a function of Δtg, the to_accum output signal from the threshold block 310 may carry information about Δtg to the timing generator 312. Thus, the output signal to_accum may enable tracking of the symbol timing, and adjust the timing of the receiver, for example in the timing generator 312. In step 410, the timing generator 312 may adjust the timing based on the input signal to_accum. The adjusted and tracked timing may be communicatively coupled from the timing generator 312 to the buffering block 330, where the timing of the FFT input window may be adjusted correspondingly.

In accordance with an embodiment of the invention, a method and system for a RS timing loop for OFDM symbol synchronization and tracking may comprise tracking symbol timing in an Orthogonal Frequency Division Multiplexing (OFDM) signal based on at least a reference symbol set, as described for FIG. 2 and FIG. 3A. A receiver timing, as described for FIG. 2 and FIG. 3A, may be adjusted based on at least the symbol timing.

The symbol timing may be tracked by generating an output signal as a function of a guard time Δtg in a phase discrimination feedback loop, for example timing part 340. The reference symbol (RS) set may be generated in an RS extraction module or circuit 314, from at least a fast Fourier transform of the received OFDM signal. The receiver timing may be coarsely adjusted and then finely adjusted, for example. The coarse receiver timing adjustment may be based on processing at least a primary synchronization signal and a secondary synchronization signal, as described for FIG. 3A. The reference symbol set may comprise a plurality of time-frequency slots. The plurality of time-frequency slots may change according to a frequency shift and pseudo-noise sequence that modulates the reference symbols. The OFDM signal may conform to a Universal Mobile Telecommunications Standards (UMTS) long-term evolution (LTE) signal. The adjustment of the receiver timing may be controlled via a receiver timing generator 312, for example.

Another embodiment of the invention may provide a machine-readable and/or computer-readable storage and/or medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the steps as described herein for a method and system for a reference signal (RS) timing loop for OFDM symbol synchronization and tracking.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims (20)

What is claimed is:
1. A timing acquisition and tracking system, comprising:
a timing module configured:
to compare a timing of a plurality of reference symbols within a reference symbol (RS) set associated with a symbol guard time to a reference clock signal to generate a plurality of error signals corresponding to the plurality of reference symbols,
to generate a weighted sum signal representative of a weighted integration of the plurality of error signals, and
to generate an output signal that varies as a function of the symbol guard time utilizing the weighted sum signal; and
a receiver configured to process a received signal utilizing a timing signal and to adjust the timing signal based on the output signal.
2. The timing acquisition and tracking system of claim 1, wherein the receiver comprises:
a timing generator configured to generate an RS extraction timing signal and a slot timing signal based on the output signal.
3. The timing acquisition and tracking system of claim 2, wherein the receiver further comprises:
a fast Fourier transform (FFT) module configured to perform an FFT of the received signal within an FFT sampling window to provide an FFT output signal, the FFT sampling window being based on the slot timing signal.
4. The timing acquisition and tracking system of claim 3, wherein the receiver further comprises:
an RS extraction module configured to extract the RS set from the received signal utilizing the FFT output signal and the RS extraction timing signal.
5. The timing acquisition and tracking system of claim 1, wherein the timing module comprises:
an integrator module configured to integrate the plurality of error signals to provide an integrated signal; and
an adder configured to provide the weighted sum signal by adding the plurality of error signals with the integrated signal.
6. The timing acquisition and tracking system of claim 5, wherein the timing module further comprises:
a threshold module configured to generate the output signal based on the weighted sum signal.
7. The timing acquisition and tracking system of claim 6, wherein the threshold module is further configured to generate a reset signal, and
wherein the integrator module is further configured to reset integration of the plurality of error signals in response to the reset signal.
8. The timing acquisition and tracking system of claim 7, wherein the threshold module is further configured to compare a signal level of the weighted sum signal to a threshold signal level and to generate the reset signal if the signal level is greater than or equal to the threshold signal level.
9. The timing acquisition and tracking system of claim 5, wherein the RS set is from among a plurality of RS sets corresponding to a plurality of subcarriers.
10. A timing acquisition and tracking system, comprising:
a receiver configured to decode a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) from a received signal utilizing a timing signal to extract a reference symbol (RS) set; and
a timing module configured to compare a timing of the RS set to a reference clock signal to generate an output signal which tracks a guard time of the RS set,
wherein the receiver is further configured to adjust the timing signal utilizing the output signal to process the received signal.
11. The timing acquisition and tracking system of claim 10, wherein the receiver comprises:
a timing generator configured to generate an RS extraction timing signal and a slot timing signal based on the output signal.
12. The timing acquisition and tracking system of claim 11, wherein the receiver further comprises:
a fast Fourier transform (FFT) module configured to perform an FFT of the received signal within an FFT sampling window to provide an FFT output signal, the FFT sampling window being based on the slot timing signal.
13. The timing acquisition and tracking system of claim 12, wherein the receiver further comprises:
an RS extraction module configured to extract the RS set from the received signal utilizing the FFT output signal and the RS extraction timing signal.
14. The timing acquisition and tracking system of claim 10, wherein the RS set is from among a plurality of RS sets,
wherein the timing module is further configured to compare a timing of the plurality of RS sets to the reference clock signal to generate a plurality of error signals, and
wherein the timing module comprises:
an integrator module configured to integrate the plurality of error signals to provide an integrated signal; and
an adder configured to provide a weighted sum signal representative of a weighted integration of the plurality of error signals by adding the plurality of error signals with the integrated signal.
15. The timing acquisition and tracking system of claim 14, wherein the timing module comprises:
a threshold module configured to compare a signal level of the weighted sum signal to a threshold signal level and to generate a reset signal if the signal level is greater than or equal to the threshold signal level, and
wherein the integrator module is further configured to reset integration of the plurality of error signals in response to the reset signal.
16. A timing acquisition and tracking system, comprising:
a reference symbol (RS) phase discriminator configured to compare a timing of a plurality of reference symbols within an RS set associated with a symbol guard time to a reference clock signal to generate a plurality of error signals corresponding to the plurality of reference symbols;
a phase discrimination feedback loop configured to generate a weighted sum signal representative of a weighted integration of the plurality of error signals;
a threshold block configured to generate an output signal that varies as a function of the symbol guard time utilizing the weighted sum signal; and
a timing generator configured to process a received signal utilizing a timing signal and to adjust the timing signal based on the output signal.
17. The timing acquisition and tracking system of claim 16, wherein the timing generator is further configured to generate an RS extraction timing signal and a slot timing signal based on the output signal.
18. The timing acquisition and tracking system of claim 17, further comprising:
a fast Fourier transform (FFT) module configured to perform an FFT of the received signal within an FFT sampling window to provide an FFT output signal, the FFT sampling window being based on the slot timing signal.
19. The timing acquisition and tracking system of claim 18, further comprising:
an RS extraction module configured to extract the RS set from the received signal utilizing the FFT output signal and the RS extraction timing signal.
20. The timing acquisition and tracking system of claim 16, wherein the phase discrimination feedback loop comprises:
an integrator module configured to integrate the plurality of error signals to provide an integrated signal;
an adder configured to provide the weighted sum signal by adding the plurality of error signals with the integrated signal; and
a threshold module configured to compare a signal level of the weighted sum signal to a threshold signal level, and to generate a reset signal if the signal level is greater than or equal to the threshold signal level,
wherein the integrator module is further configured to reset integration of the plurality of error signals in response to the reset signal.
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