US8810015B2 - Integrated circuit packaging system with high lead count and method of manufacture thereof - Google Patents

Integrated circuit packaging system with high lead count and method of manufacture thereof Download PDF

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US8810015B2
US8810015B2 US12/484,245 US48424509A US8810015B2 US 8810015 B2 US8810015 B2 US 8810015B2 US 48424509 A US48424509 A US 48424509A US 8810015 B2 US8810015 B2 US 8810015B2
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Prior art keywords
tiebar
outer lead
die
pad
inner leads
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US20100314731A1 (en
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Zigmund Ramirez Camacho
Henry Descalzo Bathan
Frederick Rodriguez Dahilig
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Stats Chippac Pte Ltd
STAT ChipPAC Ltd
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STAT ChipPAC Ltd
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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Definitions

  • the present invention relates generally to an integrated circuit packaging system and more particularly to a system for an integrated circuit packaging system with a peel strip and high lead count.
  • Integrated circuit packages for complex systems typically are comprised of multiple interconnected integrated circuit chips.
  • the integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide.
  • the integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.
  • the packages on which these integrated semiconductor chips are mounted include a substrate or other chip-mounting device.
  • a substrate is a leadframe.
  • Leadframes typically include an area on which an integrated circuit chip is mounted and multiple power, ground, and/or signal leads to which power, ground, and/or signal sites of the integrated semiconductor chip are electronically attached.
  • Semiconductor integrated chips may be attached to the leadframe using adhesive or any other techniques for attaching such chips to a leadframe which are commonly known to those skilled in the art.
  • the power, ground and/or signal sites on the chip may then be electrically connected to individual leads of the leadframe through techniques such as wire bonding.
  • a conventional leadframe includes a die pad, surrounded by a number of leads.
  • the leadframe is made from metal.
  • connection elements are used to connect different parts of the leadframe together.
  • the leads are usually connected by the outer frame of the leadframe.
  • a tiebar usually connects the die pad to the outer frame of the leadframe.
  • the connection elements are usually made out of the same metal as the leadframe due to the fact that the entire leadframe structure, including the connection elements, is cut out from a single piece of metal plate during a metallurgical forming process.
  • the packaging process starts with attaching an integrated circuit chip to the die pad using a conductive adhesive such as silver epoxy.
  • a conductive adhesive such as silver epoxy.
  • the conductive adhesive is cured after the die attach.
  • a wire bonding process is typically used to make electrical interconnections between the integrated circuit and the leads of the leadframe.
  • the leadframe with the integrated circuit attached is encapsulated using a mold compound.
  • a singulation process is used to cut the outer frame of the leadframe and thus separates the leads connected by the outer frame as well as separates individual semiconductor package apart.
  • the leads that extend from the die pad are still shorted together and not separated.
  • a partial sawing process is employed to separate those leads.
  • this partial sawing process creates certain problems because it makes the manufacturing process more complicated, it creates moisture pathway that introduces water moisture into the package that leads to device failures, it creates mechanical cracks in the package that leads to device failures, and it might cut too deep and damage other components of the package.
  • the present invention provides a method of manufacture of an integrated circuit packaging system including: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.
  • the present invention provides an integrated circuit packaging system including: a tiebar and an outer lead; an inner lead with a bottom surface exposed; a die wire bonded to the outer lead and the inner lead; a mold compound encapsulating the die and portions of the outer lead and the inner lead; and an outer lead outer pad at an end of the outer lead, the outer lead outer pad being coplanar with the bottom surface of the inner lead.
  • FIG. 1 is a cross-sectional view of an integrated circuit packaging system of a first embodiment of the present invention along line 1 - 1 of FIG. 2 after a stage of singulation.
  • FIG. 2 is a top view of the integrated circuit packaging system of the first embodiment of the present invention after a stage of singulation.
  • FIG. 3 is a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention along line 3 - 3 of FIG. 2 after a stage of singulation.
  • FIG. 4 is a cross-sectional view of a leadframe of the first embodiment of the present invention along line 4 - 4 of FIG. 5 after an intermediate stage of the process.
  • FIG. 5 is a top view of the leadframe of the first embodiment of the present invention after the intermediate stage of the process.
  • FIG. 6 is a cross-sectional view similar to FIG. 2 of the leadframe of the first embodiment of the present invention along line 6 - 6 of FIG. 5 after the intermediate stag of the process.
  • FIG. 7 is a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention after a wire bonding stage.
  • FIG. 8 is a cross-sectional view similar to FIG. 7 of the integrated circuit packaging system of the first embodiment of the present invention after a mold attaching stage.
  • FIG. 9 is a cross-sectional view similar to FIG. 8 of the integrated circuit packaging system of the first embodiment of the present invention after a molding stage.
  • FIG. 10 is a cross-sectional view similar to FIG. 9 of the integrated circuit packaging system of the first embodiment of the present invention after a peeling stage.
  • FIG. 11 is a cross-sectional view of an integrated circuit packaging system of a second embodiment of the present invention after a molding stage.
  • FIG. 12 is a cross-sectional view of an integrated circuit packaging system of a third embodiment of the present invention after a molding stage.
  • FIG. 13 is a cross-sectional view of an integrated circuit packaging system of a fourth embodiment of the present invention after a molding stage.
  • FIG. 14 is a cross-sectional view of an integrated circuit packaging system of a fifth embodiment of the present invention after a mold attaching stage.
  • FIG. 15 is a flow chart of a method of manufacture of an integrated circuit packaging system in a further embodiment of the present invention.
  • the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the leadframe, regardless of its orientation.
  • the term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane.
  • the term “on” means that there is direct contact among elements.
  • planar is defined as being in the same plane or flat. With regard to an unfinished leadframe the term means that the unfinished leadframe is in one plane and flat as contrasted with having different heights.
  • FIG. 1 therein is shown a cross-sectional view of an integrated circuit packaging system of a first embodiment of the present invention along line 1 - 1 of FIG. 2 after a stage of singulation.
  • the integrated circuit packaging system 100 has a die 102 attached to a die pad 104 through a die adhesive 106 .
  • the die 102 has a die bonding pad 108 .
  • the die bonding pad 108 is connected to an outer lead contact pad 111 of an outer lead 112 through a first bonding wire 114 .
  • the outer lead 112 also has an outer lead bend 117 and an outer lead outer pad 113 .
  • the die bonding pad 108 is also connected to an inner lead 110 through a second bonding wire 115 .
  • a bottom plane of the outer lead outer pad 113 has the same plane as the bottom surface of the inner lead 110 .
  • the die 102 , the die pad 104 , the die adhesive 106 , the die bonding pad 108 , the inner lead 110 , the outer lead contact pad 111 , the first bonding wire 114 , and the second bonding wire 115 are encapsulated by a mold compound 116 .
  • the bottom surfaces of the die pad 104 and the inner lead 110 are exposed and not encapsulated.
  • the inner lead 110 there are three rows of the inner lead 110 , of which, the inner lead 110 lying between the outer lead 112 and the inner lead 110 lying further away from the outer lead 112 is known as an intermediate lead.
  • the inner lead 110 is coplanar with the outer lead outer pad 113 .
  • Both the inner lead 110 and the outer lead outer pad 113 serve as the means of connection to the outside world. It has been discovered that such a configuration, compared to a conventional integrated circuit packaging system that has only one row of such lead, enhances the level of integration of the integrated circuit packaging system, increases the lead count, and provides a more versatile lead layout scheme.
  • FIG. 2 therein is shown a top view of the integrated circuit packaging system of the first embodiment of the present invention after a stage of singulation.
  • the integrated circuit packaging system 100 is shown.
  • the die 102 is shown to be attached to the die pad 104 .
  • the inner lead 110 and the outer lead 112 is also shown.
  • the inner lead 110 is shown arranged in three staggered rows of the inner lead 110 .
  • a tiebar 202 is shown adjacent the outer lead 112 .
  • the first bonding wire 114 and the mold compound 116 of FIG. 1 are not shown in FIG. 2 .
  • FIG. 3 therein is shown a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention along line 3 - 3 of FIG. 2 after a stage of singulation.
  • the die 102 is shown to be attached to the die pad 104 through the die adhesive 106 .
  • the tiebar 202 has a tiebar contact pad 201 and a tiebar bend 203 .
  • the tiebar contact pad 201 is attached to a glue 302 .
  • the adhesion element, such as the glue 302 . is exposed from the bottom side of the mold compound 116 .
  • the exposed side of the adhesion element is coplanar with the bottom side of the die pad 104 and the bottom side of the mold compound 116 .
  • the adhesion element is directly on the molding compound 116 and the tiebar contact pad 201 .
  • the adhesion element is between the tiebar contact pad 201 and the bottom side of the mold compound 116 .
  • the die 102 , the die pad 104 , the die adhesive 106 , the tiebar contact pad 201 , the tiebar bend 203 , and the glue 302 are encapsulated by the mold compound 116 .
  • the bottom surface of the glue 302 is also exposed.
  • FIG. 4 therein is shown a cross-sectional view of a leadframe 400 of the first embodiment of the present invention along line 4 - 4 of FIG. 5 after an intermediate stage of the process.
  • the leadframe 400 is shown.
  • the leadframe 400 has a peel strip 402 .
  • the die pad 104 and the inner lead 110 are attached to the peel strip 402 .
  • the peel strip 402 is typically made out of stainless steel.
  • the outer lead contact pad 111 is also shown. Both the die pad 104 and the inner lead 110 could be pre-plated.
  • FIG. 5 therein is shown a top view of the leadframe of the first embodiment of the present invention after the intermediate stage of the process.
  • the leadframe 400 is shown to have the outer lead 112 and the tiebar 202 .
  • the peel strip 402 is connected to the tiebar 202 .
  • the die pad 104 and the inner lead 110 are attached to the top of the peel strip 402 .
  • FIG. 6 therein is shown a cross-sectional view similar to FIG. 2 of the leadframe of the first embodiment of the present invention along line 6 - 6 of FIG. 5 after the intermediate stag of the process.
  • tiebar contact pad 201 is attached to the peel strip 402 through the glue 302 .
  • a designed-in amount of spring-back could be employed in the tiebar 202 to ensure the planarity of the die pad 104 and the inner lead 110 .
  • the bottom side of the adhesion element, such as the glue 302 is coplanar with the bottom side of the inner lead 110 and the peel strip 402 .
  • FIG. 7 therein is shown a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention after a wire bonding stage.
  • the die 102 is attached to the die pad 104 through the die adhesive 106 .
  • the die bonding pad 108 is connected to the outer lead contact pad 111 through the first bonding wire 114 .
  • the die bonding pad 108 is also connected to the inner lead 110 through the second bonding wire 115 .
  • FIG. 8 therein is shown a cross-sectional view similar to FIG. 7 of the integrated circuit packaging system 800 of the first embodiment of the present invention after a mold attaching stage.
  • a mold case 802 is attached to a peel strip side wall 804 of the peel strip 402 of the leadframe 400 of FIG. 5 .
  • the mold case 802 has a mold cavity 806 .
  • the die 102 , the die pad 104 , the die adhesive 106 , the inner lead 110 , a portion of the outer lead contact pad 111 , the first bonding wire 114 , and the second bonding wire 115 are situated inside the mold cavity 806 .
  • the peel strip side wall 804 is at an angle 808 with a mold case side wall 810 .
  • FIG. 9 therein is shown a cross-sectional view similar to FIG. 8 of the integrated circuit packaging system of the first embodiment of the present invention after a molding stage.
  • the mold compound 116 is added to fill in the mold cavity 806 of FIG. 8 .
  • the mold case 802 of FIG. 8 is then removed.
  • the die 102 , the die pad 104 , the die adhesive 106 , the inner lead 110 , a portion of the outer lead contact pad 111 , the first bonding wire 114 , and the second bonding wire 115 are encapsulated in the mold compound 116 .
  • FIG. 10 therein is shown a cross-sectional view similar to FIG. 9 of the integrated circuit packaging system of the first embodiment of the present invention after a peeling stage.
  • the peel strip 402 is peeled away. A singulation process ensues and results in the integrated circuit packaging system 100 of FIG. 1 .
  • the peeling process electrically separates the die pad 104 and the inner lead 110 which were previously held together by the peel strip 402 .
  • the bottom surfaces of the die pad 104 and inner lead 110 are also thus exposed for connection to outside components.
  • the current embodiment of the present invention employing the peeling process eliminates the partial sawing process conventionally employed to separate the die pad 104 and the inner lead 110 and it also eliminates all the risks and problems associated with the partial sawing. It has been discovered that the current embodiment of the present invention employing the peeling process makes the manufacturing process much simpler, eliminates the moisture pathway introduced by the partial sawing process, eliminates the mechanical cracks produced by the partial sawing process, and eliminates the deep cut created by the partial sawing process that usually leads to the damages of other components of the package.
  • the current embodiment of the present invention also makes possible a more versatile inner pad layout scheme.
  • FIG. 11 therein is shown a cross-sectional view of an integrated circuit packaging system of a second embodiment of the present invention after a molding stage.
  • an adhesive tape 1102 is used to attach the tiebar contact pad 201 to the peel strip 402 .
  • the adhesion element such as the adhesive tape 1102 , is exposed from the bottom side of the mold compound 116 and coplanar with the bottom side of the die pad 104 , the bottom side of the mold compound 116 , and the peel strip 402 .
  • the adhesion element is directly on the molding compound 116 and the tiebar contact pad 201 .
  • the adhesion element is between the tiebar contact pad 201 and the bottom side of the mold compound 116 .
  • FIG. 12 therein is shown a cross-sectional view of an integrated circuit packaging system of a third embodiment of the present invention after a molding stage.
  • a solder ball 1202 is used to attach the tiebar contact pad 201 to the peel strip 402 .
  • the adhesion element such as the solder ball 1202 , is exposed from the bottom side of the mold compound 116 and coplanar with the bottom side of the die pad 104 , the bottom side of the mold compound 116 , and the peel strip 402 .
  • the adhesion element is between the tiebar contact pad 201 and the bottom side of the mold compound 116 .
  • FIG. 13 therein is shown a cross-sectional view of an integrated circuit packaging system of a fourth embodiment of the present invention after a molding stage.
  • a metallic bond 1302 is formed between the tiebar contact pad 201 and the peel strip 402 to connect the tiebar contact pad 201 to the peel strip 402 .
  • the adhesion element, such as the metallic bond 1302 is exposed from the bottom side of the mold compound 116 .
  • FIG. 14 therein is shown a cross-sectional view of an integrated circuit packaging system of a fifth embodiment of the present invention after a molding attaching stage.
  • the peel strip 402 has a tapered peel strip side wall 1402 that is aligned with the mold case side wall 810 while in FIG. 8 the peel strip side wall 804 is at an angle 808 with the mold case side wall 810 .
  • the configuration in FIG. 8 suffers from a problem called mold seepage.
  • the fact that the peel strip side wall 804 is at an angle 808 with the mold case side wall 810 facilitates the mold compound 116 in FIG. 9 seeping through the connection between the peel strip side wall 804 and the mold case side wall 810 and form flickers of the mold compound 116 along the peel strip side wall 804 . These flickers of the mold compound 116 reduce the reliability of the integrated circuit packaging system.
  • the tapered peel strip side wall 1402 is aligned with the mold case side wall 810 and no angle exists between the tapered peel strip side wall 1402 and the mold case side wall 810 . It has been discovered that such a configuration improves the seating fit of the mold case 802 and also eliminates the mold seepage problem and increases the reliability of the integrated circuit packaging system.
  • the method 1500 includes forming a leadframe with a tiebar and an outer lead having an outer lead outer pad in a block 1502 ; forming an inner lead on a peel strip in a block 1504 ; attaching the leadframe to the peel strip around the inner lead in a block 1506 ; wire bonding a die to the outer lead and the inner lead in a block 1508 ; encapsulating the die and portions of the outer lead and the inner lead in a block 1510 ; removing the peel strip to expose a bottom surface of the inner lead in a block 1512 ; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead in a block 1514 .
  • the present invention increases lead or pin count, provides a more versatile lead layout scheme, eliminates the partial sawing that introduces risks, increases integrated circuit packaging system reliability, and simplifies the manufacturing process for an integrated circuit packaging system.
  • the present invention thus facilitates and accommodates the modern trend of semiconductor packaging of integrating more and more device functionality in an ever-shrinking footprint.
  • Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
  • the integrated circuit packaging system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving yield, increasing reliability, reducing complexity, and reducing cost of integrated circuit system.
  • the resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit package system fully compatible with conventional manufacturing processes and technologies.

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Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.

Description

TECHNICAL FIELD
The present invention relates generally to an integrated circuit packaging system and more particularly to a system for an integrated circuit packaging system with a peel strip and high lead count.
BACKGROUND ART
In the electronics industry, the tendency has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of multiple interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.
Typically, the packages on which these integrated semiconductor chips are mounted include a substrate or other chip-mounting device. One example of such a substrate is a leadframe. Leadframes typically include an area on which an integrated circuit chip is mounted and multiple power, ground, and/or signal leads to which power, ground, and/or signal sites of the integrated semiconductor chip are electronically attached. Semiconductor integrated chips may be attached to the leadframe using adhesive or any other techniques for attaching such chips to a leadframe which are commonly known to those skilled in the art. The power, ground and/or signal sites on the chip may then be electrically connected to individual leads of the leadframe through techniques such as wire bonding.
A conventional leadframe includes a die pad, surrounded by a number of leads. Usually the leadframe is made from metal. In order for the leadframe to be handled as a single piece of substrate, connection elements are used to connect different parts of the leadframe together. The leads are usually connected by the outer frame of the leadframe. A tiebar usually connects the die pad to the outer frame of the leadframe. The connection elements are usually made out of the same metal as the leadframe due to the fact that the entire leadframe structure, including the connection elements, is cut out from a single piece of metal plate during a metallurgical forming process.
The trend of the modern semiconductor industry is to integrate more and more functionally into one package. This trend requires an ever increasing number of leads to be present in the leadframe. One way of increasing the lead count of the leadframe is to form leads extending from the periphery of the die pad.
The packaging process starts with attaching an integrated circuit chip to the die pad using a conductive adhesive such as silver epoxy. The conductive adhesive is cured after the die attach. Then a wire bonding process is typically used to make electrical interconnections between the integrated circuit and the leads of the leadframe. After wire bonding, the leadframe with the integrated circuit attached is encapsulated using a mold compound.
That the leadframe after the stage of molding is still a single piece of connected metal suggests that all the leads are shorted together. A singulation process is used to cut the outer frame of the leadframe and thus separates the leads connected by the outer frame as well as separates individual semiconductor package apart. However, the leads that extend from the die pad are still shorted together and not separated. Usually a partial sawing process is employed to separate those leads. However, this partial sawing process creates certain problems because it makes the manufacturing process more complicated, it creates moisture pathway that introduces water moisture into the package that leads to device failures, it creates mechanical cracks in the package that leads to device failures, and it might cut too deep and damage other components of the package. Another problem with the partial sawing is that such a process prevents a more versatile lead layout from being realized. Usually there is only one row of leads extending from the die pad. If two rows of leads are desired, two steps of partial sawing would be required to separate them and the risks mentioned above associated with such partial sawing increase dramatically.
Thus, a need still remains for increasing the lead or pin count, providing a more versatile lead layout scheme, eliminating the partial sawing that introduces risks, and simplifying the manufacturing process for an integrated circuit package. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a method of manufacture of an integrated circuit packaging system including: forming a leadframe with a tiebar and an outer lead having an outer lead outer pad; forming an inner lead on a peel strip; attaching the leadframe to the peel strip around the inner lead; wire bonding a die to the outer lead and the inner lead; encapsulating the die and portions of the outer lead and the inner lead; removing the peel strip to expose a bottom surface of the inner lead; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead.
The present invention provides an integrated circuit packaging system including: a tiebar and an outer lead; an inner lead with a bottom surface exposed; a die wire bonded to the outer lead and the inner lead; a mold compound encapsulating the die and portions of the outer lead and the inner lead; and an outer lead outer pad at an end of the outer lead, the outer lead outer pad being coplanar with the bottom surface of the inner lead.
Certain embodiments of the invention have other steps or elements in addition to or in place of those mentioned above. The steps or element will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of an integrated circuit packaging system of a first embodiment of the present invention along line 1-1 of FIG. 2 after a stage of singulation.
FIG. 2 is a top view of the integrated circuit packaging system of the first embodiment of the present invention after a stage of singulation.
FIG. 3 is a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention along line 3-3 of FIG. 2 after a stage of singulation.
FIG. 4 is a cross-sectional view of a leadframe of the first embodiment of the present invention along line 4-4 of FIG. 5 after an intermediate stage of the process.
FIG. 5 is a top view of the leadframe of the first embodiment of the present invention after the intermediate stage of the process.
FIG. 6 is a cross-sectional view similar to FIG. 2 of the leadframe of the first embodiment of the present invention along line 6-6 of FIG. 5 after the intermediate stag of the process.
FIG. 7 is a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention after a wire bonding stage.
FIG. 8 is a cross-sectional view similar to FIG. 7 of the integrated circuit packaging system of the first embodiment of the present invention after a mold attaching stage.
FIG. 9 is a cross-sectional view similar to FIG. 8 of the integrated circuit packaging system of the first embodiment of the present invention after a molding stage.
FIG. 10 is a cross-sectional view similar to FIG. 9 of the integrated circuit packaging system of the first embodiment of the present invention after a peeling stage.
FIG. 11 is a cross-sectional view of an integrated circuit packaging system of a second embodiment of the present invention after a molding stage.
FIG. 12 is a cross-sectional view of an integrated circuit packaging system of a third embodiment of the present invention after a molding stage.
FIG. 13 is a cross-sectional view of an integrated circuit packaging system of a fourth embodiment of the present invention after a molding stage.
FIG. 14 is a cross-sectional view of an integrated circuit packaging system of a fifth embodiment of the present invention after a mold attaching stage.
FIG. 15 is a flow chart of a method of manufacture of an integrated circuit packaging system in a further embodiment of the present invention.
 BEST MODE FOR CARRYING OUT THE INVENTION
The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.
In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.
The drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the drawings FIGs. Similarly, although the views in the drawings for ease of description generally show similar orientations, this depiction in the FIGs. is arbitrary for the most part. Generally, the invention can be operated in any orientation.
Where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with similar reference numerals.
For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the leadframe, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means that there is direct contact among elements.
The term “coplanar” is defined as being in the same plane or flat. With regard to an unfinished leadframe the term means that the unfinished leadframe is in one plane and flat as contrasted with having different heights.
Referring now to FIG. 1, therein is shown a cross-sectional view of an integrated circuit packaging system of a first embodiment of the present invention along line 1-1 of FIG. 2 after a stage of singulation.
An integrated circuit packaging system 100 is shown. The integrated circuit packaging system 100 has a die 102 attached to a die pad 104 through a die adhesive 106. The die 102 has a die bonding pad 108. The die bonding pad 108 is connected to an outer lead contact pad 111 of an outer lead 112 through a first bonding wire 114. The outer lead 112 also has an outer lead bend 117 and an outer lead outer pad 113. The die bonding pad 108 is also connected to an inner lead 110 through a second bonding wire 115. A bottom plane of the outer lead outer pad 113 has the same plane as the bottom surface of the inner lead 110.
The die 102, the die pad 104, the die adhesive 106, the die bonding pad 108, the inner lead 110, the outer lead contact pad 111, the first bonding wire 114, and the second bonding wire 115 are encapsulated by a mold compound 116. The bottom surfaces of the die pad 104 and the inner lead 110 are exposed and not encapsulated.
In the current embodiment of the present invention, there are three rows of the inner lead 110, of which, the inner lead 110 lying between the outer lead 112 and the inner lead 110 lying further away from the outer lead 112 is known as an intermediate lead. The inner lead 110 is coplanar with the outer lead outer pad 113. Both the inner lead 110 and the outer lead outer pad 113 serve as the means of connection to the outside world. It has been discovered that such a configuration, compared to a conventional integrated circuit packaging system that has only one row of such lead, enhances the level of integration of the integrated circuit packaging system, increases the lead count, and provides a more versatile lead layout scheme.
Referring now to FIG. 2, therein is shown a top view of the integrated circuit packaging system of the first embodiment of the present invention after a stage of singulation.
The integrated circuit packaging system 100 is shown. The die 102 is shown to be attached to the die pad 104. The inner lead 110 and the outer lead 112 is also shown. The inner lead 110 is shown arranged in three staggered rows of the inner lead 110. A tiebar 202 is shown adjacent the outer lead 112. For the purpose of a clearer view, the first bonding wire 114 and the mold compound 116 of FIG. 1 are not shown in FIG. 2.
Referring now to FIG. 3, therein is shown a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention along line 3-3 of FIG. 2 after a stage of singulation.
The die 102 is shown to be attached to the die pad 104 through the die adhesive 106. The tiebar 202 has a tiebar contact pad 201 and a tiebar bend 203. The tiebar contact pad 201 is attached to a glue 302. The adhesion element, such as the glue 302. is exposed from the bottom side of the mold compound 116. The exposed side of the adhesion element is coplanar with the bottom side of the die pad 104 and the bottom side of the mold compound 116. The adhesion element is directly on the molding compound 116 and the tiebar contact pad 201. The adhesion element is between the tiebar contact pad 201 and the bottom side of the mold compound 116.
The die 102, the die pad 104, the die adhesive 106, the tiebar contact pad 201, the tiebar bend 203, and the glue 302 are encapsulated by the mold compound 116. The bottom surface of the glue 302 is also exposed.
Referring now to FIG. 4, therein is shown a cross-sectional view of a leadframe 400 of the first embodiment of the present invention along line 4-4 of FIG. 5 after an intermediate stage of the process.
The leadframe 400 is shown. The leadframe 400 has a peel strip 402. The die pad 104 and the inner lead 110 are attached to the peel strip 402. The peel strip 402 is typically made out of stainless steel. The outer lead contact pad 111 is also shown. Both the die pad 104 and the inner lead 110 could be pre-plated.
Referring now to FIG. 5, therein is shown a top view of the leadframe of the first embodiment of the present invention after the intermediate stage of the process.
The leadframe 400 is shown to have the outer lead 112 and the tiebar 202. The peel strip 402 is connected to the tiebar 202. The die pad 104 and the inner lead 110 are attached to the top of the peel strip 402.
Referring now to FIG. 6, therein is shown a cross-sectional view similar to FIG. 2 of the leadframe of the first embodiment of the present invention along line 6-6 of FIG. 5 after the intermediate stag of the process.
It is shown that the tiebar contact pad 201 is attached to the peel strip 402 through the glue 302. A designed-in amount of spring-back could be employed in the tiebar 202 to ensure the planarity of the die pad 104 and the inner lead 110. The bottom side of the adhesion element, such as the glue 302, is coplanar with the bottom side of the inner lead 110 and the peel strip 402.
Referring now to FIG. 7, therein is shown a cross-sectional view of the integrated circuit packaging system of the first embodiment of the present invention after a wire bonding stage.
The die 102 is attached to the die pad 104 through the die adhesive 106. The die bonding pad 108 is connected to the outer lead contact pad 111 through the first bonding wire 114. The die bonding pad 108 is also connected to the inner lead 110 through the second bonding wire 115.
Referring now to FIG. 8, therein is shown a cross-sectional view similar to FIG. 7 of the integrated circuit packaging system 800 of the first embodiment of the present invention after a mold attaching stage.
A mold case 802 is attached to a peel strip side wall 804 of the peel strip 402 of the leadframe 400 of FIG. 5. The mold case 802 has a mold cavity 806. The die 102, the die pad 104, the die adhesive 106, the inner lead 110, a portion of the outer lead contact pad 111, the first bonding wire 114, and the second bonding wire 115 are situated inside the mold cavity 806. The peel strip side wall 804 is at an angle 808 with a mold case side wall 810.
Referring now to FIG. 9, therein is shown a cross-sectional view similar to FIG. 8 of the integrated circuit packaging system of the first embodiment of the present invention after a molding stage.
The mold compound 116 is added to fill in the mold cavity 806 of FIG. 8. The mold case 802 of FIG. 8 is then removed. The die 102, the die pad 104, the die adhesive 106, the inner lead 110, a portion of the outer lead contact pad 111, the first bonding wire 114, and the second bonding wire 115 are encapsulated in the mold compound 116.
Referring now to FIG. 10, therein is shown a cross-sectional view similar to FIG. 9 of the integrated circuit packaging system of the first embodiment of the present invention after a peeling stage.
The peel strip 402 is peeled away. A singulation process ensues and results in the integrated circuit packaging system 100 of FIG. 1.
The peeling process electrically separates the die pad 104 and the inner lead 110 which were previously held together by the peel strip 402. The bottom surfaces of the die pad 104 and inner lead 110 are also thus exposed for connection to outside components.
The current embodiment of the present invention employing the peeling process eliminates the partial sawing process conventionally employed to separate the die pad 104 and the inner lead 110 and it also eliminates all the risks and problems associated with the partial sawing. It has been discovered that the current embodiment of the present invention employing the peeling process makes the manufacturing process much simpler, eliminates the moisture pathway introduced by the partial sawing process, eliminates the mechanical cracks produced by the partial sawing process, and eliminates the deep cut created by the partial sawing process that usually leads to the damages of other components of the package.
The current embodiment of the present invention also makes possible a more versatile inner pad layout scheme. There are three rows of the inner lead 110 shown. It is very easy to introduce more than three rows of the inner lead 110 without incurring any additional risks usually accompanying the conventional partial sawing process. It has been discovered that such a configuration enhances the level of integration sophistication of the integrated circuit packaging system and increase the number of functionality in a single package.
Referring now to FIG. 11, therein is shown a cross-sectional view of an integrated circuit packaging system of a second embodiment of the present invention after a molding stage.
In the current embodiment of the present invention, instead of using the glue 302 in FIG. 3 to attach the tiebar contact pad 201 to the peel strip 402, an adhesive tape 1102 is used to attach the tiebar contact pad 201 to the peel strip 402. The adhesion element, such as the adhesive tape 1102, is exposed from the bottom side of the mold compound 116 and coplanar with the bottom side of the die pad 104, the bottom side of the mold compound 116, and the peel strip 402. The adhesion element is directly on the molding compound 116 and the tiebar contact pad 201. The adhesion element is between the tiebar contact pad 201 and the bottom side of the mold compound 116.
Referring now to FIG. 12, therein is shown a cross-sectional view of an integrated circuit packaging system of a third embodiment of the present invention after a molding stage.
In the current embodiment of the present invention, instead of using the glue 302 in FIG. 3 to attach the tiebar contact pad 201 to the peel strip 402, a solder ball 1202 is used to attach the tiebar contact pad 201 to the peel strip 402. The adhesion element, such as the solder ball 1202, is exposed from the bottom side of the mold compound 116 and coplanar with the bottom side of the die pad 104, the bottom side of the mold compound 116, and the peel strip 402. The adhesion element is between the tiebar contact pad 201 and the bottom side of the mold compound 116.
Referring now to FIG. 13, therein is shown a cross-sectional view of an integrated circuit packaging system of a fourth embodiment of the present invention after a molding stage.
In the current embodiment of the present invention, instead of using the glue 302 in FIG. 3 to attach the tiebar contact pad 201 to the peel strip 402, a metallic bond 1302 is formed between the tiebar contact pad 201 and the peel strip 402 to connect the tiebar contact pad 201 to the peel strip 402. The adhesion element, such as the metallic bond 1302, is exposed from the bottom side of the mold compound 116.
Referring now to FIG. 14, therein is shown a cross-sectional view of an integrated circuit packaging system of a fifth embodiment of the present invention after a molding attaching stage.
Compared to FIG. 8, the peel strip 402 has a tapered peel strip side wall 1402 that is aligned with the mold case side wall 810 while in FIG. 8 the peel strip side wall 804 is at an angle 808 with the mold case side wall 810.
The configuration in FIG. 8 suffers from a problem called mold seepage. The fact that the peel strip side wall 804 is at an angle 808 with the mold case side wall 810 facilitates the mold compound 116 in FIG. 9 seeping through the connection between the peel strip side wall 804 and the mold case side wall 810 and form flickers of the mold compound 116 along the peel strip side wall 804. These flickers of the mold compound 116 reduce the reliability of the integrated circuit packaging system.
In the current embodiment of the present invention, the tapered peel strip side wall 1402 is aligned with the mold case side wall 810 and no angle exists between the tapered peel strip side wall 1402 and the mold case side wall 810. It has been discovered that such a configuration improves the seating fit of the mold case 802 and also eliminates the mold seepage problem and increases the reliability of the integrated circuit packaging system.
Referring now to FIG. 15, therein is shown a flow chart of a method 1500 of manufacture of an integrated circuit packaging system in a further embodiment of the present invention. The method 1500 includes forming a leadframe with a tiebar and an outer lead having an outer lead outer pad in a block 1502; forming an inner lead on a peel strip in a block 1504; attaching the leadframe to the peel strip around the inner lead in a block 1506; wire bonding a die to the outer lead and the inner lead in a block 1508; encapsulating the die and portions of the outer lead and the inner lead in a block 1510; removing the peel strip to expose a bottom surface of the inner lead in a block 1512; and removing the leadframe to have the outer lead outer pad of the outer lead coplanar with the bottom surface of the inner lead in a block 1514.
It is discovered that the present invention increases lead or pin count, provides a more versatile lead layout scheme, eliminates the partial sawing that introduces risks, increases integrated circuit packaging system reliability, and simplifies the manufacturing process for an integrated circuit packaging system. The present invention thus facilitates and accommodates the modern trend of semiconductor packaging of integrating more and more device functionality in an ever-shrinking footprint.
Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance.
These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level.
Thus, it has been discovered that the integrated circuit packaging system of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for improving yield, increasing reliability, reducing complexity, and reducing cost of integrated circuit system. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing integrated circuit package system fully compatible with conventional manufacturing processes and technologies.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.

Claims (18)

What is claimed is:
1. A method of manufacture of an integrated circuit packaging system comprising:
forming a leadframe with a tiebar having a tiebar contact pad and an outer lead having an outer lead outer pad;
forming inner leads arranged in staggered rows on a peel strip;
attaching the leadframe to the peel strip around the inner leads;
wire bonding a die to the outer lead and the inner leads;
forming an adhesion element directly on the tiebar contact pad and between the tiebar contact pad and the peel strip;
encapsulating the die and portions of the outer lead and the inner leads with a mold case having a mold case sidewall to form a mold compound, the mold case side wall being aligned with a tapered peel strip side wall without any angles therebetween;
removing the peel strip to expose a bottom surface of the inner lead and a portion of the adhesion element wherein the portion of the adhesion element is coplanar with the mold compound; and
removing the leadframe to have a bottom plane of the outer lead outer pad having the same plane as the bottom surface of the inner leads.
2. The method as claimed in claim 1 further comprising:
forming a die pad on the peel strip; and
attaching the die to the die pad.
3. The method as claimed in claim 1 further comprising forming an intermediate lead on the peel strip between the outer lead and the inner leads lying further away from the outer lead.
4. The method as claimed in claim 1 wherein forming the leadframe includes forming the tiebar with the tiebar contact pad at the end thereof and attaching the leadframe to the peel strip includes attaching the leadframe by the tiebar contact pad thereof.
5. The method as claimed in claim 1 wherein the mold compound having an exposed surface coplanar with the bottom of the inner leads.
6. A method of manufacture of an integrated circuit packaging system comprising:
forming a leadframe with a tiebar having a tiebar contact pad and an outer lead having an outer lead outer pad;
forming inner leads arranged in staggered rows on a peel strip;
attaching the leadframe to the peel strip around the inner leads by the tiebar contact pad at the end of the tiebar;
forming an adhesion element directly on the tiebar contact pad and between the tiebar contact pad and the peel strip;
wire bonding a die to the outer lead and the inner leads;
encapsulating the die and portions of the outer lead and the inner leads with a mold case having a mold case sidewall to form a mold compound, the mold case side wall being aligned with a tapered peel strip side wall without any angles therebetween;
removing the peel strip to expose a bottom surface of the inner lead and a portion of the adhesion element wherein the portion of the adhesion element is coplanar with the mold compound; and
removing the leadframe to have a bottom plane of the outer lead outer pad having the same plane as the bottom surface of the inner leads.
7. The method as claimed in claim 6 wherein attaching the leadframe includes connecting the tiebar contact pad to the peel strip with the adhesion element where the adhesion element is a glue, an adhesive tape, or a solder ball.
8. The method as claimed in claim 6 wherein forming the adhesion element includes forming a metallic bond between the tiebar contact pad and the peel strip.
9. An integrated circuit packaging system comprising:
a tiebar having a tiebar contact pad;
an outer lead adjacent the tiebar; inner leads arranged in staggered rows with a bottom surface exposed;
a die wire bonded to the outer lead and the inner leads;
a mold compound encapsulating the die and portions of the outer lead and the inner leads, the mold compound having a tapered profile from the outer lead directly to the inner leads;
an adhesion element directly on the tiebar contact pad, a portion of the adhesion element exposed from and coplanar with a bottom side of the mold compound, and the adhesion element between the tiebar contact pad and the bottom side of the mold compound; and
wherein:
the outer lead has an outer lead outer pad at an end of the outer lead, and a bottom plane of the outer lead outer pad having the same plane as the bottom surface of the inner leads.
10. The system as claimed in claim 9 further comprising a die pad, the die being attached to the die pad.
11. The system as claimed in claim 9 further comprising an intermediate lead between the outer lead and the inner leads lying further away from the outer lead.
12. The system as claimed in claim 9 wherein the tiebar has a designed-in amount of spring-back.
13. The system as claimed in claim 9 wherein the mold compound has an exposed surface coplanar with the bottom of the inner leads.
14. The system as claimed in claim 9 wherein the tiebar has the tiebar contact pad at the end of the tiebar.
15. The system as claimed in claim 14 wherein the adhesion element is a glue, an adhesive tape, or a solder ball.
16. The system as claimed in claim 14 wherein the adhesion is a metallic bond directly on the tiebar contact pad.
17. The system as claimed in claim 14 wherein a die pad or the inner leads are pre-plated.
18. The system as claimed in claim 14 wherein the die is connected to an outer lead contact pad of the outer lead with a first bonding wire.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160276555A1 (en) * 2015-03-18 2016-09-22 Toyoda Gosei Co., Ltd. Light emitting device manufacturing method and light emitting device
US20160307693A1 (en) * 2015-04-16 2016-10-20 Samsung Electro-Mechanics Co., Ltd. Electronic component and manufacturing method thereof
US20170301612A1 (en) * 2016-04-14 2017-10-19 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US20210249306A1 (en) * 2019-08-05 2021-08-12 Texas Instruments Incorporated Semiconductor die singulation
US11417541B2 (en) * 2019-08-27 2022-08-16 Nxp Usa, Inc. Protection from metal migration on IC packages

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101937886B (en) * 2009-06-30 2012-06-27 国碁电子(中山)有限公司 Thin chip package structure and method
KR101718321B1 (en) * 2014-12-23 2017-03-21 인텔 코포레이션 Integrated package design with wire leads for package-on-package product
US10804185B2 (en) * 2015-12-31 2020-10-13 Texas Instruments Incorporated Integrated circuit chip with a vertical connector
US10128169B1 (en) 2017-05-12 2018-11-13 Stmicroelectronics, Inc. Package with backside protective layer during molding to prevent mold flashing failure
DE102019120886A1 (en) * 2019-08-02 2021-02-04 Infineon Technologies Ag Semiconductor package with a cavity in its package body

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US6008528A (en) * 1997-11-13 1999-12-28 Texas Instruments Incorporated Semiconductor lead frame with channel beam tie bar
US6072239A (en) 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
US20020048948A1 (en) * 2000-08-09 2002-04-25 Kostat Semiconductor Co., Ltd. Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US7057280B2 (en) 1998-11-20 2006-06-06 Amkor Technology, Inc. Leadframe having lead locks to secure leads to encapsulant
US7067908B2 (en) 1999-10-15 2006-06-27 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US7170150B2 (en) 2001-03-27 2007-01-30 Amkor Technology, Inc. Lead frame for semiconductor package
US20070284733A1 (en) * 2006-06-08 2007-12-13 Advanced Interconnect Technologies Limited, A Corporation Of Mauritius. Method of making thermally enhanced substrate-base package
US7323765B2 (en) 2004-10-13 2008-01-29 Atmel Corporation Die attach paddle for mounting integrated circuit die
US7354796B2 (en) 2003-01-21 2008-04-08 Siliconware Precision Industries Co., Ltd. Method for fabricating semiconductor package free of substrate
US20080157401A1 (en) * 2006-12-30 2008-07-03 Kim Ohsug Integrated circuit package with top pad
US7411289B1 (en) 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US20090283878A1 (en) * 2008-05-19 2009-11-19 Powertech Technology Inc. Lead-on-chip semiconductor package and leadframe for the package
US20090302442A1 (en) * 2008-05-30 2009-12-10 Zigmund Ramirez Camacho Integrated circuit packaging system with isolated pads and method of manufacture thereof
US7968998B1 (en) * 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US6072239A (en) 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
US6008528A (en) * 1997-11-13 1999-12-28 Texas Instruments Incorporated Semiconductor lead frame with channel beam tie bar
US7057280B2 (en) 1998-11-20 2006-06-06 Amkor Technology, Inc. Leadframe having lead locks to secure leads to encapsulant
US7067908B2 (en) 1999-10-15 2006-06-27 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US20020048948A1 (en) * 2000-08-09 2002-04-25 Kostat Semiconductor Co., Ltd. Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US7170150B2 (en) 2001-03-27 2007-01-30 Amkor Technology, Inc. Lead frame for semiconductor package
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6876068B1 (en) 2002-09-09 2005-04-05 Amkor Technology, Inc Semiconductor package with increased number of input and output pins
US7211471B1 (en) 2002-09-09 2007-05-01 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US7354796B2 (en) 2003-01-21 2008-04-08 Siliconware Precision Industries Co., Ltd. Method for fabricating semiconductor package free of substrate
US7411289B1 (en) 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US7323765B2 (en) 2004-10-13 2008-01-29 Atmel Corporation Die attach paddle for mounting integrated circuit die
US20070284733A1 (en) * 2006-06-08 2007-12-13 Advanced Interconnect Technologies Limited, A Corporation Of Mauritius. Method of making thermally enhanced substrate-base package
US7968998B1 (en) * 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US20080157401A1 (en) * 2006-12-30 2008-07-03 Kim Ohsug Integrated circuit package with top pad
US20090283878A1 (en) * 2008-05-19 2009-11-19 Powertech Technology Inc. Lead-on-chip semiconductor package and leadframe for the package
US20090302442A1 (en) * 2008-05-30 2009-12-10 Zigmund Ramirez Camacho Integrated circuit packaging system with isolated pads and method of manufacture thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
U.S. Appl. No. 12/467,146, May 15, 2009, Camacho et al.

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160276555A1 (en) * 2015-03-18 2016-09-22 Toyoda Gosei Co., Ltd. Light emitting device manufacturing method and light emitting device
US20160307693A1 (en) * 2015-04-16 2016-10-20 Samsung Electro-Mechanics Co., Ltd. Electronic component and manufacturing method thereof
US20170301612A1 (en) * 2016-04-14 2017-10-19 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US10090229B2 (en) * 2016-04-14 2018-10-02 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US20210249306A1 (en) * 2019-08-05 2021-08-12 Texas Instruments Incorporated Semiconductor die singulation
US11881434B2 (en) * 2019-08-05 2024-01-23 Texas Instruments Incorporated Semiconductor die singulation
US11417541B2 (en) * 2019-08-27 2022-08-16 Nxp Usa, Inc. Protection from metal migration on IC packages

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